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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / plat-omap / mcbsp.c
blobebb210e6605a7c5f10b84e3a7e82c413808768fb
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/slab.h>
27
28 #include <plat/dma.h>
29 #include <plat/mcbsp.h>
30
31 #include "../mach-omap2/cm-regbits-34xx.h"
32
33 struct omap_mcbsp **mcbsp_ptr;
34 int omap_mcbsp_count, omap_mcbsp_cache_size;
35
36 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
37 {
38 if (cpu_class_is_omap1()) {
39 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
40 __raw_writew((u16)val, mcbsp->io_base + reg);
41 } else if (cpu_is_omap2420()) {
42 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
43 __raw_writew((u16)val, mcbsp->io_base + reg);
44 } else {
45 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
46 __raw_writel(val, mcbsp->io_base + reg);
47 }
48 }
49
50 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
51 {
52 if (cpu_class_is_omap1()) {
53 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
54 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
55 } else if (cpu_is_omap2420()) {
56 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
57 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
58 } else {
59 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
60 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
61 }
62 }
63
64 #ifdef CONFIG_ARCH_OMAP3
65 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
66 {
67 __raw_writel(val, mcbsp->st_data->io_base_st + reg);
68 }
69
70 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
71 {
72 return __raw_readl(mcbsp->st_data->io_base_st + reg);
73 }
74 #endif
75
76 #define MCBSP_READ(mcbsp, reg) \
77 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
78 #define MCBSP_WRITE(mcbsp, reg, val) \
79 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
80 #define MCBSP_READ_CACHE(mcbsp, reg) \
81 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
82
83 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
84 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
85
86 #define MCBSP_ST_READ(mcbsp, reg) \
87 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
89 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
90
91 static void omap_mcbsp_dump_reg(u8 id)
92 {
93 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
94
95 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
96 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
97 MCBSP_READ(mcbsp, DRR2));
98 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
99 MCBSP_READ(mcbsp, DRR1));
100 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
101 MCBSP_READ(mcbsp, DXR2));
102 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
103 MCBSP_READ(mcbsp, DXR1));
104 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
105 MCBSP_READ(mcbsp, SPCR2));
106 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
107 MCBSP_READ(mcbsp, SPCR1));
108 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
109 MCBSP_READ(mcbsp, RCR2));
110 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
111 MCBSP_READ(mcbsp, RCR1));
112 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
113 MCBSP_READ(mcbsp, XCR2));
114 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
115 MCBSP_READ(mcbsp, XCR1));
116 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
117 MCBSP_READ(mcbsp, SRGR2));
118 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
119 MCBSP_READ(mcbsp, SRGR1));
120 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
121 MCBSP_READ(mcbsp, PCR0));
122 dev_dbg(mcbsp->dev, "***********************\n");
123 }
124
125 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
126 {
127 struct omap_mcbsp *mcbsp_tx = dev_id;
128 u16 irqst_spcr2;
129
130 irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
131 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
132
133 if (irqst_spcr2 & XSYNC_ERR) {
134 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
135 irqst_spcr2);
136 /* Writing zero to XSYNC_ERR clears the IRQ */
137 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
138 } else {
139 complete(&mcbsp_tx->tx_irq_completion);
140 }
141
142 return IRQ_HANDLED;
143 }
144
145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
146 {
147 struct omap_mcbsp *mcbsp_rx = dev_id;
148 u16 irqst_spcr1;
149
150 irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
151 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
152
153 if (irqst_spcr1 & RSYNC_ERR) {
154 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
155 irqst_spcr1);
156 /* Writing zero to RSYNC_ERR clears the IRQ */
157 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
158 } else {
159 complete(&mcbsp_rx->rx_irq_completion);
160 }
161
162 return IRQ_HANDLED;
163 }
164
165 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
166 {
167 struct omap_mcbsp *mcbsp_dma_tx = data;
168
169 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
170 MCBSP_READ(mcbsp_dma_tx, SPCR2));
171
172 /* We can free the channels */
173 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
174 mcbsp_dma_tx->dma_tx_lch = -1;
175
176 complete(&mcbsp_dma_tx->tx_dma_completion);
177 }
178
179 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
180 {
181 struct omap_mcbsp *mcbsp_dma_rx = data;
182
183 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
184 MCBSP_READ(mcbsp_dma_rx, SPCR2));
185
186 /* We can free the channels */
187 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
188 mcbsp_dma_rx->dma_rx_lch = -1;
189
190 complete(&mcbsp_dma_rx->rx_dma_completion);
191 }
192
193 /*
194 * omap_mcbsp_config simply write a config to the
195 * appropriate McBSP.
196 * You either call this function or set the McBSP registers
197 * by yourself before calling omap_mcbsp_start().
198 */
199 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
200 {
201 struct omap_mcbsp *mcbsp;
202
203 if (!omap_mcbsp_check_valid_id(id)) {
204 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
205 return;
206 }
207 mcbsp = id_to_mcbsp_ptr(id);
208
209 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
210 mcbsp->id, mcbsp->phys_base);
211
212 /* We write the given config */
213 MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
214 MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
215 MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
216 MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
217 MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
218 MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
219 MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
220 MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
221 MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
222 MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
223 MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
224 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
225 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
226 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
227 }
228 }
229 EXPORT_SYMBOL(omap_mcbsp_config);
230
231 #ifdef CONFIG_ARCH_OMAP3
232 static void omap_st_on(struct omap_mcbsp *mcbsp)
233 {
234 unsigned int w;
235
236 /*
237 * Sidetone uses McBSP ICLK - which must not idle when sidetones
238 * are enabled or sidetones start sounding ugly.
239 */
240 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
241 w &= ~(1 << (mcbsp->id - 2));
242 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
243
244 /* Enable McBSP Sidetone */
245 w = MCBSP_READ(mcbsp, SSELCR);
246 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
247
248 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
249 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
250
251 /* Enable Sidetone from Sidetone Core */
252 w = MCBSP_ST_READ(mcbsp, SSELCR);
253 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
254 }
255
256 static void omap_st_off(struct omap_mcbsp *mcbsp)
257 {
258 unsigned int w;
259
260 w = MCBSP_ST_READ(mcbsp, SSELCR);
261 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
262
263 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
264 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
265
266 w = MCBSP_READ(mcbsp, SSELCR);
267 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
268
269 w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
270 w |= 1 << (mcbsp->id - 2);
271 cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
272 }
273
274 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
275 {
276 u16 val, i;
277
278 val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
279 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
280
281 val = MCBSP_ST_READ(mcbsp, SSELCR);
282
283 if (val & ST_COEFFWREN)
284 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
285
286 MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
287
288 for (i = 0; i < 128; i++)
289 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
290
291 i = 0;
292
293 val = MCBSP_ST_READ(mcbsp, SSELCR);
294 while (!(val & ST_COEFFWRDONE) && (++i < 1000))
295 val = MCBSP_ST_READ(mcbsp, SSELCR);
296
297 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
298
299 if (i == 1000)
300 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
301 }
302
303 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
304 {
305 u16 w;
306 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
307
308 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
309 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
310
311 w = MCBSP_ST_READ(mcbsp, SSELCR);
312
313 MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
314 ST_CH1GAIN(st_data->ch1gain));
315 }
316
317 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
318 {
319 struct omap_mcbsp *mcbsp;
320 struct omap_mcbsp_st_data *st_data;
321 int ret = 0;
322
323 if (!omap_mcbsp_check_valid_id(id)) {
324 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
325 return -ENODEV;
326 }
327
328 mcbsp = id_to_mcbsp_ptr(id);
329 st_data = mcbsp->st_data;
330
331 if (!st_data)
332 return -ENOENT;
333
334 spin_lock_irq(&mcbsp->lock);
335 if (channel == 0)
336 st_data->ch0gain = chgain;
337 else if (channel == 1)
338 st_data->ch1gain = chgain;
339 else
340 ret = -EINVAL;
341
342 if (st_data->enabled)
343 omap_st_chgain(mcbsp);
344 spin_unlock_irq(&mcbsp->lock);
345
346 return ret;
347 }
348 EXPORT_SYMBOL(omap_st_set_chgain);
349
350 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
351 {
352 struct omap_mcbsp *mcbsp;
353 struct omap_mcbsp_st_data *st_data;
354 int ret = 0;
355
356 if (!omap_mcbsp_check_valid_id(id)) {
357 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
358 return -ENODEV;
359 }
360
361 mcbsp = id_to_mcbsp_ptr(id);
362 st_data = mcbsp->st_data;
363
364 if (!st_data)
365 return -ENOENT;
366
367 spin_lock_irq(&mcbsp->lock);
368 if (channel == 0)
369 *chgain = st_data->ch0gain;
370 else if (channel == 1)
371 *chgain = st_data->ch1gain;
372 else
373 ret = -EINVAL;
374 spin_unlock_irq(&mcbsp->lock);
375
376 return ret;
377 }
378 EXPORT_SYMBOL(omap_st_get_chgain);
379
380 static int omap_st_start(struct omap_mcbsp *mcbsp)
381 {
382 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
383
384 if (st_data && st_data->enabled && !st_data->running) {
385 omap_st_fir_write(mcbsp, st_data->taps);
386 omap_st_chgain(mcbsp);
387
388 if (!mcbsp->free) {
389 omap_st_on(mcbsp);
390 st_data->running = 1;
391 }
392 }
393
394 return 0;
395 }
396
397 int omap_st_enable(unsigned int id)
398 {
399 struct omap_mcbsp *mcbsp;
400 struct omap_mcbsp_st_data *st_data;
401
402 if (!omap_mcbsp_check_valid_id(id)) {
403 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
404 return -ENODEV;
405 }
406
407 mcbsp = id_to_mcbsp_ptr(id);
408 st_data = mcbsp->st_data;
409
410 if (!st_data)
411 return -ENODEV;
412
413 spin_lock_irq(&mcbsp->lock);
414 st_data->enabled = 1;
415 omap_st_start(mcbsp);
416 spin_unlock_irq(&mcbsp->lock);
417
418 return 0;
419 }
420 EXPORT_SYMBOL(omap_st_enable);
421
422 static int omap_st_stop(struct omap_mcbsp *mcbsp)
423 {
424 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
425
426 if (st_data && st_data->running) {
427 if (!mcbsp->free) {
428 omap_st_off(mcbsp);
429 st_data->running = 0;
430 }
431 }
432
433 return 0;
434 }
435
436 int omap_st_disable(unsigned int id)
437 {
438 struct omap_mcbsp *mcbsp;
439 struct omap_mcbsp_st_data *st_data;
440 int ret = 0;
441
442 if (!omap_mcbsp_check_valid_id(id)) {
443 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
444 return -ENODEV;
445 }
446
447 mcbsp = id_to_mcbsp_ptr(id);
448 st_data = mcbsp->st_data;
449
450 if (!st_data)
451 return -ENODEV;
452
453 spin_lock_irq(&mcbsp->lock);
454 omap_st_stop(mcbsp);
455 st_data->enabled = 0;
456 spin_unlock_irq(&mcbsp->lock);
457
458 return ret;
459 }
460 EXPORT_SYMBOL(omap_st_disable);
461
462 int omap_st_is_enabled(unsigned int id)
463 {
464 struct omap_mcbsp *mcbsp;
465 struct omap_mcbsp_st_data *st_data;
466
467 if (!omap_mcbsp_check_valid_id(id)) {
468 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
469 return -ENODEV;
470 }
471
472 mcbsp = id_to_mcbsp_ptr(id);
473 st_data = mcbsp->st_data;
474
475 if (!st_data)
476 return -ENODEV;
477
478
479 return st_data->enabled;
480 }
481 EXPORT_SYMBOL(omap_st_is_enabled);
482
483 /*
484 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
485 * The threshold parameter is 1 based, and it is converted (threshold - 1)
486 * for the THRSH2 register.
487 */
488 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
489 {
490 struct omap_mcbsp *mcbsp;
491
492 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
493 return;
494
495 if (!omap_mcbsp_check_valid_id(id)) {
496 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
497 return;
498 }
499 mcbsp = id_to_mcbsp_ptr(id);
500
501 if (threshold && threshold <= mcbsp->max_tx_thres)
502 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
503 }
504 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
505
506 /*
507 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
508 * The threshold parameter is 1 based, and it is converted (threshold - 1)
509 * for the THRSH1 register.
510 */
511 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
512 {
513 struct omap_mcbsp *mcbsp;
514
515 if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
516 return;
517
518 if (!omap_mcbsp_check_valid_id(id)) {
519 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
520 return;
521 }
522 mcbsp = id_to_mcbsp_ptr(id);
523
524 if (threshold && threshold <= mcbsp->max_rx_thres)
525 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
526 }
527 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
528
529 /*
530 * omap_mcbsp_get_max_tx_thres just return the current configured
531 * maximum threshold for transmission
532 */
533 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
534 {
535 struct omap_mcbsp *mcbsp;
536
537 if (!omap_mcbsp_check_valid_id(id)) {
538 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
539 return -ENODEV;
540 }
541 mcbsp = id_to_mcbsp_ptr(id);
542
543 return mcbsp->max_tx_thres;
544 }
545 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
546
547 /*
548 * omap_mcbsp_get_max_rx_thres just return the current configured
549 * maximum threshold for reception
550 */
551 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
552 {
553 struct omap_mcbsp *mcbsp;
554
555 if (!omap_mcbsp_check_valid_id(id)) {
556 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
557 return -ENODEV;
558 }
559 mcbsp = id_to_mcbsp_ptr(id);
560
561 return mcbsp->max_rx_thres;
562 }
563 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
564
565 u16 omap_mcbsp_get_fifo_size(unsigned int id)
566 {
567 struct omap_mcbsp *mcbsp;
568
569 if (!omap_mcbsp_check_valid_id(id)) {
570 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
571 return -ENODEV;
572 }
573 mcbsp = id_to_mcbsp_ptr(id);
574
575 return mcbsp->pdata->buffer_size;
576 }
577 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
578
579 /*
580 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
581 */
582 u16 omap_mcbsp_get_tx_delay(unsigned int id)
583 {
584 struct omap_mcbsp *mcbsp;
585 u16 buffstat;
586
587 if (!omap_mcbsp_check_valid_id(id)) {
588 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
589 return -ENODEV;
590 }
591 mcbsp = id_to_mcbsp_ptr(id);
592
593 /* Returns the number of free locations in the buffer */
594 buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
595
596 /* Number of slots are different in McBSP ports */
597 return mcbsp->pdata->buffer_size - buffstat;
598 }
599 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
600
601 /*
602 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
603 * to reach the threshold value (when the DMA will be triggered to read it)
604 */
605 u16 omap_mcbsp_get_rx_delay(unsigned int id)
606 {
607 struct omap_mcbsp *mcbsp;
608 u16 buffstat, threshold;
609
610 if (!omap_mcbsp_check_valid_id(id)) {
611 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
612 return -ENODEV;
613 }
614 mcbsp = id_to_mcbsp_ptr(id);
615
616 /* Returns the number of used locations in the buffer */
617 buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
618 /* RX threshold */
619 threshold = MCBSP_READ(mcbsp, THRSH1);
620
621 /* Return the number of location till we reach the threshold limit */
622 if (threshold <= buffstat)
623 return 0;
624 else
625 return threshold - buffstat;
626 }
627 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
628
629 /*
630 * omap_mcbsp_get_dma_op_mode just return the current configured
631 * operating mode for the mcbsp channel
632 */
633 int omap_mcbsp_get_dma_op_mode(unsigned int id)
634 {
635 struct omap_mcbsp *mcbsp;
636 int dma_op_mode;
637
638 if (!omap_mcbsp_check_valid_id(id)) {
639 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
640 return -ENODEV;
641 }
642 mcbsp = id_to_mcbsp_ptr(id);
643
644 dma_op_mode = mcbsp->dma_op_mode;
645
646 return dma_op_mode;
647 }
648 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
649
650 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
651 {
652 /*
653 * Enable wakup behavior, smart idle and all wakeups
654 * REVISIT: some wakeups may be unnecessary
655 */
656 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
657 u16 syscon;
658
659 syscon = MCBSP_READ(mcbsp, SYSCON);
660 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
661
662 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
663 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
664 CLOCKACTIVITY(0x02));
665 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
666 } else {
667 syscon |= SIDLEMODE(0x01);
668 }
669
670 MCBSP_WRITE(mcbsp, SYSCON, syscon);
671 }
672 }
673
674 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
675 {
676 /*
677 * Disable wakup behavior, smart idle and all wakeups
678 */
679 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
680 u16 syscon;
681
682 syscon = MCBSP_READ(mcbsp, SYSCON);
683 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
684 syscon |= SIDLEMODE(0x02);
685 MCBSP_WRITE(mcbsp, SYSCON, syscon);
686
687 syscon &= ~(SIDLEMODE(0x03));
688 MCBSP_WRITE(mcbsp, SYSCON, syscon);
689
690 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
691 }
692 }
693 #else
694 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
695 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
696 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
697 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
698 #endif
699
700 /*
701 * We can choose between IRQ based or polled IO.
702 * This needs to be called before omap_mcbsp_request().
703 */
704 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
705 {
706 struct omap_mcbsp *mcbsp;
707
708 if (!omap_mcbsp_check_valid_id(id)) {
709 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
710 return -ENODEV;
711 }
712 mcbsp = id_to_mcbsp_ptr(id);
713
714 spin_lock(&mcbsp->lock);
715
716 if (!mcbsp->free) {
717 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
718 mcbsp->id);
719 spin_unlock(&mcbsp->lock);
720 return -EINVAL;
721 }
722
723 mcbsp->io_type = io_type;
724
725 spin_unlock(&mcbsp->lock);
726
727 return 0;
728 }
729 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
730
731 int omap_mcbsp_request(unsigned int id)
732 {
733 struct omap_mcbsp *mcbsp;
734 void *reg_cache;
735 int err;
736
737 if (!omap_mcbsp_check_valid_id(id)) {
738 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
739 return -ENODEV;
740 }
741 mcbsp = id_to_mcbsp_ptr(id);
742
743 reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
744 if (!reg_cache) {
745 return -ENOMEM;
746 }
747
748 spin_lock(&mcbsp->lock);
749 if (!mcbsp->free) {
750 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
751 mcbsp->id);
752 err = -EBUSY;
753 goto err_kfree;
754 }
755
756 mcbsp->free = 0;
757 mcbsp->reg_cache = reg_cache;
758 spin_unlock(&mcbsp->lock);
759
760 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
761 mcbsp->pdata->ops->request(id);
762
763 clk_enable(mcbsp->iclk);
764 clk_enable(mcbsp->fclk);
765
766 /* Do procedure specific to omap34xx arch, if applicable */
767 omap34xx_mcbsp_request(mcbsp);
768
769 /*
770 * Make sure that transmitter, receiver and sample-rate generator are
771 * not running before activating IRQs.
772 */
773 MCBSP_WRITE(mcbsp, SPCR1, 0);
774 MCBSP_WRITE(mcbsp, SPCR2, 0);
775
776 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
777 /* We need to get IRQs here */
778 init_completion(&mcbsp->tx_irq_completion);
779 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
780 0, "McBSP", (void *)mcbsp);
781 if (err != 0) {
782 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
783 "for McBSP%d\n", mcbsp->tx_irq,
784 mcbsp->id);
785 goto err_clk_disable;
786 }
787
788 if (mcbsp->rx_irq) {
789 init_completion(&mcbsp->rx_irq_completion);
790 err = request_irq(mcbsp->rx_irq,
791 omap_mcbsp_rx_irq_handler,
792 0, "McBSP", (void *)mcbsp);
793 if (err != 0) {
794 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
795 "for McBSP%d\n", mcbsp->rx_irq,
796 mcbsp->id);
797 goto err_free_irq;
798 }
799 }
800 }
801
802 return 0;
803 err_free_irq:
804 free_irq(mcbsp->tx_irq, (void *)mcbsp);
805 err_clk_disable:
806 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
807 mcbsp->pdata->ops->free(id);
808
809 /* Do procedure specific to omap34xx arch, if applicable */
810 omap34xx_mcbsp_free(mcbsp);
811
812 clk_disable(mcbsp->fclk);
813 clk_disable(mcbsp->iclk);
814
815 spin_lock(&mcbsp->lock);
816 mcbsp->free = 1;
817 mcbsp->reg_cache = NULL;
818 err_kfree:
819 spin_unlock(&mcbsp->lock);
820 kfree(reg_cache);
821
822 return err;
823 }
824 EXPORT_SYMBOL(omap_mcbsp_request);
825
826 void omap_mcbsp_free(unsigned int id)
827 {
828 struct omap_mcbsp *mcbsp;
829 void *reg_cache;
830
831 if (!omap_mcbsp_check_valid_id(id)) {
832 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
833 return;
834 }
835 mcbsp = id_to_mcbsp_ptr(id);
836
837 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
838 mcbsp->pdata->ops->free(id);
839
840 /* Do procedure specific to omap34xx arch, if applicable */
841 omap34xx_mcbsp_free(mcbsp);
842
843 clk_disable(mcbsp->fclk);
844 clk_disable(mcbsp->iclk);
845
846 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
847 /* Free IRQs */
848 if (mcbsp->rx_irq)
849 free_irq(mcbsp->rx_irq, (void *)mcbsp);
850 free_irq(mcbsp->tx_irq, (void *)mcbsp);
851 }
852
853 reg_cache = mcbsp->reg_cache;
854
855 spin_lock(&mcbsp->lock);
856 if (mcbsp->free)
857 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
858 else
859 mcbsp->free = 1;
860 mcbsp->reg_cache = NULL;
861 spin_unlock(&mcbsp->lock);
862
863 if (reg_cache)
864 kfree(reg_cache);
865 }
866 EXPORT_SYMBOL(omap_mcbsp_free);
867
868 /*
869 * Here we start the McBSP, by enabling transmitter, receiver or both.
870 * If no transmitter or receiver is active prior calling, then sample-rate
871 * generator and frame sync are started.
872 */
873 void omap_mcbsp_start(unsigned int id, int tx, int rx)
874 {
875 struct omap_mcbsp *mcbsp;
876 int idle;
877 u16 w;
878
879 if (!omap_mcbsp_check_valid_id(id)) {
880 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
881 return;
882 }
883 mcbsp = id_to_mcbsp_ptr(id);
884
885 if (cpu_is_omap34xx())
886 omap_st_start(mcbsp);
887
888 mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
889 mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
890
891 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
892 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
893
894 if (idle) {
895 /* Start the sample generator */
896 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
897 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
898 }
899
900 /* Enable transmitter and receiver */
901 tx &= 1;
902 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
903 MCBSP_WRITE(mcbsp, SPCR2, w | tx);
904
905 rx &= 1;
906 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
907 MCBSP_WRITE(mcbsp, SPCR1, w | rx);
908
909 /*
910 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
911 * REVISIT: 100us may give enough time for two CLKSRG, however
912 * due to some unknown PM related, clock gating etc. reason it
913 * is now at 500us.
914 */
915 udelay(500);
916
917 if (idle) {
918 /* Start frame sync */
919 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
920 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
921 }
922
923 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
924 /* Release the transmitter and receiver */
925 w = MCBSP_READ_CACHE(mcbsp, XCCR);
926 w &= ~(tx ? XDISABLE : 0);
927 MCBSP_WRITE(mcbsp, XCCR, w);
928 w = MCBSP_READ_CACHE(mcbsp, RCCR);
929 w &= ~(rx ? RDISABLE : 0);
930 MCBSP_WRITE(mcbsp, RCCR, w);
931 }
932
933 /* Dump McBSP Regs */
934 omap_mcbsp_dump_reg(id);
935 }
936 EXPORT_SYMBOL(omap_mcbsp_start);
937
938 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
939 {
940 struct omap_mcbsp *mcbsp;
941 int idle;
942 u16 w;
943
944 if (!omap_mcbsp_check_valid_id(id)) {
945 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
946 return;
947 }
948
949 mcbsp = id_to_mcbsp_ptr(id);
950
951 /* Reset transmitter */
952 tx &= 1;
953 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
954 w = MCBSP_READ_CACHE(mcbsp, XCCR);
955 w |= (tx ? XDISABLE : 0);
956 MCBSP_WRITE(mcbsp, XCCR, w);
957 }
958 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
959 MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
960
961 /* Reset receiver */
962 rx &= 1;
963 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
964 w = MCBSP_READ_CACHE(mcbsp, RCCR);
965 w |= (rx ? RDISABLE : 0);
966 MCBSP_WRITE(mcbsp, RCCR, w);
967 }
968 w = MCBSP_READ_CACHE(mcbsp, SPCR1);
969 MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
970
971 idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
972 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
973
974 if (idle) {
975 /* Reset the sample rate generator */
976 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
977 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
978 }
979
980 if (cpu_is_omap34xx())
981 omap_st_stop(mcbsp);
982 }
983 EXPORT_SYMBOL(omap_mcbsp_stop);
984
985 /* polled mcbsp i/o operations */
986 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
987 {
988 struct omap_mcbsp *mcbsp;
989
990 if (!omap_mcbsp_check_valid_id(id)) {
991 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
992 return -ENODEV;
993 }
994
995 mcbsp = id_to_mcbsp_ptr(id);
996
997 MCBSP_WRITE(mcbsp, DXR1, buf);
998 /* if frame sync error - clear the error */
999 if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1000 /* clear error */
1001 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1002 /* resend */
1003 return -1;
1004 } else {
1005 /* wait for transmit confirmation */
1006 int attemps = 0;
1007 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1008 if (attemps++ > 1000) {
1009 MCBSP_WRITE(mcbsp, SPCR2,
1010 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1011 (~XRST));
1012 udelay(10);
1013 MCBSP_WRITE(mcbsp, SPCR2,
1014 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1015 (XRST));
1016 udelay(10);
1017 dev_err(mcbsp->dev, "Could not write to"
1018 " McBSP%d Register\n", mcbsp->id);
1019 return -2;
1020 }
1021 }
1022 }
1023
1024 return 0;
1025 }
1026 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1027
1028 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1029 {
1030 struct omap_mcbsp *mcbsp;
1031
1032 if (!omap_mcbsp_check_valid_id(id)) {
1033 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1034 return -ENODEV;
1035 }
1036 mcbsp = id_to_mcbsp_ptr(id);
1037
1038 /* if frame sync error - clear the error */
1039 if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1040 /* clear error */
1041 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1042 /* resend */
1043 return -1;
1044 } else {
1045 /* wait for recieve confirmation */
1046 int attemps = 0;
1047 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1048 if (attemps++ > 1000) {
1049 MCBSP_WRITE(mcbsp, SPCR1,
1050 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1051 (~RRST));
1052 udelay(10);
1053 MCBSP_WRITE(mcbsp, SPCR1,
1054 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1055 (RRST));
1056 udelay(10);
1057 dev_err(mcbsp->dev, "Could not read from"
1058 " McBSP%d Register\n", mcbsp->id);
1059 return -2;
1060 }
1061 }
1062 }
1063 *buf = MCBSP_READ(mcbsp, DRR1);
1064
1065 return 0;
1066 }
1067 EXPORT_SYMBOL(omap_mcbsp_pollread);
1068
1069 /*
1070 * IRQ based word transmission.
1071 */
1072 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1073 {
1074 struct omap_mcbsp *mcbsp;
1075 omap_mcbsp_word_length word_length;
1076
1077 if (!omap_mcbsp_check_valid_id(id)) {
1078 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1079 return;
1080 }
1081
1082 mcbsp = id_to_mcbsp_ptr(id);
1083 word_length = mcbsp->tx_word_length;
1084
1085 wait_for_completion(&mcbsp->tx_irq_completion);
1086
1087 if (word_length > OMAP_MCBSP_WORD_16)
1088 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1089 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1090 }
1091 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1092
1093 u32 omap_mcbsp_recv_word(unsigned int id)
1094 {
1095 struct omap_mcbsp *mcbsp;
1096 u16 word_lsb, word_msb = 0;
1097 omap_mcbsp_word_length word_length;
1098
1099 if (!omap_mcbsp_check_valid_id(id)) {
1100 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1101 return -ENODEV;
1102 }
1103 mcbsp = id_to_mcbsp_ptr(id);
1104
1105 word_length = mcbsp->rx_word_length;
1106
1107 wait_for_completion(&mcbsp->rx_irq_completion);
1108
1109 if (word_length > OMAP_MCBSP_WORD_16)
1110 word_msb = MCBSP_READ(mcbsp, DRR2);
1111 word_lsb = MCBSP_READ(mcbsp, DRR1);
1112
1113 return (word_lsb | (word_msb << 16));
1114 }
1115 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1116
1117 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1118 {
1119 struct omap_mcbsp *mcbsp;
1120 omap_mcbsp_word_length tx_word_length;
1121 omap_mcbsp_word_length rx_word_length;
1122 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1123
1124 if (!omap_mcbsp_check_valid_id(id)) {
1125 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1126 return -ENODEV;
1127 }
1128 mcbsp = id_to_mcbsp_ptr(id);
1129 tx_word_length = mcbsp->tx_word_length;
1130 rx_word_length = mcbsp->rx_word_length;
1131
1132 if (tx_word_length != rx_word_length)
1133 return -EINVAL;
1134
1135 /* First we wait for the transmitter to be ready */
1136 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1137 while (!(spcr2 & XRDY)) {
1138 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1139 if (attempts++ > 1000) {
1140 /* We must reset the transmitter */
1141 MCBSP_WRITE(mcbsp, SPCR2,
1142 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1143 udelay(10);
1144 MCBSP_WRITE(mcbsp, SPCR2,
1145 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1146 udelay(10);
1147 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1148 "ready\n", mcbsp->id);
1149 return -EAGAIN;
1150 }
1151 }
1152
1153 /* Now we can push the data */
1154 if (tx_word_length > OMAP_MCBSP_WORD_16)
1155 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1156 MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1157
1158 /* We wait for the receiver to be ready */
1159 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1160 while (!(spcr1 & RRDY)) {
1161 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1162 if (attempts++ > 1000) {
1163 /* We must reset the receiver */
1164 MCBSP_WRITE(mcbsp, SPCR1,
1165 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1166 udelay(10);
1167 MCBSP_WRITE(mcbsp, SPCR1,
1168 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1169 udelay(10);
1170 dev_err(mcbsp->dev, "McBSP%d receiver not "
1171 "ready\n", mcbsp->id);
1172 return -EAGAIN;
1173 }
1174 }
1175
1176 /* Receiver is ready, let's read the dummy data */
1177 if (rx_word_length > OMAP_MCBSP_WORD_16)
1178 word_msb = MCBSP_READ(mcbsp, DRR2);
1179 word_lsb = MCBSP_READ(mcbsp, DRR1);
1180
1181 return 0;
1182 }
1183 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1184
1185 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1186 {
1187 struct omap_mcbsp *mcbsp;
1188 u32 clock_word = 0;
1189 omap_mcbsp_word_length tx_word_length;
1190 omap_mcbsp_word_length rx_word_length;
1191 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1192
1193 if (!omap_mcbsp_check_valid_id(id)) {
1194 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1195 return -ENODEV;
1196 }
1197
1198 mcbsp = id_to_mcbsp_ptr(id);
1199
1200 tx_word_length = mcbsp->tx_word_length;
1201 rx_word_length = mcbsp->rx_word_length;
1202
1203 if (tx_word_length != rx_word_length)
1204 return -EINVAL;
1205
1206 /* First we wait for the transmitter to be ready */
1207 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1208 while (!(spcr2 & XRDY)) {
1209 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1210 if (attempts++ > 1000) {
1211 /* We must reset the transmitter */
1212 MCBSP_WRITE(mcbsp, SPCR2,
1213 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1214 udelay(10);
1215 MCBSP_WRITE(mcbsp, SPCR2,
1216 MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1217 udelay(10);
1218 dev_err(mcbsp->dev, "McBSP%d transmitter not "
1219 "ready\n", mcbsp->id);
1220 return -EAGAIN;
1221 }
1222 }
1223
1224 /* We first need to enable the bus clock */
1225 if (tx_word_length > OMAP_MCBSP_WORD_16)
1226 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1227 MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1228
1229 /* We wait for the receiver to be ready */
1230 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1231 while (!(spcr1 & RRDY)) {
1232 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1233 if (attempts++ > 1000) {
1234 /* We must reset the receiver */
1235 MCBSP_WRITE(mcbsp, SPCR1,
1236 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1237 udelay(10);
1238 MCBSP_WRITE(mcbsp, SPCR1,
1239 MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1240 udelay(10);
1241 dev_err(mcbsp->dev, "McBSP%d receiver not "
1242 "ready\n", mcbsp->id);
1243 return -EAGAIN;
1244 }
1245 }
1246
1247 /* Receiver is ready, there is something for us */
1248 if (rx_word_length > OMAP_MCBSP_WORD_16)
1249 word_msb = MCBSP_READ(mcbsp, DRR2);
1250 word_lsb = MCBSP_READ(mcbsp, DRR1);
1251
1252 word[0] = (word_lsb | (word_msb << 16));
1253
1254 return 0;
1255 }
1256 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1257
1258 /*
1259 * Simple DMA based buffer rx/tx routines.
1260 * Nothing fancy, just a single buffer tx/rx through DMA.
1261 * The DMA resources are released once the transfer is done.
1262 * For anything fancier, you should use your own customized DMA
1263 * routines and callbacks.
1264 */
1265 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1266 unsigned int length)
1267 {
1268 struct omap_mcbsp *mcbsp;
1269 int dma_tx_ch;
1270 int src_port = 0;
1271 int dest_port = 0;
1272 int sync_dev = 0;
1273
1274 if (!omap_mcbsp_check_valid_id(id)) {
1275 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1276 return -ENODEV;
1277 }
1278 mcbsp = id_to_mcbsp_ptr(id);
1279
1280 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1281 omap_mcbsp_tx_dma_callback,
1282 mcbsp,
1283 &dma_tx_ch)) {
1284 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1285 "McBSP%d TX. Trying IRQ based TX\n",
1286 mcbsp->id);
1287 return -EAGAIN;
1288 }
1289 mcbsp->dma_tx_lch = dma_tx_ch;
1290
1291 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1292 dma_tx_ch);
1293
1294 init_completion(&mcbsp->tx_dma_completion);
1295
1296 if (cpu_class_is_omap1()) {
1297 src_port = OMAP_DMA_PORT_TIPB;
1298 dest_port = OMAP_DMA_PORT_EMIFF;
1299 }
1300 if (cpu_class_is_omap2())
1301 sync_dev = mcbsp->dma_tx_sync;
1302
1303 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1304 OMAP_DMA_DATA_TYPE_S16,
1305 length >> 1, 1,
1306 OMAP_DMA_SYNC_ELEMENT,
1307 sync_dev, 0);
1308
1309 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1310 src_port,
1311 OMAP_DMA_AMODE_CONSTANT,
1312 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1313 0, 0);
1314
1315 omap_set_dma_src_params(mcbsp->dma_tx_lch,
1316 dest_port,
1317 OMAP_DMA_AMODE_POST_INC,
1318 buffer,
1319 0, 0);
1320
1321 omap_start_dma(mcbsp->dma_tx_lch);
1322 wait_for_completion(&mcbsp->tx_dma_completion);
1323
1324 return 0;
1325 }
1326 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1327
1328 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1329 unsigned int length)
1330 {
1331 struct omap_mcbsp *mcbsp;
1332 int dma_rx_ch;
1333 int src_port = 0;
1334 int dest_port = 0;
1335 int sync_dev = 0;
1336
1337 if (!omap_mcbsp_check_valid_id(id)) {
1338 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1339 return -ENODEV;
1340 }
1341 mcbsp = id_to_mcbsp_ptr(id);
1342
1343 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1344 omap_mcbsp_rx_dma_callback,
1345 mcbsp,
1346 &dma_rx_ch)) {
1347 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1348 "McBSP%d RX. Trying IRQ based RX\n",
1349 mcbsp->id);
1350 return -EAGAIN;
1351 }
1352 mcbsp->dma_rx_lch = dma_rx_ch;
1353
1354 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1355 dma_rx_ch);
1356
1357 init_completion(&mcbsp->rx_dma_completion);
1358
1359 if (cpu_class_is_omap1()) {
1360 src_port = OMAP_DMA_PORT_TIPB;
1361 dest_port = OMAP_DMA_PORT_EMIFF;
1362 }
1363 if (cpu_class_is_omap2())
1364 sync_dev = mcbsp->dma_rx_sync;
1365
1366 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1367 OMAP_DMA_DATA_TYPE_S16,
1368 length >> 1, 1,
1369 OMAP_DMA_SYNC_ELEMENT,
1370 sync_dev, 0);
1371
1372 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1373 src_port,
1374 OMAP_DMA_AMODE_CONSTANT,
1375 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1376 0, 0);
1377
1378 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1379 dest_port,
1380 OMAP_DMA_AMODE_POST_INC,
1381 buffer,
1382 0, 0);
1383
1384 omap_start_dma(mcbsp->dma_rx_lch);
1385 wait_for_completion(&mcbsp->rx_dma_completion);
1386
1387 return 0;
1388 }
1389 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1390
1391 /*
1392 * SPI wrapper.
1393 * Since SPI setup is much simpler than the generic McBSP one,
1394 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1395 * Once this is done, you can call omap_mcbsp_start().
1396 */
1397 void omap_mcbsp_set_spi_mode(unsigned int id,
1398 const struct omap_mcbsp_spi_cfg *spi_cfg)
1399 {
1400 struct omap_mcbsp *mcbsp;
1401 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1402
1403 if (!omap_mcbsp_check_valid_id(id)) {
1404 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1405 return;
1406 }
1407 mcbsp = id_to_mcbsp_ptr(id);
1408
1409 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1410
1411 /* SPI has only one frame */
1412 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1413 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1414
1415 /* Clock stop mode */
1416 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1417 mcbsp_cfg.spcr1 |= (1 << 12);
1418 else
1419 mcbsp_cfg.spcr1 |= (3 << 11);
1420
1421 /* Set clock parities */
1422 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1423 mcbsp_cfg.pcr0 |= CLKRP;
1424 else
1425 mcbsp_cfg.pcr0 &= ~CLKRP;
1426
1427 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1428 mcbsp_cfg.pcr0 &= ~CLKXP;
1429 else
1430 mcbsp_cfg.pcr0 |= CLKXP;
1431
1432 /* Set SCLKME to 0 and CLKSM to 1 */
1433 mcbsp_cfg.pcr0 &= ~SCLKME;
1434 mcbsp_cfg.srgr2 |= CLKSM;
1435
1436 /* Set FSXP */
1437 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1438 mcbsp_cfg.pcr0 &= ~FSXP;
1439 else
1440 mcbsp_cfg.pcr0 |= FSXP;
1441
1442 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1443 mcbsp_cfg.pcr0 |= CLKXM;
1444 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1445 mcbsp_cfg.pcr0 |= FSXM;
1446 mcbsp_cfg.srgr2 &= ~FSGM;
1447 mcbsp_cfg.xcr2 |= XDATDLY(1);
1448 mcbsp_cfg.rcr2 |= RDATDLY(1);
1449 } else {
1450 mcbsp_cfg.pcr0 &= ~CLKXM;
1451 mcbsp_cfg.srgr1 |= CLKGDV(1);
1452 mcbsp_cfg.pcr0 &= ~FSXM;
1453 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1454 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1455 }
1456
1457 mcbsp_cfg.xcr2 &= ~XPHASE;
1458 mcbsp_cfg.rcr2 &= ~RPHASE;
1459
1460 omap_mcbsp_config(id, &mcbsp_cfg);
1461 }
1462 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1463
1464 #ifdef CONFIG_ARCH_OMAP3
1465 #define max_thres(m) (mcbsp->pdata->buffer_size)
1466 #define valid_threshold(m, val) ((val) <= max_thres(m))
1467 #define THRESHOLD_PROP_BUILDER(prop) \
1468 static ssize_t prop##_show(struct device *dev, \
1469 struct device_attribute *attr, char *buf) \
1470 { \
1471 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1472 \
1473 return sprintf(buf, "%u\n", mcbsp->prop); \
1474 } \
1475 \
1476 static ssize_t prop##_store(struct device *dev, \
1477 struct device_attribute *attr, \
1478 const char *buf, size_t size) \
1479 { \
1480 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1481 unsigned long val; \
1482 int status; \
1483 \
1484 status = strict_strtoul(buf, 0, &val); \
1485 if (status) \
1486 return status; \
1487 \
1488 if (!valid_threshold(mcbsp, val)) \
1489 return -EDOM; \
1490 \
1491 mcbsp->prop = val; \
1492 return size; \
1493 } \
1494 \
1495 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1496
1497 THRESHOLD_PROP_BUILDER(max_tx_thres);
1498 THRESHOLD_PROP_BUILDER(max_rx_thres);
1499
1500 static const char *dma_op_modes[] = {
1501 "element", "threshold", "frame",
1502 };
1503
1504 static ssize_t dma_op_mode_show(struct device *dev,
1505 struct device_attribute *attr, char *buf)
1506 {
1507 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1508 int dma_op_mode, i = 0;
1509 ssize_t len = 0;
1510 const char * const *s;
1511
1512 dma_op_mode = mcbsp->dma_op_mode;
1513
1514 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1515 if (dma_op_mode == i)
1516 len += sprintf(buf + len, "[%s] ", *s);
1517 else
1518 len += sprintf(buf + len, "%s ", *s);
1519 }
1520 len += sprintf(buf + len, "\n");
1521
1522 return len;
1523 }
1524
1525 static ssize_t dma_op_mode_store(struct device *dev,
1526 struct device_attribute *attr,
1527 const char *buf, size_t size)
1528 {
1529 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1530 const char * const *s;
1531 int i = 0;
1532
1533 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1534 if (sysfs_streq(buf, *s))
1535 break;
1536
1537 if (i == ARRAY_SIZE(dma_op_modes))
1538 return -EINVAL;
1539
1540 spin_lock_irq(&mcbsp->lock);
1541 if (!mcbsp->free) {
1542 size = -EBUSY;
1543 goto unlock;
1544 }
1545 mcbsp->dma_op_mode = i;
1546
1547 unlock:
1548 spin_unlock_irq(&mcbsp->lock);
1549
1550 return size;
1551 }
1552
1553 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1554
1555 static ssize_t st_taps_show(struct device *dev,
1556 struct device_attribute *attr, char *buf)
1557 {
1558 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1559 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1560 ssize_t status = 0;
1561 int i;
1562
1563 spin_lock_irq(&mcbsp->lock);
1564 for (i = 0; i < st_data->nr_taps; i++)
1565 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1566 st_data->taps[i]);
1567 if (i)
1568 status += sprintf(&buf[status], "\n");
1569 spin_unlock_irq(&mcbsp->lock);
1570
1571 return status;
1572 }
1573
1574 static ssize_t st_taps_store(struct device *dev,
1575 struct device_attribute *attr,
1576 const char *buf, size_t size)
1577 {
1578 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1579 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1580 int val, tmp, status, i = 0;
1581
1582 spin_lock_irq(&mcbsp->lock);
1583 memset(st_data->taps, 0, sizeof(st_data->taps));
1584 st_data->nr_taps = 0;
1585
1586 do {
1587 status = sscanf(buf, "%d%n", &val, &tmp);
1588 if (status < 0 || status == 0) {
1589 size = -EINVAL;
1590 goto out;
1591 }
1592 if (val < -32768 || val > 32767) {
1593 size = -EINVAL;
1594 goto out;
1595 }
1596 st_data->taps[i++] = val;
1597 buf += tmp;
1598 if (*buf != ',')
1599 break;
1600 buf++;
1601 } while (1);
1602
1603 st_data->nr_taps = i;
1604
1605 out:
1606 spin_unlock_irq(&mcbsp->lock);
1607
1608 return size;
1609 }
1610
1611 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1612
1613 static const struct attribute *additional_attrs[] = {
1614 &dev_attr_max_tx_thres.attr,
1615 &dev_attr_max_rx_thres.attr,
1616 &dev_attr_dma_op_mode.attr,
1617 NULL,
1618 };
1619
1620 static const struct attribute_group additional_attr_group = {
1621 .attrs = (struct attribute **)additional_attrs,
1622 };
1623
1624 static inline int __devinit omap_additional_add(struct device *dev)
1625 {
1626 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1627 }
1628
1629 static inline void __devexit omap_additional_remove(struct device *dev)
1630 {
1631 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1632 }
1633
1634 static const struct attribute *sidetone_attrs[] = {
1635 &dev_attr_st_taps.attr,
1636 NULL,
1637 };
1638
1639 static const struct attribute_group sidetone_attr_group = {
1640 .attrs = (struct attribute **)sidetone_attrs,
1641 };
1642
1643 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1644 {
1645 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1646 struct omap_mcbsp_st_data *st_data;
1647 int err;
1648
1649 st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1650 if (!st_data) {
1651 err = -ENOMEM;
1652 goto err1;
1653 }
1654
1655 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1656 if (!st_data->io_base_st) {
1657 err = -ENOMEM;
1658 goto err2;
1659 }
1660
1661 err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1662 if (err)
1663 goto err3;
1664
1665 mcbsp->st_data = st_data;
1666 return 0;
1667
1668 err3:
1669 iounmap(st_data->io_base_st);
1670 err2:
1671 kfree(st_data);
1672 err1:
1673 return err;
1674
1675 }
1676
1677 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1678 {
1679 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1680
1681 if (st_data) {
1682 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1683 iounmap(st_data->io_base_st);
1684 kfree(st_data);
1685 }
1686 }
1687
1688 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1689 {
1690 mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1691 if (cpu_is_omap34xx()) {
1692 /*
1693 * Initially configure the maximum thresholds to a safe value.
1694 * The McBSP FIFO usage with these values should not go under
1695 * 16 locations.
1696 * If the whole FIFO without safety buffer is used, than there
1697 * is a possibility that the DMA will be not able to push the
1698 * new data on time, causing channel shifts in runtime.
1699 */
1700 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1701 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1702 /*
1703 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1704 * for mcbsp2 instances.
1705 */
1706 if (omap_additional_add(mcbsp->dev))
1707 dev_warn(mcbsp->dev,
1708 "Unable to create additional controls\n");
1709
1710 if (mcbsp->id == 2 || mcbsp->id == 3)
1711 if (omap_st_add(mcbsp))
1712 dev_warn(mcbsp->dev,
1713 "Unable to create sidetone controls\n");
1714
1715 } else {
1716 mcbsp->max_tx_thres = -EINVAL;
1717 mcbsp->max_rx_thres = -EINVAL;
1718 }
1719 }
1720
1721 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1722 {
1723 if (cpu_is_omap34xx()) {
1724 omap_additional_remove(mcbsp->dev);
1725
1726 if (mcbsp->id == 2 || mcbsp->id == 3)
1727 omap_st_remove(mcbsp);
1728 }
1729 }
1730 #else
1731 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1732 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1733 #endif /* CONFIG_ARCH_OMAP3 */
1734
1735 /*
1736 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1737 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1738 */
1739 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1740 {
1741 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1742 struct omap_mcbsp *mcbsp;
1743 int id = pdev->id - 1;
1744 int ret = 0;
1745
1746 if (!pdata) {
1747 dev_err(&pdev->dev, "McBSP device initialized without"
1748 "platform data\n");
1749 ret = -EINVAL;
1750 goto exit;
1751 }
1752
1753 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1754
1755 if (id >= omap_mcbsp_count) {
1756 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1757 ret = -EINVAL;
1758 goto exit;
1759 }
1760
1761 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1762 if (!mcbsp) {
1763 ret = -ENOMEM;
1764 goto exit;
1765 }
1766
1767 spin_lock_init(&mcbsp->lock);
1768 mcbsp->id = id + 1;
1769 mcbsp->free = 1;
1770 mcbsp->dma_tx_lch = -1;
1771 mcbsp->dma_rx_lch = -1;
1772
1773 mcbsp->phys_base = pdata->phys_base;
1774 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1775 if (!mcbsp->io_base) {
1776 ret = -ENOMEM;
1777 goto err_ioremap;
1778 }
1779
1780 /* Default I/O is IRQ based */
1781 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1782 mcbsp->tx_irq = pdata->tx_irq;
1783 mcbsp->rx_irq = pdata->rx_irq;
1784 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1785 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1786
1787 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1788 if (IS_ERR(mcbsp->iclk)) {
1789 ret = PTR_ERR(mcbsp->iclk);
1790 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1791 goto err_iclk;
1792 }
1793
1794 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1795 if (IS_ERR(mcbsp->fclk)) {
1796 ret = PTR_ERR(mcbsp->fclk);
1797 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1798 goto err_fclk;
1799 }
1800
1801 mcbsp->pdata = pdata;
1802 mcbsp->dev = &pdev->dev;
1803 mcbsp_ptr[id] = mcbsp;
1804 platform_set_drvdata(pdev, mcbsp);
1805
1806 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1807 omap34xx_device_init(mcbsp);
1808
1809 return 0;
1810
1811 err_fclk:
1812 clk_put(mcbsp->iclk);
1813 err_iclk:
1814 iounmap(mcbsp->io_base);
1815 err_ioremap:
1816 kfree(mcbsp);
1817 exit:
1818 return ret;
1819 }
1820
1821 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1822 {
1823 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1824
1825 platform_set_drvdata(pdev, NULL);
1826 if (mcbsp) {
1827
1828 if (mcbsp->pdata && mcbsp->pdata->ops &&
1829 mcbsp->pdata->ops->free)
1830 mcbsp->pdata->ops->free(mcbsp->id);
1831
1832 omap34xx_device_exit(mcbsp);
1833
1834 clk_disable(mcbsp->fclk);
1835 clk_disable(mcbsp->iclk);
1836 clk_put(mcbsp->fclk);
1837 clk_put(mcbsp->iclk);
1838
1839 iounmap(mcbsp->io_base);
1840
1841 mcbsp->fclk = NULL;
1842 mcbsp->iclk = NULL;
1843 mcbsp->free = 0;
1844 mcbsp->dev = NULL;
1845 }
1846
1847 return 0;
1848 }
1849
1850 static struct platform_driver omap_mcbsp_driver = {
1851 .probe = omap_mcbsp_probe,
1852 .remove = __devexit_p(omap_mcbsp_remove),
1853 .driver = {
1854 .name = "omap-mcbsp",
1855 },
1856 };
1857
1858 int __init omap_mcbsp_init(void)
1859 {
1860 /* Register the McBSP driver */
1861 return platform_driver_register(&omap_mcbsp_driver);
1862 }
Tomato firmware and modifications.