release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/plat-omap/i2c.c

   1 /*
   2  * linux/arch/arm/plat-omap/i2c.c
   3  *
   4  * Helper module for board specific I2C bus registration
   5  *
   6  * Copyright (C) 2007 Nokia Corporation.
   7  *
   8  * Contact: Jarkko Nikula <jhnikula@gmail.com>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * version 2 as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
  15  * WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  22  * 02110-1301 USA
  23  *
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/i2c.h>
  29 #include <linux/i2c-omap.h>
  30
  31 #include <mach/irqs.h>
  32 #include <plat/mux.h>
  33 #include <plat/i2c.h>
  34 #include <plat/omap-pm.h>
  35
  36 #define OMAP_I2C_SIZE           0x3f
  37 #define OMAP1_I2C_BASE          0xfffb3800
  38 #define OMAP2_I2C_BASE1         0x48070000
  39 #define OMAP2_I2C_BASE2         0x48072000
  40 #define OMAP2_I2C_BASE3         0x48060000
  41 #define OMAP4_I2C_BASE4         0x48350000
  42
  43 static const char name[] = "i2c_omap";
  44
  45 #define I2C_RESOURCE_BUILDER(base, irq)                 \
  46         {                                               \
  47                 .start  = (base),                       \
  48                 .end    = (base) + OMAP_I2C_SIZE,       \
  49                 .flags  = IORESOURCE_MEM,               \
  50         },                                              \
  51         {                                               \
  52                 .start  = (irq),                        \
  53                 .flags  = IORESOURCE_IRQ,               \
  54         },
  55
  56 static struct resource i2c_resources[][2] = {
  57         { I2C_RESOURCE_BUILDER(0, 0) },
  58 #if     defined(CONFIG_ARCH_OMAP2PLUS)
  59         { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) },
  60 #endif
  61 #if     defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  62         { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) },
  63 #endif
  64 #if     defined(CONFIG_ARCH_OMAP4)
  65         { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) },
  66 #endif
  67 };
  68
  69 #define I2C_DEV_BUILDER(bus_id, res, data)              \
  70         {                                               \
  71                 .id     = (bus_id),                     \
  72                 .name   = name,                         \
  73                 .num_resources  = ARRAY_SIZE(res),      \
  74                 .resource       = (res),                \
  75                 .dev            = {                     \
  76                         .platform_data  = (data),       \
  77                 },                                      \
  78         }
  79
  80 static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)];
  81 static struct platform_device omap_i2c_devices[] = {
  82         I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]),
  83 #if     defined(CONFIG_ARCH_OMAP2PLUS)
  84         I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]),
  85 #endif
  86 #if     defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
  87         I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]),
  88 #endif
  89 #if     defined(CONFIG_ARCH_OMAP4)
  90         I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]),
  91 #endif
  92 };
  93
  94 #define OMAP_I2C_CMDLINE_SETUP  (BIT(31))
  95
  96 static int __init omap_i2c_nr_ports(void)
  97 {
  98         int ports = 0;
  99
 100         if (cpu_class_is_omap1())
 101                 ports = 1;
 102         else if (cpu_is_omap24xx())
 103                 ports = 2;
 104         else if (cpu_is_omap34xx())
 105                 ports = 3;
 106         else if (cpu_is_omap44xx())
 107                 ports = 4;
 108
 109         return ports;
 110 }
 111
 112 /* Shared between omap2 and 3 */
 113 static resource_size_t omap2_i2c_irq[3] __initdata = {
 114         INT_24XX_I2C1_IRQ,
 115         INT_24XX_I2C2_IRQ,
 116         INT_34XX_I2C3_IRQ,
 117 };
 118
 119 static resource_size_t omap4_i2c_irq[4] __initdata = {
 120         OMAP44XX_IRQ_I2C1,
 121         OMAP44XX_IRQ_I2C2,
 122         OMAP44XX_IRQ_I2C3,
 123         OMAP44XX_IRQ_I2C4,
 124 };
 125
 126 static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id)
 127 {
 128         struct omap_i2c_bus_platform_data *pd;
 129         struct resource *res;
 130
 131         pd = pdev->dev.platform_data;
 132         res = pdev->resource;
 133         res[0].start = OMAP1_I2C_BASE;
 134         res[0].end = res[0].start + OMAP_I2C_SIZE;
 135         res[1].start = INT_I2C;
 136         omap1_i2c_mux_pins(bus_id);
 137
 138         return platform_device_register(pdev);
 139 }
 140
 141 static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t)
 142 {
 143         omap_pm_set_max_mpu_wakeup_lat(dev, t);
 144 }
 145
 146 static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id)
 147 {
 148         struct resource *res;
 149         resource_size_t *irq;
 150
 151         res = pdev->resource;
 152
 153         if (!cpu_is_omap44xx())
 154                 irq = omap2_i2c_irq;
 155         else
 156                 irq = omap4_i2c_irq;
 157
 158         if (bus_id == 1) {
 159                 res[0].start = OMAP2_I2C_BASE1;
 160                 res[0].end = res[0].start + OMAP_I2C_SIZE;
 161         }
 162
 163         res[1].start = irq[bus_id - 1];
 164         omap2_i2c_mux_pins(bus_id);
 165
 166         /*
 167          * When waiting for completion of a i2c transfer, we need to
 168          * set a wake up latency constraint for the MPU. This is to
 169          * ensure quick enough wakeup from idle, when transfer
 170          * completes.
 171          */
 172         if (cpu_is_omap34xx()) {
 173                 struct omap_i2c_bus_platform_data *pd;
 174
 175                 pd = pdev->dev.platform_data;
 176                 pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat;
 177         }
 178
 179         return platform_device_register(pdev);
 180 }
 181
 182 static int __init omap_i2c_add_bus(int bus_id)
 183 {
 184         struct platform_device *pdev;
 185
 186         pdev = &omap_i2c_devices[bus_id - 1];
 187
 188         if (cpu_class_is_omap1())
 189                 return omap1_i2c_add_bus(pdev, bus_id);
 190         else
 191                 return omap2_i2c_add_bus(pdev, bus_id);
 192 }
 193
 194 /**
 195  * omap_i2c_bus_setup - Process command line options for the I2C bus speed
 196  * @str: String of options
 197  *
 198  * This function allow to override the default I2C bus speed for given I2C
 199  * bus with a command line option.
 200  *
 201  * Format: i2c_bus=bus_id,clkrate (in kHz)
 202  *
 203  * Returns 1 on success, 0 otherwise.
 204  */
 205 static int __init omap_i2c_bus_setup(char *str)
 206 {
 207         int ports;
 208         int ints[3];
 209
 210         ports = omap_i2c_nr_ports();
 211         get_options(str, 3, ints);
 212         if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports)
 213                 return 0;
 214         i2c_pdata[ints[1] - 1].clkrate = ints[2];
 215         i2c_pdata[ints[1] - 1].clkrate |= OMAP_I2C_CMDLINE_SETUP;
 216
 217         return 1;
 218 }
 219 __setup("i2c_bus=", omap_i2c_bus_setup);
 220
 221 /*
 222  * Register busses defined in command line but that are not registered with
 223  * omap_register_i2c_bus from board initialization code.
 224  */
 225 static int __init omap_register_i2c_bus_cmdline(void)
 226 {
 227         int i, err = 0;
 228
 229         for (i = 0; i < ARRAY_SIZE(i2c_pdata); i++)
 230                 if (i2c_pdata[i].clkrate & OMAP_I2C_CMDLINE_SETUP) {
 231                         i2c_pdata[i].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
 232                         err = omap_i2c_add_bus(i + 1);
 233                         if (err)
 234                                 goto out;
 235                 }
 236
 237 out:
 238         return err;
 239 }
 240 subsys_initcall(omap_register_i2c_bus_cmdline);
 241
 242 /**
 243  * omap_register_i2c_bus - register I2C bus with device descriptors
 244  * @bus_id: bus id counting from number 1
 245  * @clkrate: clock rate of the bus in kHz
 246  * @info: pointer into I2C device descriptor table or NULL
 247  * @len: number of descriptors in the table
 248  *
 249  * Returns 0 on success or an error code.
 250  */
 251 int __init omap_register_i2c_bus(int bus_id, u32 clkrate,
 252                           struct i2c_board_info const *info,
 253                           unsigned len)
 254 {
 255         int err;
 256
 257         BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports());
 258
 259         if (info) {
 260                 err = i2c_register_board_info(bus_id, info, len);
 261                 if (err)
 262                         return err;
 263         }
 264
 265         if (!i2c_pdata[bus_id - 1].clkrate)
 266                 i2c_pdata[bus_id - 1].clkrate = clkrate;
 267
 268         i2c_pdata[bus_id - 1].clkrate &= ~OMAP_I2C_CMDLINE_SETUP;
 269
 270         return omap_i2c_add_bus(bus_id);
 271 }