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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / mach-tegra / tegra2_clocks.c
blob6441544fc399ffde86d959c4d01308643fa9873d
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/hrtimer.h>
27
28 #include <asm/clkdev.h>
29
30 #include <mach/iomap.h>
31
32 #include "clock.h"
33
34 #define RST_DEVICES 0x004
35 #define RST_DEVICES_SET 0x300
36 #define RST_DEVICES_CLR 0x304
37
38 #define CLK_OUT_ENB 0x010
39 #define CLK_OUT_ENB_SET 0x320
40 #define CLK_OUT_ENB_CLR 0x324
41
42 #define OSC_CTRL 0x50
43 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
44 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
45 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
46 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
47 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
48
49 #define OSC_FREQ_DET 0x58
50 #define OSC_FREQ_DET_TRIG (1<<31)
51
52 #define OSC_FREQ_DET_STATUS 0x5C
53 #define OSC_FREQ_DET_BUSY (1<<31)
54 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
55
56 #define PERIPH_CLK_SOURCE_MASK (3<<30)
57 #define PERIPH_CLK_SOURCE_SHIFT 30
58 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
59 #define PERIPH_CLK_SOURCE_DIV_MASK 0xFF
60 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
61
62 #define PLL_BASE 0x0
63 #define PLL_BASE_BYPASS (1<<31)
64 #define PLL_BASE_ENABLE (1<<30)
65 #define PLL_BASE_REF_ENABLE (1<<29)
66 #define PLL_BASE_OVERRIDE (1<<28)
67 #define PLL_BASE_LOCK (1<<27)
68 #define PLL_BASE_DIVP_MASK (0x7<<20)
69 #define PLL_BASE_DIVP_SHIFT 20
70 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
71 #define PLL_BASE_DIVN_SHIFT 8
72 #define PLL_BASE_DIVM_MASK (0x1F)
73 #define PLL_BASE_DIVM_SHIFT 0
74
75 #define PLL_OUT_RATIO_MASK (0xFF<<8)
76 #define PLL_OUT_RATIO_SHIFT 8
77 #define PLL_OUT_OVERRIDE (1<<2)
78 #define PLL_OUT_CLKEN (1<<1)
79 #define PLL_OUT_RESET_DISABLE (1<<0)
80
81 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
82 #define PLL_MISC_DCCON_SHIFT 20
83 #define PLL_MISC_LOCK_ENABLE (1<<18)
84 #define PLL_MISC_CPCON_SHIFT 8
85 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
86 #define PLL_MISC_LFCON_SHIFT 4
87 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
88 #define PLL_MISC_VCOCON_SHIFT 0
89 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
90
91 #define PLLD_MISC_CLKENABLE (1<<30)
92 #define PLLD_MISC_DIV_RST (1<<23)
93 #define PLLD_MISC_DCCON_SHIFT 12
94
95 #define PERIPH_CLK_TO_ENB_REG(c) ((c->clk_num / 32) * 4)
96 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->clk_num / 32) * 8)
97 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->clk_num % 32))
98
99 #define SUPER_CLK_MUX 0x00
100 #define SUPER_STATE_SHIFT 28
101 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
102 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
103 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
104 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
105 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
106 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
107 #define SUPER_SOURCE_MASK 0xF
108 #define SUPER_FIQ_SOURCE_SHIFT 12
109 #define SUPER_IRQ_SOURCE_SHIFT 8
110 #define SUPER_RUN_SOURCE_SHIFT 4
111 #define SUPER_IDLE_SOURCE_SHIFT 0
112
113 #define SUPER_CLK_DIVIDER 0x04
114
115 #define BUS_CLK_DISABLE (1<<3)
116 #define BUS_CLK_DIV_MASK 0x3
117
118 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
119
120 #define clk_writel(value, reg) \
121 __raw_writel(value, (u32)reg_clk_base + (reg))
122 #define clk_readl(reg) \
123 __raw_readl((u32)reg_clk_base + (reg))
124
125 unsigned long clk_measure_input_freq(void)
126 {
127 u32 clock_autodetect;
128 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
129 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
130 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
131 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
132 return 12000000;
133 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
134 return 13000000;
135 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
136 return 19200000;
137 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
138 return 26000000;
139 } else {
140 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
141 BUG();
142 return 0;
143 }
144 }
145
146 static int clk_div71_get_divider(struct clk *c, unsigned long rate)
147 {
148 unsigned long divider_u71;
149
150 divider_u71 = DIV_ROUND_UP(c->rate * 2, rate);
151
152 if (divider_u71 - 2 > 255 || divider_u71 - 2 < 0)
153 return -EINVAL;
154
155 return divider_u71 - 2;
156 }
157
158 static unsigned long tegra2_clk_recalculate_rate(struct clk *c)
159 {
160 unsigned long rate;
161 rate = c->parent->rate;
162
163 if (c->mul != 0 && c->div != 0)
164 c->rate = rate * c->mul / c->div;
165 else
166 c->rate = rate;
167 return c->rate;
168 }
169
170
171 /* clk_m functions */
172 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
173 {
174 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
175
176 c->rate = clk_measure_input_freq();
177 switch (c->rate) {
178 case 12000000:
179 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
180 break;
181 case 13000000:
182 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
183 break;
184 case 19200000:
185 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
186 break;
187 case 26000000:
188 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
189 break;
190 default:
191 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
192 BUG();
193 }
194 clk_writel(auto_clock_control, OSC_CTRL);
195 return c->rate;
196 }
197
198 static void tegra2_clk_m_init(struct clk *c)
199 {
200 pr_debug("%s on clock %s\n", __func__, c->name);
201 tegra2_clk_m_autodetect_rate(c);
202 }
203
204 static int tegra2_clk_m_enable(struct clk *c)
205 {
206 pr_debug("%s on clock %s\n", __func__, c->name);
207 return 0;
208 }
209
210 static void tegra2_clk_m_disable(struct clk *c)
211 {
212 pr_debug("%s on clock %s\n", __func__, c->name);
213 BUG();
214 }
215
216 static struct clk_ops tegra_clk_m_ops = {
217 .init = tegra2_clk_m_init,
218 .enable = tegra2_clk_m_enable,
219 .disable = tegra2_clk_m_disable,
220 };
221
222 /* super clock functions */
223 /* "super clocks" on tegra have two-stage muxes and a clock skipping
224 * super divider. We will ignore the clock skipping divider, since we
225 * can't lower the voltage when using the clock skip, but we can if we
226 * lower the PLL frequency.
227 */
228 static void tegra2_super_clk_init(struct clk *c)
229 {
230 u32 val;
231 int source;
232 int shift;
233 const struct clk_mux_sel *sel;
234 val = clk_readl(c->reg + SUPER_CLK_MUX);
235 c->state = ON;
236 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
237 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
238 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
239 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
240 source = (val >> shift) & SUPER_SOURCE_MASK;
241 for (sel = c->inputs; sel->input != NULL; sel++) {
242 if (sel->value == source)
243 break;
244 }
245 BUG_ON(sel->input == NULL);
246 c->parent = sel->input;
247 tegra2_clk_recalculate_rate(c);
248 }
249
250 static int tegra2_super_clk_enable(struct clk *c)
251 {
252 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
253 return 0;
254 }
255
256 static void tegra2_super_clk_disable(struct clk *c)
257 {
258 pr_debug("%s on clock %s\n", __func__, c->name);
259
260 /* oops - don't disable the CPU clock! */
261 BUG();
262 }
263
264 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
265 {
266 u32 val;
267 const struct clk_mux_sel *sel;
268 int shift;
269 val = clk_readl(c->reg + SUPER_CLK_MUX);;
270 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
271 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
272 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
273 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
274 for (sel = c->inputs; sel->input != NULL; sel++) {
275 if (sel->input == p) {
276 clk_reparent(c, p);
277 val &= ~(SUPER_SOURCE_MASK << shift);
278 val |= sel->value << shift;
279 clk_writel(val, c->reg);
280 c->rate = c->parent->rate;
281 return 0;
282 }
283 }
284 return -EINVAL;
285 }
286
287 static struct clk_ops tegra_super_ops = {
288 .init = tegra2_super_clk_init,
289 .enable = tegra2_super_clk_enable,
290 .disable = tegra2_super_clk_disable,
291 .set_parent = tegra2_super_clk_set_parent,
292 .recalculate_rate = tegra2_clk_recalculate_rate,
293 };
294
295 /* bus clock functions */
296 static void tegra2_bus_clk_init(struct clk *c)
297 {
298 u32 val = clk_readl(c->reg);
299 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
300 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
301 c->mul = 1;
302 tegra2_clk_recalculate_rate(c);
303 }
304
305 static int tegra2_bus_clk_enable(struct clk *c)
306 {
307 u32 val = clk_readl(c->reg);
308 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
309 clk_writel(val, c->reg);
310 return 0;
311 }
312
313 static void tegra2_bus_clk_disable(struct clk *c)
314 {
315 u32 val = clk_readl(c->reg);
316 val |= BUS_CLK_DISABLE << c->reg_shift;
317 clk_writel(val, c->reg);
318 }
319
320 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
321 {
322 u32 val = clk_readl(c->reg);
323 unsigned long parent_rate = c->parent->rate;
324 int i;
325 for (i = 1; i <= 4; i++) {
326 if (rate == parent_rate / i) {
327 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
328 val |= (i - 1) << c->reg_shift;
329 clk_writel(val, c->reg);
330 c->div = i;
331 c->mul = 1;
332 return 0;
333 }
334 }
335 return -EINVAL;
336 }
337
338 static struct clk_ops tegra_bus_ops = {
339 .init = tegra2_bus_clk_init,
340 .enable = tegra2_bus_clk_enable,
341 .disable = tegra2_bus_clk_disable,
342 .set_rate = tegra2_bus_clk_set_rate,
343 .recalculate_rate = tegra2_clk_recalculate_rate,
344 };
345
346 /* PLL Functions */
347 static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
348 {
349 u64 rate;
350 rate = c->parent->rate;
351 rate *= c->n;
352 do_div(rate, c->m);
353 if (c->p == 2)
354 rate >>= 1;
355 c->rate = rate;
356 return c->rate;
357 }
358
359 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
360 {
361 ktime_t before;
362
363 before = ktime_get();
364 while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
365 if (ktime_us_delta(ktime_get(), before) > 5000) {
366 pr_err("Timed out waiting for lock bit on pll %s",
367 c->name);
368 return -1;
369 }
370 }
371
372 return 0;
373 }
374
375 static void tegra2_pll_clk_init(struct clk *c)
376 {
377 u32 val = clk_readl(c->reg + PLL_BASE);
378
379 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
380
381 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
382 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
383 c->n = 1;
384 c->m = 0;
385 c->p = 1;
386 } else if (val & PLL_BASE_BYPASS) {
387 c->n = 1;
388 c->m = 1;
389 c->p = 1;
390 } else {
391 c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
392 c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
393 c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
394 }
395
396 val = clk_readl(c->reg + PLL_MISC(c));
397 if (c->flags & PLL_HAS_CPCON)
398 c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT;
399
400 tegra2_pll_clk_recalculate_rate(c);
401 }
402
403 static int tegra2_pll_clk_enable(struct clk *c)
404 {
405 u32 val;
406 pr_debug("%s on clock %s\n", __func__, c->name);
407
408 val = clk_readl(c->reg + PLL_BASE);
409 val &= ~PLL_BASE_BYPASS;
410 val |= PLL_BASE_ENABLE;
411 clk_writel(val, c->reg + PLL_BASE);
412
413 val = clk_readl(c->reg + PLL_MISC(c));
414 val |= PLL_MISC_LOCK_ENABLE;
415 clk_writel(val, c->reg + PLL_MISC(c));
416
417 tegra2_pll_clk_wait_for_lock(c);
418
419 return 0;
420 }
421
422 static void tegra2_pll_clk_disable(struct clk *c)
423 {
424 u32 val;
425 pr_debug("%s on clock %s\n", __func__, c->name);
426
427 val = clk_readl(c->reg);
428 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
429 clk_writel(val, c->reg);
430 }
431
432 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
433 {
434 u32 val;
435 unsigned long input_rate;
436 const struct clk_pll_table *sel;
437
438 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
439 BUG_ON(c->refcnt != 0);
440
441 input_rate = c->parent->rate;
442 for (sel = c->pll_table; sel->input_rate != 0; sel++) {
443 if (sel->input_rate == input_rate && sel->output_rate == rate) {
444 c->n = sel->n;
445 c->m = sel->m;
446 c->p = sel->p;
447 c->cpcon = sel->cpcon;
448
449 val = clk_readl(c->reg + PLL_BASE);
450 if (c->flags & PLL_FIXED)
451 val |= PLL_BASE_OVERRIDE;
452 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
453 PLL_BASE_DIVM_MASK);
454 val |= (c->m << PLL_BASE_DIVM_SHIFT) |
455 (c->n << PLL_BASE_DIVN_SHIFT);
456 BUG_ON(c->p > 2);
457 if (c->p == 2)
458 val |= 1 << PLL_BASE_DIVP_SHIFT;
459 clk_writel(val, c->reg + PLL_BASE);
460
461 if (c->flags & PLL_HAS_CPCON) {
462 val = c->cpcon << PLL_MISC_CPCON_SHIFT;
463 val |= PLL_MISC_LOCK_ENABLE;
464 clk_writel(val, c->reg + PLL_MISC(c));
465 }
466
467 if (c->state == ON)
468 tegra2_pll_clk_enable(c);
469
470 c->rate = rate;
471 return 0;
472 }
473 }
474 return -EINVAL;
475 }
476
477 static struct clk_ops tegra_pll_ops = {
478 .init = tegra2_pll_clk_init,
479 .enable = tegra2_pll_clk_enable,
480 .disable = tegra2_pll_clk_disable,
481 .set_rate = tegra2_pll_clk_set_rate,
482 .recalculate_rate = tegra2_pll_clk_recalculate_rate,
483 };
484
485 /* Clock divider ops */
486 static void tegra2_pll_div_clk_init(struct clk *c)
487 {
488 u32 val = clk_readl(c->reg);
489 u32 divu71;
490 val >>= c->reg_shift;
491 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
492 if (!(val & PLL_OUT_RESET_DISABLE))
493 c->state = OFF;
494
495 if (c->flags & DIV_U71) {
496 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
497 c->div = (divu71 + 2);
498 c->mul = 2;
499 } else if (c->flags & DIV_2) {
500 c->div = 2;
501 c->mul = 1;
502 } else {
503 c->div = 1;
504 c->mul = 1;
505 }
506
507 tegra2_clk_recalculate_rate(c);
508 }
509
510 static int tegra2_pll_div_clk_enable(struct clk *c)
511 {
512 u32 val;
513 u32 new_val;
514
515 pr_debug("%s: %s\n", __func__, c->name);
516 if (c->flags & DIV_U71) {
517 val = clk_readl(c->reg);
518 new_val = val >> c->reg_shift;
519 new_val &= 0xFFFF;
520
521 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
522
523 val &= ~(0xFFFF << c->reg_shift);
524 val |= new_val << c->reg_shift;
525 clk_writel(val, c->reg);
526 return 0;
527 } else if (c->flags & DIV_2) {
528 BUG_ON(!(c->flags & PLLD));
529 val = clk_readl(c->reg);
530 val &= ~PLLD_MISC_DIV_RST;
531 clk_writel(val, c->reg);
532 return 0;
533 }
534 return -EINVAL;
535 }
536
537 static void tegra2_pll_div_clk_disable(struct clk *c)
538 {
539 u32 val;
540 u32 new_val;
541
542 pr_debug("%s: %s\n", __func__, c->name);
543 if (c->flags & DIV_U71) {
544 val = clk_readl(c->reg);
545 new_val = val >> c->reg_shift;
546 new_val &= 0xFFFF;
547
548 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
549
550 val &= ~(0xFFFF << c->reg_shift);
551 val |= new_val << c->reg_shift;
552 clk_writel(val, c->reg);
553 } else if (c->flags & DIV_2) {
554 BUG_ON(!(c->flags & PLLD));
555 val = clk_readl(c->reg);
556 val |= PLLD_MISC_DIV_RST;
557 clk_writel(val, c->reg);
558 }
559 }
560
561 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
562 {
563 u32 val;
564 u32 new_val;
565 int divider_u71;
566 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
567 if (c->flags & DIV_U71) {
568 divider_u71 = clk_div71_get_divider(c->parent, rate);
569 if (divider_u71 >= 0) {
570 val = clk_readl(c->reg);
571 new_val = val >> c->reg_shift;
572 new_val &= 0xFFFF;
573 if (c->flags & DIV_U71_FIXED)
574 new_val |= PLL_OUT_OVERRIDE;
575 new_val &= ~PLL_OUT_RATIO_MASK;
576 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
577
578 val &= ~(0xFFFF << c->reg_shift);
579 val |= new_val << c->reg_shift;
580 clk_writel(val, c->reg);
581 c->div = divider_u71 + 2;
582 c->mul = 2;
583 tegra2_clk_recalculate_rate(c);
584 return 0;
585 }
586 } else if (c->flags & DIV_2) {
587 if (c->parent->rate == rate * 2) {
588 c->rate = rate;
589 return 0;
590 }
591 }
592 return -EINVAL;
593 }
594
595
596 static struct clk_ops tegra_pll_div_ops = {
597 .init = tegra2_pll_div_clk_init,
598 .enable = tegra2_pll_div_clk_enable,
599 .disable = tegra2_pll_div_clk_disable,
600 .set_rate = tegra2_pll_div_clk_set_rate,
601 .recalculate_rate = tegra2_clk_recalculate_rate,
602 };
603
604 /* Periph clk ops */
605
606 static void tegra2_periph_clk_init(struct clk *c)
607 {
608 u32 val = clk_readl(c->reg);
609 const struct clk_mux_sel *mux = 0;
610 const struct clk_mux_sel *sel;
611 if (c->flags & MUX) {
612 for (sel = c->inputs; sel->input != NULL; sel++) {
613 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
614 mux = sel;
615 }
616 BUG_ON(!mux);
617
618 c->parent = mux->input;
619 } else {
620 c->parent = c->inputs[0].input;
621 }
622
623 if (c->flags & DIV_U71) {
624 u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK;
625 c->div = divu71 + 2;
626 c->mul = 2;
627 } else {
628 c->div = 1;
629 c->mul = 1;
630 }
631
632 c->state = ON;
633 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
634 PERIPH_CLK_TO_ENB_BIT(c)))
635 c->state = OFF;
636 if (!(c->flags & PERIPH_NO_RESET))
637 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
638 PERIPH_CLK_TO_ENB_BIT(c))
639 c->state = OFF;
640 tegra2_clk_recalculate_rate(c);
641 }
642
643 static int tegra2_periph_clk_enable(struct clk *c)
644 {
645 u32 val;
646 pr_debug("%s on clock %s\n", __func__, c->name);
647
648 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
649 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
650 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
651 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
652 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
653 if (c->flags & PERIPH_EMC_ENB) {
654 /* The EMC peripheral clock has 2 extra enable bits */
655 val = clk_readl(c->reg);
656 val |= 0x3 << 24;
657 clk_writel(val, c->reg);
658 }
659 return 0;
660 }
661
662 static void tegra2_periph_clk_disable(struct clk *c)
663 {
664 pr_debug("%s on clock %s\n", __func__, c->name);
665
666 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
667 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
668 }
669
670 void tegra2_periph_reset_deassert(struct clk *c)
671 {
672 pr_debug("%s on clock %s\n", __func__, c->name);
673 if (!(c->flags & PERIPH_NO_RESET))
674 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
675 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
676 }
677
678 void tegra2_periph_reset_assert(struct clk *c)
679 {
680 pr_debug("%s on clock %s\n", __func__, c->name);
681 if (!(c->flags & PERIPH_NO_RESET))
682 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
683 RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
684 }
685
686
687 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
688 {
689 u32 val;
690 const struct clk_mux_sel *sel;
691 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
692 for (sel = c->inputs; sel->input != NULL; sel++) {
693 if (sel->input == p) {
694 clk_reparent(c, p);
695 val = clk_readl(c->reg);
696 val &= ~PERIPH_CLK_SOURCE_MASK;
697 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
698 clk_writel(val, c->reg);
699 c->rate = c->parent->rate;
700 return 0;
701 }
702 }
703
704 return -EINVAL;
705 }
706
707 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
708 {
709 u32 val;
710 int divider_u71;
711 pr_debug("%s: %lu\n", __func__, rate);
712 if (c->flags & DIV_U71) {
713 divider_u71 = clk_div71_get_divider(c->parent, rate);
714 if (divider_u71 >= 0) {
715 val = clk_readl(c->reg);
716 val &= ~PERIPH_CLK_SOURCE_DIV_MASK;
717 val |= divider_u71;
718 clk_writel(val, c->reg);
719 c->div = divider_u71 + 2;
720 c->mul = 2;
721 tegra2_clk_recalculate_rate(c);
722 return 0;
723 }
724 }
725 return -EINVAL;
726 }
727
728 static struct clk_ops tegra_periph_clk_ops = {
729 .init = &tegra2_periph_clk_init,
730 .enable = &tegra2_periph_clk_enable,
731 .disable = &tegra2_periph_clk_disable,
732 .set_parent = &tegra2_periph_clk_set_parent,
733 .set_rate = &tegra2_periph_clk_set_rate,
734 .recalculate_rate = &tegra2_clk_recalculate_rate,
735 };
736
737 /* Clock doubler ops */
738 static void tegra2_clk_double_init(struct clk *c)
739 {
740 c->mul = 2;
741 c->div = 1;
742 c->state = ON;
743 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
744 PERIPH_CLK_TO_ENB_BIT(c)))
745 c->state = OFF;
746 tegra2_clk_recalculate_rate(c);
747 };
748
749 static struct clk_ops tegra_clk_double_ops = {
750 .init = &tegra2_clk_double_init,
751 .enable = &tegra2_periph_clk_enable,
752 .disable = &tegra2_periph_clk_disable,
753 .recalculate_rate = &tegra2_clk_recalculate_rate,
754 };
755
756 /* Clock definitions */
757 static struct clk tegra_clk_32k = {
758 .name = "clk_32k",
759 .rate = 32678,
760 .ops = NULL,
761 };
762
763 static struct clk_pll_table tegra_pll_s_table[] = {
764 {32768, 12000000, 366, 1, 1, 0},
765 {32768, 13000000, 397, 1, 1, 0},
766 {32768, 19200000, 586, 1, 1, 0},
767 {32768, 26000000, 793, 1, 1, 0},
768 {0, 0, 0, 0, 0, 0},
769 };
770
771 static struct clk tegra_pll_s = {
772 .name = "pll_s",
773 .flags = PLL_ALT_MISC_REG,
774 .ops = &tegra_pll_ops,
775 .reg = 0xf0,
776 .input_min = 32768,
777 .input_max = 32768,
778 .parent = &tegra_clk_32k,
779 .cf_min = 0,
780 .cf_max = 0,
781 .vco_min = 12000000,
782 .vco_max = 26000000,
783 .pll_table = tegra_pll_s_table,
784 };
785
786 static struct clk_mux_sel tegra_clk_m_sel[] = {
787 { .input = &tegra_clk_32k, .value = 0},
788 { .input = &tegra_pll_s, .value = 1},
789 { 0, 0},
790 };
791 static struct clk tegra_clk_m = {
792 .name = "clk_m",
793 .flags = ENABLE_ON_INIT,
794 .ops = &tegra_clk_m_ops,
795 .inputs = tegra_clk_m_sel,
796 .reg = 0x1fc,
797 .reg_mask = (1<<28),
798 .reg_shift = 28,
799 };
800
801 static struct clk_pll_table tegra_pll_c_table[] = {
802 { 0, 0, 0, 0, 0, 0 },
803 };
804
805 static struct clk tegra_pll_c = {
806 .name = "pll_c",
807 .flags = PLL_HAS_CPCON,
808 .ops = &tegra_pll_ops,
809 .reg = 0x80,
810 .input_min = 2000000,
811 .input_max = 31000000,
812 .parent = &tegra_clk_m,
813 .cf_min = 1000000,
814 .cf_max = 6000000,
815 .vco_min = 20000000,
816 .vco_max = 1400000000,
817 .pll_table = tegra_pll_c_table,
818 };
819
820 static struct clk tegra_pll_c_out1 = {
821 .name = "pll_c_out1",
822 .ops = &tegra_pll_div_ops,
823 .flags = DIV_U71,
824 .parent = &tegra_pll_c,
825 .reg = 0x84,
826 .reg_shift = 0,
827 };
828
829 static struct clk_pll_table tegra_pll_m_table[] = {
830 { 0, 0, 0, 0, 0, 0 },
831 };
832
833 static struct clk tegra_pll_m = {
834 .name = "pll_m",
835 .flags = PLL_HAS_CPCON,
836 .ops = &tegra_pll_ops,
837 .reg = 0x90,
838 .input_min = 2000000,
839 .input_max = 31000000,
840 .parent = &tegra_clk_m,
841 .cf_min = 1000000,
842 .cf_max = 6000000,
843 .vco_min = 20000000,
844 .vco_max = 1200000000,
845 .pll_table = tegra_pll_m_table,
846 };
847
848 static struct clk tegra_pll_m_out1 = {
849 .name = "pll_m_out1",
850 .ops = &tegra_pll_div_ops,
851 .flags = DIV_U71,
852 .parent = &tegra_pll_m,
853 .reg = 0x94,
854 .reg_shift = 0,
855 };
856
857 static struct clk_pll_table tegra_pll_p_table[] = {
858 { 12000000, 216000000, 432, 12, 2, 8},
859 { 13000000, 216000000, 432, 13, 2, 8},
860 { 19200000, 216000000, 90, 4, 2, 1},
861 { 26000000, 216000000, 432, 26, 2, 8},
862 { 12000000, 432000000, 432, 12, 1, 8},
863 { 13000000, 432000000, 432, 13, 1, 8},
864 { 19200000, 432000000, 90, 4, 1, 1},
865 { 26000000, 432000000, 432, 26, 1, 8},
866 { 0, 0, 0, 0, 0, 0 },
867 };
868
869 static struct clk tegra_pll_p = {
870 .name = "pll_p",
871 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
872 .ops = &tegra_pll_ops,
873 .reg = 0xa0,
874 .input_min = 2000000,
875 .input_max = 31000000,
876 .parent = &tegra_clk_m,
877 .cf_min = 1000000,
878 .cf_max = 6000000,
879 .vco_min = 20000000,
880 .vco_max = 1400000000,
881 .pll_table = tegra_pll_p_table,
882 };
883
884 static struct clk tegra_pll_p_out1 = {
885 .name = "pll_p_out1",
886 .ops = &tegra_pll_div_ops,
887 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
888 .parent = &tegra_pll_p,
889 .reg = 0xa4,
890 .reg_shift = 0,
891 };
892
893 static struct clk tegra_pll_p_out2 = {
894 .name = "pll_p_out2",
895 .ops = &tegra_pll_div_ops,
896 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
897 .parent = &tegra_pll_p,
898 .reg = 0xa4,
899 .reg_shift = 16,
900 };
901
902 static struct clk tegra_pll_p_out3 = {
903 .name = "pll_p_out3",
904 .ops = &tegra_pll_div_ops,
905 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
906 .parent = &tegra_pll_p,
907 .reg = 0xa8,
908 .reg_shift = 0,
909 };
910
911 static struct clk tegra_pll_p_out4 = {
912 .name = "pll_p_out4",
913 .ops = &tegra_pll_div_ops,
914 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
915 .parent = &tegra_pll_p,
916 .reg = 0xa8,
917 .reg_shift = 16,
918 };
919
920 static struct clk_pll_table tegra_pll_a_table[] = {
921 { 28800000, 56448000, 49, 25, 1, 1},
922 { 28800000, 73728000, 64, 25, 1, 1},
923 { 28800000, 11289600, 49, 25, 1, 1},
924 { 28800000, 12288000, 64, 25, 1, 1},
925 { 0, 0, 0, 0, 0, 0 },
926 };
927
928 static struct clk tegra_pll_a = {
929 .name = "pll_a",
930 .flags = PLL_HAS_CPCON,
931 .ops = &tegra_pll_ops,
932 .reg = 0xb0,
933 .input_min = 2000000,
934 .input_max = 31000000,
935 .parent = &tegra_pll_p_out1,
936 .cf_min = 1000000,
937 .cf_max = 6000000,
938 .vco_min = 20000000,
939 .vco_max = 1400000000,
940 .pll_table = tegra_pll_a_table,
941 };
942
943 static struct clk tegra_pll_a_out0 = {
944 .name = "pll_a_out0",
945 .ops = &tegra_pll_div_ops,
946 .flags = DIV_U71,
947 .parent = &tegra_pll_a,
948 .reg = 0xb4,
949 .reg_shift = 0,
950 };
951
952 static struct clk_pll_table tegra_pll_d_table[] = {
953 { 12000000, 1000000000, 1000, 12, 1, 12},
954 { 13000000, 1000000000, 1000, 13, 1, 12},
955 { 19200000, 1000000000, 625, 12, 1, 8},
956 { 26000000, 1000000000, 1000, 26, 1, 12},
957 { 0, 0, 0, 0, 0, 0 },
958 };
959
960 static struct clk tegra_pll_d = {
961 .name = "pll_d",
962 .flags = PLL_HAS_CPCON | PLLD,
963 .ops = &tegra_pll_ops,
964 .reg = 0xd0,
965 .input_min = 2000000,
966 .input_max = 40000000,
967 .parent = &tegra_clk_m,
968 .cf_min = 1000000,
969 .cf_max = 6000000,
970 .vco_min = 40000000,
971 .vco_max = 1000000000,
972 .pll_table = tegra_pll_d_table,
973 };
974
975 static struct clk tegra_pll_d_out0 = {
976 .name = "pll_d_out0",
977 .ops = &tegra_pll_div_ops,
978 .flags = DIV_2 | PLLD,
979 .parent = &tegra_pll_d,
980 };
981
982 static struct clk_pll_table tegra_pll_u_table[] = {
983 { 12000000, 480000000, 960, 12, 1, 0},
984 { 13000000, 480000000, 960, 13, 1, 0},
985 { 19200000, 480000000, 200, 4, 1, 0},
986 { 26000000, 480000000, 960, 26, 1, 0},
987 { 0, 0, 0, 0, 0, 0 },
988 };
989
990 static struct clk tegra_pll_u = {
991 .name = "pll_u",
992 .flags = 0,
993 .ops = &tegra_pll_ops,
994 .reg = 0xc0,
995 .input_min = 2000000,
996 .input_max = 40000000,
997 .parent = &tegra_clk_m,
998 .cf_min = 1000000,
999 .cf_max = 6000000,
1000 .vco_min = 480000000,
1001 .vco_max = 960000000,
1002 .pll_table = tegra_pll_u_table,
1003 };
1004
1005 static struct clk_pll_table tegra_pll_x_table[] = {
1006 { 12000000, 1000000000, 1000, 12, 1, 12},
1007 { 13000000, 1000000000, 1000, 13, 1, 12},
1008 { 19200000, 1000000000, 625, 12, 1, 8},
1009 { 26000000, 1000000000, 1000, 26, 1, 12},
1010 { 12000000, 750000000, 750, 12, 1, 12},
1011 { 13000000, 750000000, 750, 13, 1, 12},
1012 { 19200000, 750000000, 625, 16, 1, 8},
1013 { 26000000, 750000000, 750, 26, 1, 12},
1014 { 0, 0, 0, 0, 0, 0 },
1015 };
1016
1017 static struct clk tegra_pll_x = {
1018 .name = "pll_x",
1019 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1020 .ops = &tegra_pll_ops,
1021 .reg = 0xe0,
1022 .input_min = 2000000,
1023 .input_max = 31000000,
1024 .parent = &tegra_clk_m,
1025 .cf_min = 1000000,
1026 .cf_max = 6000000,
1027 .vco_min = 20000000,
1028 .vco_max = 1200000000,
1029 .pll_table = tegra_pll_x_table,
1030 };
1031
1032 static struct clk tegra_clk_d = {
1033 .name = "clk_d",
1034 .flags = PERIPH_NO_RESET,
1035 .ops = &tegra_clk_double_ops,
1036 .clk_num = 90,
1037 .reg = 0x34,
1038 .reg_shift = 12,
1039 .parent = &tegra_clk_m,
1040 };
1041
1042
1043 static struct clk_mux_sel mux_cclk[] = {
1044 { .input = &tegra_clk_m, .value = 0},
1045 { .input = &tegra_pll_c, .value = 1},
1046 { .input = &tegra_clk_32k, .value = 2},
1047 { .input = &tegra_pll_m, .value = 3},
1048 { .input = &tegra_pll_p, .value = 4},
1049 { .input = &tegra_pll_p_out4, .value = 5},
1050 { .input = &tegra_pll_p_out3, .value = 6},
1051 { .input = &tegra_clk_d, .value = 7},
1052 { .input = &tegra_pll_x, .value = 8},
1053 { 0, 0},
1054 };
1055
1056 static struct clk_mux_sel mux_sclk[] = {
1057 { .input = &tegra_clk_m, .value = 0},
1058 { .input = &tegra_pll_c_out1, .value = 1},
1059 { .input = &tegra_pll_p_out4, .value = 2},
1060 { .input = &tegra_pll_p_out3, .value = 3},
1061 { .input = &tegra_pll_p_out2, .value = 4},
1062 { .input = &tegra_clk_d, .value = 5},
1063 { .input = &tegra_clk_32k, .value = 6},
1064 { .input = &tegra_pll_m_out1, .value = 7},
1065 { 0, 0},
1066 };
1067
1068 static struct clk tegra_clk_cpu = {
1069 .name = "cpu",
1070 .inputs = mux_cclk,
1071 .reg = 0x20,
1072 .ops = &tegra_super_ops,
1073 };
1074
1075 static struct clk tegra_clk_sys = {
1076 .name = "sys",
1077 .inputs = mux_sclk,
1078 .reg = 0x28,
1079 .ops = &tegra_super_ops,
1080 };
1081
1082 static struct clk tegra_clk_hclk = {
1083 .name = "hclk",
1084 .flags = DIV_BUS,
1085 .parent = &tegra_clk_sys,
1086 .reg = 0x30,
1087 .reg_shift = 4,
1088 .ops = &tegra_bus_ops,
1089 };
1090
1091 static struct clk tegra_clk_pclk = {
1092 .name = "pclk",
1093 .flags = DIV_BUS,
1094 .parent = &tegra_clk_hclk,
1095 .reg = 0x30,
1096 .reg_shift = 0,
1097 .ops = &tegra_bus_ops,
1098 };
1099
1100 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1101 { .input = &tegra_pll_m, .value = 0},
1102 { .input = &tegra_pll_c, .value = 1},
1103 { .input = &tegra_pll_p, .value = 2},
1104 { .input = &tegra_pll_a_out0, .value = 3},
1105 { 0, 0},
1106 };
1107
1108 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1109 { .input = &tegra_pll_m, .value = 0},
1110 { .input = &tegra_pll_c, .value = 1},
1111 { .input = &tegra_pll_p, .value = 2},
1112 { .input = &tegra_clk_m, .value = 3},
1113 { 0, 0},
1114 };
1115
1116 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1117 { .input = &tegra_pll_p, .value = 0},
1118 { .input = &tegra_pll_c, .value = 1},
1119 { .input = &tegra_pll_m, .value = 2},
1120 { .input = &tegra_clk_m, .value = 3},
1121 { 0, 0},
1122 };
1123
1124 static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = {
1125 {.input = &tegra_pll_a, .value = 0},
1126 {.input = &tegra_pll_p, .value = 2},
1127 {.input = &tegra_clk_m, .value = 3},
1128 { 0, 0},
1129 };
1130
1131 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1132 {.input = &tegra_pll_p, .value = 0},
1133 {.input = &tegra_pll_d_out0, .value = 1},
1134 {.input = &tegra_pll_c, .value = 2},
1135 {.input = &tegra_clk_m, .value = 3},
1136 { 0, 0},
1137 };
1138
1139 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1140 {.input = &tegra_pll_p, .value = 0},
1141 {.input = &tegra_pll_c, .value = 1},
1142 {.input = &tegra_clk_m, .value = 3},
1143 {.input = &tegra_clk_32k, .value = 4},
1144 { 0, 0},
1145 };
1146
1147 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1148 {.input = &tegra_pll_p, .value = 0},
1149 {.input = &tegra_pll_c, .value = 1},
1150 {.input = &tegra_pll_m, .value = 2},
1151 { 0, 0},
1152 };
1153
1154 static struct clk_mux_sel mux_clk_m[] = {
1155 { .input = &tegra_clk_m, .value = 0},
1156 { 0, 0},
1157 };
1158
1159 static struct clk_mux_sel mux_pllp_out3[] = {
1160 { .input = &tegra_pll_p_out3, .value = 0},
1161 { 0, 0},
1162 };
1163
1164 static struct clk_mux_sel mux_plld[] = {
1165 { .input = &tegra_pll_d, .value = 0},
1166 { 0, 0},
1167 };
1168
1169 static struct clk_mux_sel mux_clk_32k[] = {
1170 { .input = &tegra_clk_32k, .value = 0},
1171 { 0, 0},
1172 };
1173
1174 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \
1175 { \
1176 .name = _name, \
1177 .lookup = { \
1178 .dev_id = _dev, \
1179 .con_id = _con, \
1180 }, \
1181 .ops = &tegra_periph_clk_ops, \
1182 .clk_num = _clk_num, \
1183 .reg = _reg, \
1184 .inputs = _inputs, \
1185 .flags = _flags, \
1186 }
1187
1188 struct clk tegra_periph_clks[] = {
1189 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, mux_clk_32k, PERIPH_NO_RESET),
1190 PERIPH_CLK("timer", "timer", NULL, 5, 0, mux_clk_m, 0),
1191 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, mux_plla_audio_pllp_clkm, MUX | DIV_U71),
1192 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, mux_plla_audio_pllp_clkm, MUX | DIV_U71),
1193 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, mux_plla_audio_pllp_clkm, MUX | DIV_U71),
1194 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, mux_pllp_pllc_pllm, MUX | DIV_U71),
1195 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1196 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1197 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1198 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1199 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1200 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1201 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1202 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1203 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1204 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1205 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1206 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1207 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1208 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1209 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x160, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1210 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1211 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1212 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1213 PERIPH_CLK("owr", "owr", NULL, 71, 0x1cc, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1214 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1215 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1216 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1217 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1218 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1219 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1220 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, mux_pllp_out3, 0),
1221 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, mux_pllp_out3, 0),
1222 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, mux_pllp_out3, 0),
1223 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, mux_pllp_out3, 0),
1224 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1225 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1226 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1227 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1228 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1229 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET),
1230 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71),
1231 PERIPH_CLK("vi", "vi", NULL, 20, 0x148, mux_pllm_pllc_pllp_plla, MUX | DIV_U71),
1232 PERIPH_CLK("vi_sensor", "vi_sensor", NULL, 20, 0x1a8, mux_pllm_pllc_pllp_plla, MUX | DIV_U71),
1233 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, mux_pllm_pllc_pllp_plla, MUX | DIV_U71),
1234 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, mux_pllm_pllc_pllp_plla, MUX | DIV_U71),
1235 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, mux_pllm_pllc_pllp_plla, MUX | DIV_U71),
1236 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, mux_pllp_plld_pllc_clkm, MUX | DIV_U71),
1237 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, mux_pllp_plld_pllc_clkm, MUX | DIV_U71),
1238 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71),
1239 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, mux_pllp_plld_pllc_clkm, MUX | DIV_U71),
1240 PERIPH_CLK("disp1", "tegrafb.0", NULL, 27, 0x138, mux_pllp_plld_pllc_clkm, MUX | DIV_U71),
1241 PERIPH_CLK("disp2", "tegrafb.1", NULL, 26, 0x13c, mux_pllp_plld_pllc_clkm, MUX | DIV_U71),
1242 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, mux_clk_m, 0),
1243 PERIPH_CLK("usb2", "usb.1", NULL, 58, 0, mux_clk_m, 0),
1244 PERIPH_CLK("usb3", "usb.2", NULL, 59, 0, mux_clk_m, 0),
1245 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
1246 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, mux_plld, 0),
1247 };
1248
1249 #define CLK_DUPLICATE(_name, _dev, _con) \
1250 { \
1251 .name = _name, \
1252 .lookup = { \
1253 .dev_id = _dev, \
1254 .con_id = _con, \
1255 }, \
1256 }
1257
1258 /* Some clocks may be used by different drivers depending on the board
1259 * configuration. List those here to register them twice in the clock lookup
1260 * table under two names.
1261 */
1262 struct clk_duplicate tegra_clk_duplicates[] = {
1263 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
1264 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
1265 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
1266 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
1267 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
1268 };
1269
1270 #define CLK(dev, con, ck) \
1271 { \
1272 .dev_id = dev, \
1273 .con_id = con, \
1274 .clk = ck, \
1275 }
1276
1277 struct clk_lookup tegra_clk_lookups[] = {
1278 /* external root sources */
1279 CLK(NULL, "32k_clk", &tegra_clk_32k),
1280 CLK(NULL, "pll_s", &tegra_pll_s),
1281 CLK(NULL, "clk_m", &tegra_clk_m),
1282 CLK(NULL, "pll_m", &tegra_pll_m),
1283 CLK(NULL, "pll_m_out1", &tegra_pll_m_out1),
1284 CLK(NULL, "pll_c", &tegra_pll_c),
1285 CLK(NULL, "pll_c_out1", &tegra_pll_c_out1),
1286 CLK(NULL, "pll_p", &tegra_pll_p),
1287 CLK(NULL, "pll_p_out1", &tegra_pll_p_out1),
1288 CLK(NULL, "pll_p_out2", &tegra_pll_p_out2),
1289 CLK(NULL, "pll_p_out3", &tegra_pll_p_out3),
1290 CLK(NULL, "pll_p_out4", &tegra_pll_p_out4),
1291 CLK(NULL, "pll_a", &tegra_pll_a),
1292 CLK(NULL, "pll_a_out0", &tegra_pll_a_out0),
1293 CLK(NULL, "pll_d", &tegra_pll_d),
1294 CLK(NULL, "pll_d_out0", &tegra_pll_d_out0),
1295 CLK(NULL, "pll_u", &tegra_pll_u),
1296 CLK(NULL, "pll_x", &tegra_pll_x),
1297 CLK(NULL, "cpu", &tegra_clk_cpu),
1298 CLK(NULL, "sys", &tegra_clk_sys),
1299 CLK(NULL, "hclk", &tegra_clk_hclk),
1300 CLK(NULL, "pclk", &tegra_clk_pclk),
1301 CLK(NULL, "clk_d", &tegra_clk_d),
1302 };
1303
1304 void __init tegra2_init_clocks(void)
1305 {
1306 int i;
1307 struct clk_lookup *cl;
1308 struct clk *c;
1309 struct clk_duplicate *cd;
1310
1311 for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) {
1312 cl = &tegra_clk_lookups[i];
1313 clk_init(cl->clk);
1314 clkdev_add(cl);
1315 }
1316
1317 for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) {
1318 c = &tegra_periph_clks[i];
1319 cl = &c->lookup;
1320 cl->clk = c;
1321
1322 clk_init(cl->clk);
1323 clkdev_add(cl);
1324 }
1325
1326 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
1327 cd = &tegra_clk_duplicates[i];
1328 c = tegra_get_clock_by_name(cd->name);
1329 if (c) {
1330 cl = &cd->lookup;
1331 cl->clk = c;
1332 clkdev_add(cl);
1333 } else {
1334 pr_err("%s: Unknown duplicate clock %s\n", __func__,
1335 cd->name);
1336 }
1337 }
1338 }
Tomato firmware and modifications.