release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5pv210/setup-fb-24bpp.c

   1 /* linux/arch/arm/plat-s5pv210/setup-fb-24bpp.c
   2  *
   3  * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * Base s5pv210 setup information for 24bpp LCD framebuffer
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/types.h>
  15 #include <linux/fb.h>
  16 #include <linux/gpio.h>
  17
  18 #include <mach/regs-fb.h>
  19 #include <mach/map.h>
  20 #include <plat/fb.h>
  21 #include <mach/regs-clock.h>
  22 #include <plat/gpio-cfg.h>
  23
  24 void s5pv210_fb_gpio_setup_24bpp(void)
  25 {
  26         unsigned int gpio = 0;
  27
  28         for (gpio = S5PV210_GPF0(0); gpio <= S5PV210_GPF0(7); gpio++) {
  29                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
  30                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
  31                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
  32         }
  33
  34         for (gpio = S5PV210_GPF1(0); gpio <= S5PV210_GPF1(7); gpio++) {
  35                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
  36                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
  37                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
  38         }
  39
  40         for (gpio = S5PV210_GPF2(0); gpio <= S5PV210_GPF2(7); gpio++) {
  41                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
  42                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
  43                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
  44         }
  45
  46         for (gpio = S5PV210_GPF3(0); gpio <= S5PV210_GPF3(3); gpio++) {
  47                 s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
  48                 s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
  49                 s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
  50         }
  51
  52         /* Set DISPLAY_CONTROL register for Display path selection.
  53          *
  54          * ouput   |   RGB   |   I80   |   ITU
  55          * -----------------------------------
  56          *  00     |   MIE   |  FIMD   |  FIMD
  57          *  01     | MDNIE   | MDNIE   |  FIMD
  58          *  10     |  FIMD   |  FIMD   |  FIMD
  59          *  11     |  FIMD   |  FIMD   |  FIMD
  60          */
  61         writel(0x2, S5P_MDNIE_SEL);
  62 }