release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-s5p6442/include/mach/regs-clock.h

   1 /* linux/arch/arm/mach-s5p6442/include/mach/regs-clock.h
   2  *
   3  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com/
   5  *
   6  * S5P6442 - Clock register definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11 */
  12
  13 #ifndef __ASM_ARCH_REGS_CLOCK_H
  14 #define __ASM_ARCH_REGS_CLOCK_H __FILE__
  15
  16 #include <mach/map.h>
  17
  18 #define S5P_CLKREG(x)           (S3C_VA_SYS + (x))
  19
  20 #define S5P_APLL_LOCK           S5P_CLKREG(0x00)
  21 #define S5P_MPLL_LOCK           S5P_CLKREG(0x08)
  22 #define S5P_EPLL_LOCK           S5P_CLKREG(0x10)
  23 #define S5P_VPLL_LOCK           S5P_CLKREG(0x20)
  24
  25 #define S5P_APLL_CON            S5P_CLKREG(0x100)
  26 #define S5P_MPLL_CON            S5P_CLKREG(0x108)
  27 #define S5P_EPLL_CON            S5P_CLKREG(0x110)
  28 #define S5P_VPLL_CON            S5P_CLKREG(0x120)
  29
  30 #define S5P_CLK_SRC0            S5P_CLKREG(0x200)
  31 #define S5P_CLK_SRC1            S5P_CLKREG(0x204)
  32 #define S5P_CLK_SRC2            S5P_CLKREG(0x208)
  33 #define S5P_CLK_SRC3            S5P_CLKREG(0x20C)
  34 #define S5P_CLK_SRC4            S5P_CLKREG(0x210)
  35 #define S5P_CLK_SRC5            S5P_CLKREG(0x214)
  36 #define S5P_CLK_SRC6            S5P_CLKREG(0x218)
  37
  38 #define S5P_CLK_SRC_MASK0       S5P_CLKREG(0x280)
  39 #define S5P_CLK_SRC_MASK1       S5P_CLKREG(0x284)
  40
  41 #define S5P_CLK_DIV0            S5P_CLKREG(0x300)
  42 #define S5P_CLK_DIV1            S5P_CLKREG(0x304)
  43 #define S5P_CLK_DIV2            S5P_CLKREG(0x308)
  44 #define S5P_CLK_DIV3            S5P_CLKREG(0x30C)
  45 #define S5P_CLK_DIV4            S5P_CLKREG(0x310)
  46 #define S5P_CLK_DIV5            S5P_CLKREG(0x314)
  47 #define S5P_CLK_DIV6            S5P_CLKREG(0x318)
  48
  49 #define S5P_CLKGATE_IP3         S5P_CLKREG(0x46C)
  50
  51 /* CLK_OUT */
  52 #define S5P_CLK_OUT_SHIFT       (12)
  53 #define S5P_CLK_OUT_MASK        (0x1F << S5P_CLK_OUT_SHIFT)
  54 #define S5P_CLK_OUT             S5P_CLKREG(0x500)
  55
  56 #define S5P_CLK_DIV_STAT0       S5P_CLKREG(0x1000)
  57 #define S5P_CLK_DIV_STAT1       S5P_CLKREG(0x1004)
  58
  59 #define S5P_CLK_MUX_STAT0       S5P_CLKREG(0x1100)
  60 #define S5P_CLK_MUX_STAT1       S5P_CLKREG(0x1104)
  61
  62 #define S5P_MDNIE_SEL           S5P_CLKREG(0x7008)
  63
  64 /* Register Bit definition */
  65 #define S5P_EPLL_EN                     (1<<31)
  66 #define S5P_EPLL_MASK                   0xffffffff
  67 #define S5P_EPLLVAL(_m, _p, _s)         ((_m) << 16 | ((_p) << 8) | ((_s)))
  68
  69 /* CLKDIV0 */
  70 #define S5P_CLKDIV0_APLL_SHIFT          (0)
  71 #define S5P_CLKDIV0_APLL_MASK           (0x7 << S5P_CLKDIV0_APLL_SHIFT)
  72 #define S5P_CLKDIV0_A2M_SHIFT           (4)
  73 #define S5P_CLKDIV0_A2M_MASK            (0x7 << S5P_CLKDIV0_A2M_SHIFT)
  74 #define S5P_CLKDIV0_D0CLK_SHIFT         (16)
  75 #define S5P_CLKDIV0_D0CLK_MASK          (0xF << S5P_CLKDIV0_D0CLK_SHIFT)
  76 #define S5P_CLKDIV0_P0CLK_SHIFT         (20)
  77 #define S5P_CLKDIV0_P0CLK_MASK          (0x7 << S5P_CLKDIV0_P0CLK_SHIFT)
  78 #define S5P_CLKDIV0_D1CLK_SHIFT         (24)
  79 #define S5P_CLKDIV0_D1CLK_MASK          (0xF << S5P_CLKDIV0_D1CLK_SHIFT)
  80 #define S5P_CLKDIV0_P1CLK_SHIFT         (28)
  81 #define S5P_CLKDIV0_P1CLK_MASK          (0x7 << S5P_CLKDIV0_P1CLK_SHIFT)
  82
  83 /* Clock MUX status Registers */
  84 #define S5P_CLK_MUX_STAT0_APLL_SHIFT    (0)
  85 #define S5P_CLK_MUX_STAT0_APLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_APLL_SHIFT)
  86 #define S5P_CLK_MUX_STAT0_MPLL_SHIFT    (4)
  87 #define S5P_CLK_MUX_STAT0_MPLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_MPLL_SHIFT)
  88 #define S5P_CLK_MUX_STAT0_EPLL_SHIFT    (8)
  89 #define S5P_CLK_MUX_STAT0_EPLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_EPLL_SHIFT)
  90 #define S5P_CLK_MUX_STAT0_VPLL_SHIFT    (12)
  91 #define S5P_CLK_MUX_STAT0_VPLL_MASK     (0x7 << S5P_CLK_MUX_STAT0_VPLL_SHIFT)
  92 #define S5P_CLK_MUX_STAT0_MUXARM_SHIFT  (16)
  93 #define S5P_CLK_MUX_STAT0_MUXARM_MASK   (0x7 << S5P_CLK_MUX_STAT0_MUXARM_SHIFT)
  94 #define S5P_CLK_MUX_STAT0_MUXD0_SHIFT   (20)
  95 #define S5P_CLK_MUX_STAT0_MUXD0_MASK    (0x7 << S5P_CLK_MUX_STAT0_MUXD0_SHIFT)
  96 #define S5P_CLK_MUX_STAT0_MUXD1_SHIFT   (24)
  97 #define S5P_CLK_MUX_STAT0_MUXD1_MASK    (0x7 << S5P_CLK_MUX_STAT0_MUXD1_SHIFT)
  98 #define S5P_CLK_MUX_STAT1_D1SYNC_SHIFT  (24)
  99 #define S5P_CLK_MUX_STAT1_D1SYNC_MASK   (0x7 << S5P_CLK_MUX_STAT1_D1SYNC_SHIFT)
 100 #define S5P_CLK_MUX_STAT1_D0SYNC_SHIFT  (28)
 101 #define S5P_CLK_MUX_STAT1_D0SYNC_MASK   (0x7 << S5P_CLK_MUX_STAT1_D0SYNC_SHIFT)
 102
 103 #endif /* __ASM_ARCH_REGS_CLOCK_H */