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RT-AC56 3.0.0.4.374.37 core
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / mach-omap2 / clock44xx_data.c
blobe10db7a90cb270f5f833cd1b9076bd7b6cb38356
1 /*
2 * OMAP4 Clock data
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/list.h>
24 #include <linux/clk.h>
25
26 #include <plat/control.h>
27 #include <plat/clkdev_omap.h>
28
29 #include "clock.h"
30 #include "clock44xx.h"
31 #include "cm.h"
32 #include "cm-regbits-44xx.h"
33 #include "prm.h"
34 #include "prm-regbits-44xx.h"
35
36 /* Root clocks */
37
38 static struct clk extalt_clkin_ck = {
39 .name = "extalt_clkin_ck",
40 .rate = 59000000,
41 .ops = &clkops_null,
42 };
43
44 static struct clk pad_clks_ck = {
45 .name = "pad_clks_ck",
46 .rate = 12000000,
47 .ops = &clkops_null,
48 };
49
50 static struct clk pad_slimbus_core_clks_ck = {
51 .name = "pad_slimbus_core_clks_ck",
52 .rate = 12000000,
53 .ops = &clkops_null,
54 };
55
56 static struct clk secure_32k_clk_src_ck = {
57 .name = "secure_32k_clk_src_ck",
58 .rate = 32768,
59 .ops = &clkops_null,
60 };
61
62 static struct clk slimbus_clk = {
63 .name = "slimbus_clk",
64 .rate = 12000000,
65 .ops = &clkops_null,
66 };
67
68 static struct clk sys_32k_ck = {
69 .name = "sys_32k_ck",
70 .rate = 32768,
71 .ops = &clkops_null,
72 };
73
74 static struct clk virt_12000000_ck = {
75 .name = "virt_12000000_ck",
76 .ops = &clkops_null,
77 .rate = 12000000,
78 };
79
80 static struct clk virt_13000000_ck = {
81 .name = "virt_13000000_ck",
82 .ops = &clkops_null,
83 .rate = 13000000,
84 };
85
86 static struct clk virt_16800000_ck = {
87 .name = "virt_16800000_ck",
88 .ops = &clkops_null,
89 .rate = 16800000,
90 };
91
92 static struct clk virt_19200000_ck = {
93 .name = "virt_19200000_ck",
94 .ops = &clkops_null,
95 .rate = 19200000,
96 };
97
98 static struct clk virt_26000000_ck = {
99 .name = "virt_26000000_ck",
100 .ops = &clkops_null,
101 .rate = 26000000,
102 };
103
104 static struct clk virt_27000000_ck = {
105 .name = "virt_27000000_ck",
106 .ops = &clkops_null,
107 .rate = 27000000,
108 };
109
110 static struct clk virt_38400000_ck = {
111 .name = "virt_38400000_ck",
112 .ops = &clkops_null,
113 .rate = 38400000,
114 };
115
116 static const struct clksel_rate div_1_0_rates[] = {
117 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
118 { .div = 0 },
119 };
120
121 static const struct clksel_rate div_1_1_rates[] = {
122 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
123 { .div = 0 },
124 };
125
126 static const struct clksel_rate div_1_2_rates[] = {
127 { .div = 1, .val = 2, .flags = RATE_IN_4430 },
128 { .div = 0 },
129 };
130
131 static const struct clksel_rate div_1_3_rates[] = {
132 { .div = 1, .val = 3, .flags = RATE_IN_4430 },
133 { .div = 0 },
134 };
135
136 static const struct clksel_rate div_1_4_rates[] = {
137 { .div = 1, .val = 4, .flags = RATE_IN_4430 },
138 { .div = 0 },
139 };
140
141 static const struct clksel_rate div_1_5_rates[] = {
142 { .div = 1, .val = 5, .flags = RATE_IN_4430 },
143 { .div = 0 },
144 };
145
146 static const struct clksel_rate div_1_6_rates[] = {
147 { .div = 1, .val = 6, .flags = RATE_IN_4430 },
148 { .div = 0 },
149 };
150
151 static const struct clksel_rate div_1_7_rates[] = {
152 { .div = 1, .val = 7, .flags = RATE_IN_4430 },
153 { .div = 0 },
154 };
155
156 static const struct clksel sys_clkin_sel[] = {
157 { .parent = &virt_12000000_ck, .rates = div_1_1_rates },
158 { .parent = &virt_13000000_ck, .rates = div_1_2_rates },
159 { .parent = &virt_16800000_ck, .rates = div_1_3_rates },
160 { .parent = &virt_19200000_ck, .rates = div_1_4_rates },
161 { .parent = &virt_26000000_ck, .rates = div_1_5_rates },
162 { .parent = &virt_27000000_ck, .rates = div_1_6_rates },
163 { .parent = &virt_38400000_ck, .rates = div_1_7_rates },
164 { .parent = NULL },
165 };
166
167 static struct clk sys_clkin_ck = {
168 .name = "sys_clkin_ck",
169 .rate = 38400000,
170 .clksel = sys_clkin_sel,
171 .init = &omap2_init_clksel_parent,
172 .clksel_reg = OMAP4430_CM_SYS_CLKSEL,
173 .clksel_mask = OMAP4430_SYS_CLKSEL_MASK,
174 .ops = &clkops_null,
175 .recalc = &omap2_clksel_recalc,
176 };
177
178 static struct clk utmi_phy_clkout_ck = {
179 .name = "utmi_phy_clkout_ck",
180 .rate = 12000000,
181 .ops = &clkops_null,
182 };
183
184 static struct clk xclk60mhsp1_ck = {
185 .name = "xclk60mhsp1_ck",
186 .rate = 12000000,
187 .ops = &clkops_null,
188 };
189
190 static struct clk xclk60mhsp2_ck = {
191 .name = "xclk60mhsp2_ck",
192 .rate = 12000000,
193 .ops = &clkops_null,
194 };
195
196 static struct clk xclk60motg_ck = {
197 .name = "xclk60motg_ck",
198 .rate = 60000000,
199 .ops = &clkops_null,
200 };
201
202 /* Module clocks and DPLL outputs */
203
204 static const struct clksel_rate div2_1to2_rates[] = {
205 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
206 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
207 { .div = 0 },
208 };
209
210 static const struct clksel dpll_sys_ref_clk_div[] = {
211 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
212 { .parent = NULL },
213 };
214
215 static struct clk dpll_sys_ref_clk = {
216 .name = "dpll_sys_ref_clk",
217 .parent = &sys_clkin_ck,
218 .clksel = dpll_sys_ref_clk_div,
219 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
220 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
221 .ops = &clkops_null,
222 .recalc = &omap2_clksel_recalc,
223 .round_rate = &omap2_clksel_round_rate,
224 .set_rate = &omap2_clksel_set_rate,
225 };
226
227 static const struct clksel abe_dpll_refclk_mux_sel[] = {
228 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
229 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
230 { .parent = NULL },
231 };
232
233 static struct clk abe_dpll_refclk_mux_ck = {
234 .name = "abe_dpll_refclk_mux_ck",
235 .parent = &dpll_sys_ref_clk,
236 .clksel = abe_dpll_refclk_mux_sel,
237 .init = &omap2_init_clksel_parent,
238 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
239 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
240 .ops = &clkops_null,
241 .recalc = &omap2_clksel_recalc,
242 };
243
244 /* DPLL_ABE */
245 static struct dpll_data dpll_abe_dd = {
246 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
247 .clk_bypass = &sys_clkin_ck,
248 .clk_ref = &abe_dpll_refclk_mux_ck,
249 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
250 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
251 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
252 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_ABE,
253 .mult_mask = OMAP4430_DPLL_MULT_MASK,
254 .div1_mask = OMAP4430_DPLL_DIV_MASK,
255 .enable_mask = OMAP4430_DPLL_EN_MASK,
256 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
257 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
258 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
259 .max_divider = OMAP4430_MAX_DPLL_DIV,
260 .min_divider = 1,
261 };
262
263
264 static struct clk dpll_abe_ck = {
265 .name = "dpll_abe_ck",
266 .parent = &abe_dpll_refclk_mux_ck,
267 .dpll_data = &dpll_abe_dd,
268 .init = &omap2_init_dpll_parent,
269 .ops = &clkops_omap3_noncore_dpll_ops,
270 .recalc = &omap3_dpll_recalc,
271 .round_rate = &omap2_dpll_round_rate,
272 .set_rate = &omap3_noncore_dpll_set_rate,
273 };
274
275 static struct clk dpll_abe_m2x2_ck = {
276 .name = "dpll_abe_m2x2_ck",
277 .parent = &dpll_abe_ck,
278 .ops = &clkops_null,
279 .recalc = &followparent_recalc,
280 };
281
282 static struct clk abe_24m_fclk = {
283 .name = "abe_24m_fclk",
284 .parent = &dpll_abe_m2x2_ck,
285 .ops = &clkops_null,
286 .recalc = &followparent_recalc,
287 };
288
289 static const struct clksel_rate div3_1to4_rates[] = {
290 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
291 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
292 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
293 { .div = 0 },
294 };
295
296 static const struct clksel abe_clk_div[] = {
297 { .parent = &dpll_abe_m2x2_ck, .rates = div3_1to4_rates },
298 { .parent = NULL },
299 };
300
301 static struct clk abe_clk = {
302 .name = "abe_clk",
303 .parent = &dpll_abe_m2x2_ck,
304 .clksel = abe_clk_div,
305 .clksel_reg = OMAP4430_CM_CLKSEL_ABE,
306 .clksel_mask = OMAP4430_CLKSEL_OPP_MASK,
307 .ops = &clkops_null,
308 .recalc = &omap2_clksel_recalc,
309 .round_rate = &omap2_clksel_round_rate,
310 .set_rate = &omap2_clksel_set_rate,
311 };
312
313 static const struct clksel aess_fclk_div[] = {
314 { .parent = &abe_clk, .rates = div2_1to2_rates },
315 { .parent = NULL },
316 };
317
318 static struct clk aess_fclk = {
319 .name = "aess_fclk",
320 .parent = &abe_clk,
321 .clksel = aess_fclk_div,
322 .clksel_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
323 .clksel_mask = OMAP4430_CLKSEL_AESS_FCLK_MASK,
324 .ops = &clkops_null,
325 .recalc = &omap2_clksel_recalc,
326 .round_rate = &omap2_clksel_round_rate,
327 .set_rate = &omap2_clksel_set_rate,
328 };
329
330 static const struct clksel_rate div31_1to31_rates[] = {
331 { .div = 1, .val = 1, .flags = RATE_IN_4430 },
332 { .div = 2, .val = 2, .flags = RATE_IN_4430 },
333 { .div = 3, .val = 3, .flags = RATE_IN_4430 },
334 { .div = 4, .val = 4, .flags = RATE_IN_4430 },
335 { .div = 5, .val = 5, .flags = RATE_IN_4430 },
336 { .div = 6, .val = 6, .flags = RATE_IN_4430 },
337 { .div = 7, .val = 7, .flags = RATE_IN_4430 },
338 { .div = 8, .val = 8, .flags = RATE_IN_4430 },
339 { .div = 9, .val = 9, .flags = RATE_IN_4430 },
340 { .div = 10, .val = 10, .flags = RATE_IN_4430 },
341 { .div = 11, .val = 11, .flags = RATE_IN_4430 },
342 { .div = 12, .val = 12, .flags = RATE_IN_4430 },
343 { .div = 13, .val = 13, .flags = RATE_IN_4430 },
344 { .div = 14, .val = 14, .flags = RATE_IN_4430 },
345 { .div = 15, .val = 15, .flags = RATE_IN_4430 },
346 { .div = 16, .val = 16, .flags = RATE_IN_4430 },
347 { .div = 17, .val = 17, .flags = RATE_IN_4430 },
348 { .div = 18, .val = 18, .flags = RATE_IN_4430 },
349 { .div = 19, .val = 19, .flags = RATE_IN_4430 },
350 { .div = 20, .val = 20, .flags = RATE_IN_4430 },
351 { .div = 21, .val = 21, .flags = RATE_IN_4430 },
352 { .div = 22, .val = 22, .flags = RATE_IN_4430 },
353 { .div = 23, .val = 23, .flags = RATE_IN_4430 },
354 { .div = 24, .val = 24, .flags = RATE_IN_4430 },
355 { .div = 25, .val = 25, .flags = RATE_IN_4430 },
356 { .div = 26, .val = 26, .flags = RATE_IN_4430 },
357 { .div = 27, .val = 27, .flags = RATE_IN_4430 },
358 { .div = 28, .val = 28, .flags = RATE_IN_4430 },
359 { .div = 29, .val = 29, .flags = RATE_IN_4430 },
360 { .div = 30, .val = 30, .flags = RATE_IN_4430 },
361 { .div = 31, .val = 31, .flags = RATE_IN_4430 },
362 { .div = 0 },
363 };
364
365 static const struct clksel dpll_abe_m3_div[] = {
366 { .parent = &dpll_abe_ck, .rates = div31_1to31_rates },
367 { .parent = NULL },
368 };
369
370 static struct clk dpll_abe_m3_ck = {
371 .name = "dpll_abe_m3_ck",
372 .parent = &dpll_abe_ck,
373 .clksel = dpll_abe_m3_div,
374 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_ABE,
375 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
376 .ops = &clkops_null,
377 .recalc = &omap2_clksel_recalc,
378 .round_rate = &omap2_clksel_round_rate,
379 .set_rate = &omap2_clksel_set_rate,
380 };
381
382 static const struct clksel core_hsd_byp_clk_mux_sel[] = {
383 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
384 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
385 { .parent = NULL },
386 };
387
388 static struct clk core_hsd_byp_clk_mux_ck = {
389 .name = "core_hsd_byp_clk_mux_ck",
390 .parent = &dpll_sys_ref_clk,
391 .clksel = core_hsd_byp_clk_mux_sel,
392 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
394 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
395 .ops = &clkops_null,
396 .recalc = &omap2_clksel_recalc,
397 };
398
399 /* DPLL_CORE */
400 static struct dpll_data dpll_core_dd = {
401 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
402 .clk_bypass = &core_hsd_byp_clk_mux_ck,
403 .clk_ref = &dpll_sys_ref_clk,
404 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
406 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
407 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_CORE,
408 .mult_mask = OMAP4430_DPLL_MULT_MASK,
409 .div1_mask = OMAP4430_DPLL_DIV_MASK,
410 .enable_mask = OMAP4430_DPLL_EN_MASK,
411 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
412 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
413 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
414 .max_divider = OMAP4430_MAX_DPLL_DIV,
415 .min_divider = 1,
416 };
417
418
419 static struct clk dpll_core_ck = {
420 .name = "dpll_core_ck",
421 .parent = &dpll_sys_ref_clk,
422 .dpll_data = &dpll_core_dd,
423 .init = &omap2_init_dpll_parent,
424 .ops = &clkops_null,
425 .recalc = &omap3_dpll_recalc,
426 };
427
428 static const struct clksel dpll_core_m6_div[] = {
429 { .parent = &dpll_core_ck, .rates = div31_1to31_rates },
430 { .parent = NULL },
431 };
432
433 static struct clk dpll_core_m6_ck = {
434 .name = "dpll_core_m6_ck",
435 .parent = &dpll_core_ck,
436 .clksel = dpll_core_m6_div,
437 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_CORE,
438 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
439 .ops = &clkops_null,
440 .recalc = &omap2_clksel_recalc,
441 .round_rate = &omap2_clksel_round_rate,
442 .set_rate = &omap2_clksel_set_rate,
443 };
444
445 static const struct clksel dbgclk_mux_sel[] = {
446 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
447 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
448 { .parent = NULL },
449 };
450
451 static struct clk dbgclk_mux_ck = {
452 .name = "dbgclk_mux_ck",
453 .parent = &sys_clkin_ck,
454 .ops = &clkops_null,
455 .recalc = &followparent_recalc,
456 };
457
458 static struct clk dpll_core_m2_ck = {
459 .name = "dpll_core_m2_ck",
460 .parent = &dpll_core_ck,
461 .clksel = dpll_core_m6_div,
462 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_CORE,
463 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
464 .ops = &clkops_null,
465 .recalc = &omap2_clksel_recalc,
466 .round_rate = &omap2_clksel_round_rate,
467 .set_rate = &omap2_clksel_set_rate,
468 };
469
470 static struct clk ddrphy_ck = {
471 .name = "ddrphy_ck",
472 .parent = &dpll_core_m2_ck,
473 .ops = &clkops_null,
474 .recalc = &followparent_recalc,
475 };
476
477 static struct clk dpll_core_m5_ck = {
478 .name = "dpll_core_m5_ck",
479 .parent = &dpll_core_ck,
480 .clksel = dpll_core_m6_div,
481 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_CORE,
482 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
483 .ops = &clkops_null,
484 .recalc = &omap2_clksel_recalc,
485 .round_rate = &omap2_clksel_round_rate,
486 .set_rate = &omap2_clksel_set_rate,
487 };
488
489 static const struct clksel div_core_div[] = {
490 { .parent = &dpll_core_m5_ck, .rates = div2_1to2_rates },
491 { .parent = NULL },
492 };
493
494 static struct clk div_core_ck = {
495 .name = "div_core_ck",
496 .parent = &dpll_core_m5_ck,
497 .clksel = div_core_div,
498 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
499 .clksel_mask = OMAP4430_CLKSEL_CORE_MASK,
500 .ops = &clkops_null,
501 .recalc = &omap2_clksel_recalc,
502 .round_rate = &omap2_clksel_round_rate,
503 .set_rate = &omap2_clksel_set_rate,
504 };
505
506 static const struct clksel_rate div4_1to8_rates[] = {
507 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
508 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
509 { .div = 4, .val = 2, .flags = RATE_IN_4430 },
510 { .div = 8, .val = 3, .flags = RATE_IN_4430 },
511 { .div = 0 },
512 };
513
514 static const struct clksel div_iva_hs_clk_div[] = {
515 { .parent = &dpll_core_m5_ck, .rates = div4_1to8_rates },
516 { .parent = NULL },
517 };
518
519 static struct clk div_iva_hs_clk = {
520 .name = "div_iva_hs_clk",
521 .parent = &dpll_core_m5_ck,
522 .clksel = div_iva_hs_clk_div,
523 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_IVA,
524 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
525 .ops = &clkops_null,
526 .recalc = &omap2_clksel_recalc,
527 .round_rate = &omap2_clksel_round_rate,
528 .set_rate = &omap2_clksel_set_rate,
529 };
530
531 static struct clk div_mpu_hs_clk = {
532 .name = "div_mpu_hs_clk",
533 .parent = &dpll_core_m5_ck,
534 .clksel = div_iva_hs_clk_div,
535 .clksel_reg = OMAP4430_CM_BYPCLK_DPLL_MPU,
536 .clksel_mask = OMAP4430_CLKSEL_0_1_MASK,
537 .ops = &clkops_null,
538 .recalc = &omap2_clksel_recalc,
539 .round_rate = &omap2_clksel_round_rate,
540 .set_rate = &omap2_clksel_set_rate,
541 };
542
543 static struct clk dpll_core_m4_ck = {
544 .name = "dpll_core_m4_ck",
545 .parent = &dpll_core_ck,
546 .clksel = dpll_core_m6_div,
547 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_CORE,
548 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
549 .ops = &clkops_null,
550 .recalc = &omap2_clksel_recalc,
551 .round_rate = &omap2_clksel_round_rate,
552 .set_rate = &omap2_clksel_set_rate,
553 };
554
555 static struct clk dll_clk_div_ck = {
556 .name = "dll_clk_div_ck",
557 .parent = &dpll_core_m4_ck,
558 .ops = &clkops_null,
559 .recalc = &followparent_recalc,
560 };
561
562 static struct clk dpll_abe_m2_ck = {
563 .name = "dpll_abe_m2_ck",
564 .parent = &dpll_abe_ck,
565 .clksel = dpll_abe_m3_div,
566 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
567 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
568 .ops = &clkops_null,
569 .recalc = &omap2_clksel_recalc,
570 .round_rate = &omap2_clksel_round_rate,
571 .set_rate = &omap2_clksel_set_rate,
572 };
573
574 static struct clk dpll_core_m3_ck = {
575 .name = "dpll_core_m3_ck",
576 .parent = &dpll_core_ck,
577 .clksel = dpll_core_m6_div,
578 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
579 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
580 .ops = &clkops_null,
581 .recalc = &omap2_clksel_recalc,
582 .round_rate = &omap2_clksel_round_rate,
583 .set_rate = &omap2_clksel_set_rate,
584 };
585
586 static struct clk dpll_core_m7_ck = {
587 .name = "dpll_core_m7_ck",
588 .parent = &dpll_core_ck,
589 .clksel = dpll_core_m6_div,
590 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_CORE,
591 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
592 .ops = &clkops_null,
593 .recalc = &omap2_clksel_recalc,
594 .round_rate = &omap2_clksel_round_rate,
595 .set_rate = &omap2_clksel_set_rate,
596 };
597
598 static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
599 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
600 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
601 { .parent = NULL },
602 };
603
604 static struct clk iva_hsd_byp_clk_mux_ck = {
605 .name = "iva_hsd_byp_clk_mux_ck",
606 .parent = &dpll_sys_ref_clk,
607 .ops = &clkops_null,
608 .recalc = &followparent_recalc,
609 };
610
611 /* DPLL_IVA */
612 static struct dpll_data dpll_iva_dd = {
613 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
614 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
615 .clk_ref = &dpll_sys_ref_clk,
616 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
617 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
619 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_IVA,
620 .mult_mask = OMAP4430_DPLL_MULT_MASK,
621 .div1_mask = OMAP4430_DPLL_DIV_MASK,
622 .enable_mask = OMAP4430_DPLL_EN_MASK,
623 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
624 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
625 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
626 .max_divider = OMAP4430_MAX_DPLL_DIV,
627 .min_divider = 1,
628 };
629
630
631 static struct clk dpll_iva_ck = {
632 .name = "dpll_iva_ck",
633 .parent = &dpll_sys_ref_clk,
634 .dpll_data = &dpll_iva_dd,
635 .init = &omap2_init_dpll_parent,
636 .ops = &clkops_omap3_noncore_dpll_ops,
637 .recalc = &omap3_dpll_recalc,
638 .round_rate = &omap2_dpll_round_rate,
639 .set_rate = &omap3_noncore_dpll_set_rate,
640 };
641
642 static const struct clksel dpll_iva_m4_div[] = {
643 { .parent = &dpll_iva_ck, .rates = div31_1to31_rates },
644 { .parent = NULL },
645 };
646
647 static struct clk dpll_iva_m4_ck = {
648 .name = "dpll_iva_m4_ck",
649 .parent = &dpll_iva_ck,
650 .clksel = dpll_iva_m4_div,
651 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_IVA,
652 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
653 .ops = &clkops_null,
654 .recalc = &omap2_clksel_recalc,
655 .round_rate = &omap2_clksel_round_rate,
656 .set_rate = &omap2_clksel_set_rate,
657 };
658
659 static struct clk dpll_iva_m5_ck = {
660 .name = "dpll_iva_m5_ck",
661 .parent = &dpll_iva_ck,
662 .clksel = dpll_iva_m4_div,
663 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_IVA,
664 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
665 .ops = &clkops_null,
666 .recalc = &omap2_clksel_recalc,
667 .round_rate = &omap2_clksel_round_rate,
668 .set_rate = &omap2_clksel_set_rate,
669 };
670
671 /* DPLL_MPU */
672 static struct dpll_data dpll_mpu_dd = {
673 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
674 .clk_bypass = &div_mpu_hs_clk,
675 .clk_ref = &dpll_sys_ref_clk,
676 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
677 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
678 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
679 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_MPU,
680 .mult_mask = OMAP4430_DPLL_MULT_MASK,
681 .div1_mask = OMAP4430_DPLL_DIV_MASK,
682 .enable_mask = OMAP4430_DPLL_EN_MASK,
683 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
684 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
685 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
686 .max_divider = OMAP4430_MAX_DPLL_DIV,
687 .min_divider = 1,
688 };
689
690
691 static struct clk dpll_mpu_ck = {
692 .name = "dpll_mpu_ck",
693 .parent = &dpll_sys_ref_clk,
694 .dpll_data = &dpll_mpu_dd,
695 .init = &omap2_init_dpll_parent,
696 .ops = &clkops_omap3_noncore_dpll_ops,
697 .recalc = &omap3_dpll_recalc,
698 .round_rate = &omap2_dpll_round_rate,
699 .set_rate = &omap3_noncore_dpll_set_rate,
700 };
701
702 static const struct clksel dpll_mpu_m2_div[] = {
703 { .parent = &dpll_mpu_ck, .rates = div31_1to31_rates },
704 { .parent = NULL },
705 };
706
707 static struct clk dpll_mpu_m2_ck = {
708 .name = "dpll_mpu_m2_ck",
709 .parent = &dpll_mpu_ck,
710 .clksel = dpll_mpu_m2_div,
711 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_MPU,
712 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
713 .ops = &clkops_null,
714 .recalc = &omap2_clksel_recalc,
715 .round_rate = &omap2_clksel_round_rate,
716 .set_rate = &omap2_clksel_set_rate,
717 };
718
719 static struct clk per_hs_clk_div_ck = {
720 .name = "per_hs_clk_div_ck",
721 .parent = &dpll_abe_m3_ck,
722 .ops = &clkops_null,
723 .recalc = &followparent_recalc,
724 };
725
726 static const struct clksel per_hsd_byp_clk_mux_sel[] = {
727 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
728 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
729 { .parent = NULL },
730 };
731
732 static struct clk per_hsd_byp_clk_mux_ck = {
733 .name = "per_hsd_byp_clk_mux_ck",
734 .parent = &dpll_sys_ref_clk,
735 .clksel = per_hsd_byp_clk_mux_sel,
736 .init = &omap2_init_clksel_parent,
737 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
738 .clksel_mask = OMAP4430_DPLL_BYP_CLKSEL_MASK,
739 .ops = &clkops_null,
740 .recalc = &omap2_clksel_recalc,
741 };
742
743 /* DPLL_PER */
744 static struct dpll_data dpll_per_dd = {
745 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
746 .clk_bypass = &per_hsd_byp_clk_mux_ck,
747 .clk_ref = &dpll_sys_ref_clk,
748 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
749 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
750 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
751 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_PER,
752 .mult_mask = OMAP4430_DPLL_MULT_MASK,
753 .div1_mask = OMAP4430_DPLL_DIV_MASK,
754 .enable_mask = OMAP4430_DPLL_EN_MASK,
755 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
756 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
757 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
758 .max_divider = OMAP4430_MAX_DPLL_DIV,
759 .min_divider = 1,
760 };
761
762
763 static struct clk dpll_per_ck = {
764 .name = "dpll_per_ck",
765 .parent = &dpll_sys_ref_clk,
766 .dpll_data = &dpll_per_dd,
767 .init = &omap2_init_dpll_parent,
768 .ops = &clkops_omap3_noncore_dpll_ops,
769 .recalc = &omap3_dpll_recalc,
770 .round_rate = &omap2_dpll_round_rate,
771 .set_rate = &omap3_noncore_dpll_set_rate,
772 };
773
774 static const struct clksel dpll_per_m2_div[] = {
775 { .parent = &dpll_per_ck, .rates = div31_1to31_rates },
776 { .parent = NULL },
777 };
778
779 static struct clk dpll_per_m2_ck = {
780 .name = "dpll_per_m2_ck",
781 .parent = &dpll_per_ck,
782 .clksel = dpll_per_m2_div,
783 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
784 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
785 .ops = &clkops_null,
786 .recalc = &omap2_clksel_recalc,
787 .round_rate = &omap2_clksel_round_rate,
788 .set_rate = &omap2_clksel_set_rate,
789 };
790
791 static struct clk dpll_per_m2x2_ck = {
792 .name = "dpll_per_m2x2_ck",
793 .parent = &dpll_per_ck,
794 .ops = &clkops_null,
795 .recalc = &followparent_recalc,
796 };
797
798 static struct clk dpll_per_m3_ck = {
799 .name = "dpll_per_m3_ck",
800 .parent = &dpll_per_ck,
801 .clksel = dpll_per_m2_div,
802 .clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
803 .clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
804 .ops = &clkops_null,
805 .recalc = &omap2_clksel_recalc,
806 .round_rate = &omap2_clksel_round_rate,
807 .set_rate = &omap2_clksel_set_rate,
808 };
809
810 static struct clk dpll_per_m4_ck = {
811 .name = "dpll_per_m4_ck",
812 .parent = &dpll_per_ck,
813 .clksel = dpll_per_m2_div,
814 .clksel_reg = OMAP4430_CM_DIV_M4_DPLL_PER,
815 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
816 .ops = &clkops_null,
817 .recalc = &omap2_clksel_recalc,
818 .round_rate = &omap2_clksel_round_rate,
819 .set_rate = &omap2_clksel_set_rate,
820 };
821
822 static struct clk dpll_per_m5_ck = {
823 .name = "dpll_per_m5_ck",
824 .parent = &dpll_per_ck,
825 .clksel = dpll_per_m2_div,
826 .clksel_reg = OMAP4430_CM_DIV_M5_DPLL_PER,
827 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
828 .ops = &clkops_null,
829 .recalc = &omap2_clksel_recalc,
830 .round_rate = &omap2_clksel_round_rate,
831 .set_rate = &omap2_clksel_set_rate,
832 };
833
834 static struct clk dpll_per_m6_ck = {
835 .name = "dpll_per_m6_ck",
836 .parent = &dpll_per_ck,
837 .clksel = dpll_per_m2_div,
838 .clksel_reg = OMAP4430_CM_DIV_M6_DPLL_PER,
839 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
840 .ops = &clkops_null,
841 .recalc = &omap2_clksel_recalc,
842 .round_rate = &omap2_clksel_round_rate,
843 .set_rate = &omap2_clksel_set_rate,
844 };
845
846 static struct clk dpll_per_m7_ck = {
847 .name = "dpll_per_m7_ck",
848 .parent = &dpll_per_ck,
849 .clksel = dpll_per_m2_div,
850 .clksel_reg = OMAP4430_CM_DIV_M7_DPLL_PER,
851 .clksel_mask = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
852 .ops = &clkops_null,
853 .recalc = &omap2_clksel_recalc,
854 .round_rate = &omap2_clksel_round_rate,
855 .set_rate = &omap2_clksel_set_rate,
856 };
857
858 /* DPLL_UNIPRO */
859 static struct dpll_data dpll_unipro_dd = {
860 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
861 .clk_bypass = &dpll_sys_ref_clk,
862 .clk_ref = &dpll_sys_ref_clk,
863 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
864 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
865 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
866 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
867 .mult_mask = OMAP4430_DPLL_MULT_MASK,
868 .div1_mask = OMAP4430_DPLL_DIV_MASK,
869 .enable_mask = OMAP4430_DPLL_EN_MASK,
870 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
871 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
872 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
873 .max_divider = OMAP4430_MAX_DPLL_DIV,
874 .min_divider = 1,
875 };
876
877
878 static struct clk dpll_unipro_ck = {
879 .name = "dpll_unipro_ck",
880 .parent = &dpll_sys_ref_clk,
881 .dpll_data = &dpll_unipro_dd,
882 .init = &omap2_init_dpll_parent,
883 .ops = &clkops_omap3_noncore_dpll_ops,
884 .recalc = &omap3_dpll_recalc,
885 .round_rate = &omap2_dpll_round_rate,
886 .set_rate = &omap3_noncore_dpll_set_rate,
887 };
888
889 static const struct clksel dpll_unipro_m2x2_div[] = {
890 { .parent = &dpll_unipro_ck, .rates = div31_1to31_rates },
891 { .parent = NULL },
892 };
893
894 static struct clk dpll_unipro_m2x2_ck = {
895 .name = "dpll_unipro_m2x2_ck",
896 .parent = &dpll_unipro_ck,
897 .clksel = dpll_unipro_m2x2_div,
898 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
899 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
900 .ops = &clkops_null,
901 .recalc = &omap2_clksel_recalc,
902 .round_rate = &omap2_clksel_round_rate,
903 .set_rate = &omap2_clksel_set_rate,
904 };
905
906 static struct clk usb_hs_clk_div_ck = {
907 .name = "usb_hs_clk_div_ck",
908 .parent = &dpll_abe_m3_ck,
909 .ops = &clkops_null,
910 .recalc = &followparent_recalc,
911 };
912
913 /* DPLL_USB */
914 static struct dpll_data dpll_usb_dd = {
915 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
916 .clk_bypass = &usb_hs_clk_div_ck,
917 .clk_ref = &dpll_sys_ref_clk,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
921 .idlest_reg = OMAP4430_CM_IDLEST_DPLL_USB,
922 .mult_mask = OMAP4430_DPLL_MULT_MASK,
923 .div1_mask = OMAP4430_DPLL_DIV_MASK,
924 .enable_mask = OMAP4430_DPLL_EN_MASK,
925 .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
926 .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1,
930 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
931 };
932
933
934 static struct clk dpll_usb_ck = {
935 .name = "dpll_usb_ck",
936 .parent = &dpll_sys_ref_clk,
937 .dpll_data = &dpll_usb_dd,
938 .init = &omap2_init_dpll_parent,
939 .ops = &clkops_omap3_noncore_dpll_ops,
940 .recalc = &omap3_dpll_recalc,
941 .round_rate = &omap2_dpll_round_rate,
942 .set_rate = &omap3_noncore_dpll_set_rate,
943 };
944
945 static struct clk dpll_usb_clkdcoldo_ck = {
946 .name = "dpll_usb_clkdcoldo_ck",
947 .parent = &dpll_usb_ck,
948 .ops = &clkops_null,
949 .recalc = &followparent_recalc,
950 };
951
952 static const struct clksel dpll_usb_m2_div[] = {
953 { .parent = &dpll_usb_ck, .rates = div31_1to31_rates },
954 { .parent = NULL },
955 };
956
957 static struct clk dpll_usb_m2_ck = {
958 .name = "dpll_usb_m2_ck",
959 .parent = &dpll_usb_ck,
960 .clksel = dpll_usb_m2_div,
961 .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_USB,
962 .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
963 .ops = &clkops_null,
964 .recalc = &omap2_clksel_recalc,
965 .round_rate = &omap2_clksel_round_rate,
966 .set_rate = &omap2_clksel_set_rate,
967 };
968
969 static const struct clksel ducati_clk_mux_sel[] = {
970 { .parent = &div_core_ck, .rates = div_1_0_rates },
971 { .parent = &dpll_per_m6_ck, .rates = div_1_1_rates },
972 { .parent = NULL },
973 };
974
975 static struct clk ducati_clk_mux_ck = {
976 .name = "ducati_clk_mux_ck",
977 .parent = &div_core_ck,
978 .clksel = ducati_clk_mux_sel,
979 .init = &omap2_init_clksel_parent,
980 .clksel_reg = OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT,
981 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
982 .ops = &clkops_null,
983 .recalc = &omap2_clksel_recalc,
984 };
985
986 static struct clk func_12m_fclk = {
987 .name = "func_12m_fclk",
988 .parent = &dpll_per_m2x2_ck,
989 .ops = &clkops_null,
990 .recalc = &followparent_recalc,
991 };
992
993 static struct clk func_24m_clk = {
994 .name = "func_24m_clk",
995 .parent = &dpll_per_m2_ck,
996 .ops = &clkops_null,
997 .recalc = &followparent_recalc,
998 };
999
1000 static struct clk func_24mc_fclk = {
1001 .name = "func_24mc_fclk",
1002 .parent = &dpll_per_m2x2_ck,
1003 .ops = &clkops_null,
1004 .recalc = &followparent_recalc,
1005 };
1006
1007 static const struct clksel_rate div2_4to8_rates[] = {
1008 { .div = 4, .val = 0, .flags = RATE_IN_4430 },
1009 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1010 { .div = 0 },
1011 };
1012
1013 static const struct clksel func_48m_fclk_div[] = {
1014 { .parent = &dpll_per_m2x2_ck, .rates = div2_4to8_rates },
1015 { .parent = NULL },
1016 };
1017
1018 static struct clk func_48m_fclk = {
1019 .name = "func_48m_fclk",
1020 .parent = &dpll_per_m2x2_ck,
1021 .clksel = func_48m_fclk_div,
1022 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1023 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1024 .ops = &clkops_null,
1025 .recalc = &omap2_clksel_recalc,
1026 .round_rate = &omap2_clksel_round_rate,
1027 .set_rate = &omap2_clksel_set_rate,
1028 };
1029
1030 static struct clk func_48mc_fclk = {
1031 .name = "func_48mc_fclk",
1032 .parent = &dpll_per_m2x2_ck,
1033 .ops = &clkops_null,
1034 .recalc = &followparent_recalc,
1035 };
1036
1037 static const struct clksel_rate div2_2to4_rates[] = {
1038 { .div = 2, .val = 0, .flags = RATE_IN_4430 },
1039 { .div = 4, .val = 1, .flags = RATE_IN_4430 },
1040 { .div = 0 },
1041 };
1042
1043 static const struct clksel func_64m_fclk_div[] = {
1044 { .parent = &dpll_per_m4_ck, .rates = div2_2to4_rates },
1045 { .parent = NULL },
1046 };
1047
1048 static struct clk func_64m_fclk = {
1049 .name = "func_64m_fclk",
1050 .parent = &dpll_per_m4_ck,
1051 .clksel = func_64m_fclk_div,
1052 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1053 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1054 .ops = &clkops_null,
1055 .recalc = &omap2_clksel_recalc,
1056 .round_rate = &omap2_clksel_round_rate,
1057 .set_rate = &omap2_clksel_set_rate,
1058 };
1059
1060 static const struct clksel func_96m_fclk_div[] = {
1061 { .parent = &dpll_per_m2x2_ck, .rates = div2_2to4_rates },
1062 { .parent = NULL },
1063 };
1064
1065 static struct clk func_96m_fclk = {
1066 .name = "func_96m_fclk",
1067 .parent = &dpll_per_m2x2_ck,
1068 .clksel = func_96m_fclk_div,
1069 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1070 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1071 .ops = &clkops_null,
1072 .recalc = &omap2_clksel_recalc,
1073 .round_rate = &omap2_clksel_round_rate,
1074 .set_rate = &omap2_clksel_set_rate,
1075 };
1076
1077 static const struct clksel hsmmc6_fclk_sel[] = {
1078 { .parent = &func_64m_fclk, .rates = div_1_0_rates },
1079 { .parent = &func_96m_fclk, .rates = div_1_1_rates },
1080 { .parent = NULL },
1081 };
1082
1083 static struct clk hsmmc6_fclk = {
1084 .name = "hsmmc6_fclk",
1085 .parent = &func_64m_fclk,
1086 .ops = &clkops_null,
1087 .recalc = &followparent_recalc,
1088 };
1089
1090 static const struct clksel_rate div2_1to8_rates[] = {
1091 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
1092 { .div = 8, .val = 1, .flags = RATE_IN_4430 },
1093 { .div = 0 },
1094 };
1095
1096 static const struct clksel init_60m_fclk_div[] = {
1097 { .parent = &dpll_usb_m2_ck, .rates = div2_1to8_rates },
1098 { .parent = NULL },
1099 };
1100
1101 static struct clk init_60m_fclk = {
1102 .name = "init_60m_fclk",
1103 .parent = &dpll_usb_m2_ck,
1104 .clksel = init_60m_fclk_div,
1105 .clksel_reg = OMAP4430_CM_CLKSEL_USB_60MHZ,
1106 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1107 .ops = &clkops_null,
1108 .recalc = &omap2_clksel_recalc,
1109 .round_rate = &omap2_clksel_round_rate,
1110 .set_rate = &omap2_clksel_set_rate,
1111 };
1112
1113 static const struct clksel l3_div_div[] = {
1114 { .parent = &div_core_ck, .rates = div2_1to2_rates },
1115 { .parent = NULL },
1116 };
1117
1118 static struct clk l3_div_ck = {
1119 .name = "l3_div_ck",
1120 .parent = &div_core_ck,
1121 .clksel = l3_div_div,
1122 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1123 .clksel_mask = OMAP4430_CLKSEL_L3_MASK,
1124 .ops = &clkops_null,
1125 .recalc = &omap2_clksel_recalc,
1126 .round_rate = &omap2_clksel_round_rate,
1127 .set_rate = &omap2_clksel_set_rate,
1128 };
1129
1130 static const struct clksel l4_div_div[] = {
1131 { .parent = &l3_div_ck, .rates = div2_1to2_rates },
1132 { .parent = NULL },
1133 };
1134
1135 static struct clk l4_div_ck = {
1136 .name = "l4_div_ck",
1137 .parent = &l3_div_ck,
1138 .clksel = l4_div_div,
1139 .clksel_reg = OMAP4430_CM_CLKSEL_CORE,
1140 .clksel_mask = OMAP4430_CLKSEL_L4_MASK,
1141 .ops = &clkops_null,
1142 .recalc = &omap2_clksel_recalc,
1143 .round_rate = &omap2_clksel_round_rate,
1144 .set_rate = &omap2_clksel_set_rate,
1145 };
1146
1147 static struct clk lp_clk_div_ck = {
1148 .name = "lp_clk_div_ck",
1149 .parent = &dpll_abe_m2x2_ck,
1150 .ops = &clkops_null,
1151 .recalc = &followparent_recalc,
1152 };
1153
1154 static const struct clksel l4_wkup_clk_mux_sel[] = {
1155 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1156 { .parent = &lp_clk_div_ck, .rates = div_1_1_rates },
1157 { .parent = NULL },
1158 };
1159
1160 static struct clk l4_wkup_clk_mux_ck = {
1161 .name = "l4_wkup_clk_mux_ck",
1162 .parent = &sys_clkin_ck,
1163 .clksel = l4_wkup_clk_mux_sel,
1164 .init = &omap2_init_clksel_parent,
1165 .clksel_reg = OMAP4430_CM_L4_WKUP_CLKSEL,
1166 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1167 .ops = &clkops_null,
1168 .recalc = &omap2_clksel_recalc,
1169 };
1170
1171 static const struct clksel per_abe_nc_fclk_div[] = {
1172 { .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
1173 { .parent = NULL },
1174 };
1175
1176 static struct clk per_abe_nc_fclk = {
1177 .name = "per_abe_nc_fclk",
1178 .parent = &dpll_abe_m2_ck,
1179 .clksel = per_abe_nc_fclk_div,
1180 .clksel_reg = OMAP4430_CM_SCALE_FCLK,
1181 .clksel_mask = OMAP4430_SCALE_FCLK_MASK,
1182 .ops = &clkops_null,
1183 .recalc = &omap2_clksel_recalc,
1184 .round_rate = &omap2_clksel_round_rate,
1185 .set_rate = &omap2_clksel_set_rate,
1186 };
1187
1188 static const struct clksel mcasp2_fclk_sel[] = {
1189 { .parent = &func_96m_fclk, .rates = div_1_0_rates },
1190 { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
1191 { .parent = NULL },
1192 };
1193
1194 static struct clk mcasp2_fclk = {
1195 .name = "mcasp2_fclk",
1196 .parent = &func_96m_fclk,
1197 .ops = &clkops_null,
1198 .recalc = &followparent_recalc,
1199 };
1200
1201 static struct clk mcasp3_fclk = {
1202 .name = "mcasp3_fclk",
1203 .parent = &func_96m_fclk,
1204 .ops = &clkops_null,
1205 .recalc = &followparent_recalc,
1206 };
1207
1208 static struct clk ocp_abe_iclk = {
1209 .name = "ocp_abe_iclk",
1210 .parent = &aess_fclk,
1211 .ops = &clkops_null,
1212 .recalc = &followparent_recalc,
1213 };
1214
1215 static struct clk per_abe_24m_fclk = {
1216 .name = "per_abe_24m_fclk",
1217 .parent = &dpll_abe_m2_ck,
1218 .ops = &clkops_null,
1219 .recalc = &followparent_recalc,
1220 };
1221
1222 static const struct clksel pmd_stm_clock_mux_sel[] = {
1223 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1224 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1225 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates },
1226 { .parent = NULL },
1227 };
1228
1229 static struct clk pmd_stm_clock_mux_ck = {
1230 .name = "pmd_stm_clock_mux_ck",
1231 .parent = &sys_clkin_ck,
1232 .ops = &clkops_null,
1233 .recalc = &followparent_recalc,
1234 };
1235
1236 static struct clk pmd_trace_clk_mux_ck = {
1237 .name = "pmd_trace_clk_mux_ck",
1238 .parent = &sys_clkin_ck,
1239 .ops = &clkops_null,
1240 .recalc = &followparent_recalc,
1241 };
1242
1243 static struct clk syc_clk_div_ck = {
1244 .name = "syc_clk_div_ck",
1245 .parent = &sys_clkin_ck,
1246 .clksel = dpll_sys_ref_clk_div,
1247 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1248 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1249 .ops = &clkops_null,
1250 .recalc = &omap2_clksel_recalc,
1251 .round_rate = &omap2_clksel_round_rate,
1252 .set_rate = &omap2_clksel_set_rate,
1253 };
1254
1255 /* Leaf clocks controlled by modules */
1256
1257 static struct clk aes1_fck = {
1258 .name = "aes1_fck",
1259 .ops = &clkops_omap2_dflt,
1260 .enable_reg = OMAP4430_CM_L4SEC_AES1_CLKCTRL,
1261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1262 .clkdm_name = "l4_secure_clkdm",
1263 .parent = &l3_div_ck,
1264 .recalc = &followparent_recalc,
1265 };
1266
1267 static struct clk aes2_fck = {
1268 .name = "aes2_fck",
1269 .ops = &clkops_omap2_dflt,
1270 .enable_reg = OMAP4430_CM_L4SEC_AES2_CLKCTRL,
1271 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1272 .clkdm_name = "l4_secure_clkdm",
1273 .parent = &l3_div_ck,
1274 .recalc = &followparent_recalc,
1275 };
1276
1277 static struct clk aess_fck = {
1278 .name = "aess_fck",
1279 .ops = &clkops_omap2_dflt,
1280 .enable_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
1281 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1282 .clkdm_name = "abe_clkdm",
1283 .parent = &aess_fclk,
1284 .recalc = &followparent_recalc,
1285 };
1286
1287 static struct clk cust_efuse_fck = {
1288 .name = "cust_efuse_fck",
1289 .ops = &clkops_omap2_dflt,
1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1292 .clkdm_name = "l4_cefuse_clkdm",
1293 .parent = &sys_clkin_ck,
1294 .recalc = &followparent_recalc,
1295 };
1296
1297 static struct clk des3des_fck = {
1298 .name = "des3des_fck",
1299 .ops = &clkops_omap2_dflt,
1300 .enable_reg = OMAP4430_CM_L4SEC_DES3DES_CLKCTRL,
1301 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1302 .clkdm_name = "l4_secure_clkdm",
1303 .parent = &l4_div_ck,
1304 .recalc = &followparent_recalc,
1305 };
1306
1307 static const struct clksel dmic_sync_mux_sel[] = {
1308 { .parent = &abe_24m_fclk, .rates = div_1_0_rates },
1309 { .parent = &syc_clk_div_ck, .rates = div_1_1_rates },
1310 { .parent = &func_24m_clk, .rates = div_1_2_rates },
1311 { .parent = NULL },
1312 };
1313
1314 static struct clk dmic_sync_mux_ck = {
1315 .name = "dmic_sync_mux_ck",
1316 .parent = &abe_24m_fclk,
1317 .clksel = dmic_sync_mux_sel,
1318 .init = &omap2_init_clksel_parent,
1319 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1320 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1321 .ops = &clkops_null,
1322 .recalc = &omap2_clksel_recalc,
1323 };
1324
1325 static const struct clksel func_dmic_abe_gfclk_sel[] = {
1326 { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
1327 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1328 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1329 { .parent = NULL },
1330 };
1331
1332 /* Merged func_dmic_abe_gfclk into dmic */
1333 static struct clk dmic_fck = {
1334 .name = "dmic_fck",
1335 .parent = &dmic_sync_mux_ck,
1336 .clksel = func_dmic_abe_gfclk_sel,
1337 .init = &omap2_init_clksel_parent,
1338 .clksel_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1339 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1340 .ops = &clkops_omap2_dflt,
1341 .recalc = &omap2_clksel_recalc,
1342 .enable_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
1343 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1344 .clkdm_name = "abe_clkdm",
1345 };
1346
1347 static struct clk dss_fck = {
1348 .name = "dss_fck",
1349 .ops = &clkops_omap2_dflt,
1350 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1351 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1352 .clkdm_name = "l3_dss_clkdm",
1353 .parent = &l3_div_ck,
1354 .recalc = &followparent_recalc,
1355 };
1356
1357 static struct clk ducati_ick = {
1358 .name = "ducati_ick",
1359 .ops = &clkops_omap2_dflt,
1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1362 .clkdm_name = "ducati_clkdm",
1363 .parent = &ducati_clk_mux_ck,
1364 .recalc = &followparent_recalc,
1365 };
1366
1367 static struct clk emif1_ick = {
1368 .name = "emif1_ick",
1369 .ops = &clkops_omap2_dflt,
1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1372 .flags = ENABLE_ON_INIT,
1373 .clkdm_name = "l3_emif_clkdm",
1374 .parent = &ddrphy_ck,
1375 .recalc = &followparent_recalc,
1376 };
1377
1378 static struct clk emif2_ick = {
1379 .name = "emif2_ick",
1380 .ops = &clkops_omap2_dflt,
1381 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1382 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1383 .flags = ENABLE_ON_INIT,
1384 .clkdm_name = "l3_emif_clkdm",
1385 .parent = &ddrphy_ck,
1386 .recalc = &followparent_recalc,
1387 };
1388
1389 static const struct clksel fdif_fclk_div[] = {
1390 { .parent = &dpll_per_m4_ck, .rates = div3_1to4_rates },
1391 { .parent = NULL },
1392 };
1393
1394 /* Merged fdif_fclk into fdif */
1395 static struct clk fdif_fck = {
1396 .name = "fdif_fck",
1397 .parent = &dpll_per_m4_ck,
1398 .clksel = fdif_fclk_div,
1399 .clksel_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1400 .clksel_mask = OMAP4430_CLKSEL_FCLK_MASK,
1401 .ops = &clkops_omap2_dflt,
1402 .recalc = &omap2_clksel_recalc,
1403 .round_rate = &omap2_clksel_round_rate,
1404 .set_rate = &omap2_clksel_set_rate,
1405 .enable_reg = OMAP4430_CM_CAM_FDIF_CLKCTRL,
1406 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1407 .clkdm_name = "iss_clkdm",
1408 };
1409
1410 static const struct clksel per_sgx_fclk_div[] = {
1411 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1412 { .parent = NULL },
1413 };
1414
1415 static struct clk per_sgx_fclk = {
1416 .name = "per_sgx_fclk",
1417 .parent = &dpll_per_m2x2_ck,
1418 .clksel = per_sgx_fclk_div,
1419 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1420 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1421 .ops = &clkops_null,
1422 .recalc = &omap2_clksel_recalc,
1423 .round_rate = &omap2_clksel_round_rate,
1424 .set_rate = &omap2_clksel_set_rate,
1425 };
1426
1427 static const struct clksel sgx_clk_mux_sel[] = {
1428 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1429 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1430 { .parent = NULL },
1431 };
1432
1433 /* Merged sgx_clk_mux into gfx */
1434 static struct clk gfx_fck = {
1435 .name = "gfx_fck",
1436 .parent = &dpll_core_m7_ck,
1437 .clksel = sgx_clk_mux_sel,
1438 .init = &omap2_init_clksel_parent,
1439 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1440 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1441 .ops = &clkops_omap2_dflt,
1442 .recalc = &omap2_clksel_recalc,
1443 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1444 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1445 .clkdm_name = "l3_gfx_clkdm",
1446 };
1447
1448 static struct clk gpio1_ick = {
1449 .name = "gpio1_ick",
1450 .ops = &clkops_omap2_dflt,
1451 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1452 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1453 .clkdm_name = "l4_wkup_clkdm",
1454 .parent = &l4_wkup_clk_mux_ck,
1455 .recalc = &followparent_recalc,
1456 };
1457
1458 static struct clk gpio2_ick = {
1459 .name = "gpio2_ick",
1460 .ops = &clkops_omap2_dflt,
1461 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1462 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1463 .clkdm_name = "l4_per_clkdm",
1464 .parent = &l4_div_ck,
1465 .recalc = &followparent_recalc,
1466 };
1467
1468 static struct clk gpio3_ick = {
1469 .name = "gpio3_ick",
1470 .ops = &clkops_omap2_dflt,
1471 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1472 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1473 .clkdm_name = "l4_per_clkdm",
1474 .parent = &l4_div_ck,
1475 .recalc = &followparent_recalc,
1476 };
1477
1478 static struct clk gpio4_ick = {
1479 .name = "gpio4_ick",
1480 .ops = &clkops_omap2_dflt,
1481 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1482 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1483 .clkdm_name = "l4_per_clkdm",
1484 .parent = &l4_div_ck,
1485 .recalc = &followparent_recalc,
1486 };
1487
1488 static struct clk gpio5_ick = {
1489 .name = "gpio5_ick",
1490 .ops = &clkops_omap2_dflt,
1491 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1492 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1493 .clkdm_name = "l4_per_clkdm",
1494 .parent = &l4_div_ck,
1495 .recalc = &followparent_recalc,
1496 };
1497
1498 static struct clk gpio6_ick = {
1499 .name = "gpio6_ick",
1500 .ops = &clkops_omap2_dflt,
1501 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1502 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1503 .clkdm_name = "l4_per_clkdm",
1504 .parent = &l4_div_ck,
1505 .recalc = &followparent_recalc,
1506 };
1507
1508 static struct clk gpmc_ick = {
1509 .name = "gpmc_ick",
1510 .ops = &clkops_omap2_dflt,
1511 .enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
1512 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1513 .clkdm_name = "l3_2_clkdm",
1514 .parent = &l3_div_ck,
1515 .recalc = &followparent_recalc,
1516 };
1517
1518 static const struct clksel dmt1_clk_mux_sel[] = {
1519 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1520 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1521 { .parent = NULL },
1522 };
1523
1524 /*
1525 * Merged dmt1_clk_mux into gptimer1
1526 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
1527 */
1528 static struct clk gpt1_fck = {
1529 .name = "gpt1_fck",
1530 .parent = &sys_clkin_ck,
1531 .clksel = dmt1_clk_mux_sel,
1532 .init = &omap2_init_clksel_parent,
1533 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1534 .clksel_mask = OMAP4430_CLKSEL_MASK,
1535 .ops = &clkops_omap2_dflt,
1536 .recalc = &omap2_clksel_recalc,
1537 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1538 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1539 .clkdm_name = "l4_wkup_clkdm",
1540 };
1541
1542 /*
1543 * Merged cm2_dm10_mux into gptimer10
1544 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1545 */
1546 static struct clk gpt10_fck = {
1547 .name = "gpt10_fck",
1548 .parent = &sys_clkin_ck,
1549 .clksel = dmt1_clk_mux_sel,
1550 .init = &omap2_init_clksel_parent,
1551 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1552 .clksel_mask = OMAP4430_CLKSEL_MASK,
1553 .ops = &clkops_omap2_dflt,
1554 .recalc = &omap2_clksel_recalc,
1555 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1556 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1557 .clkdm_name = "l4_per_clkdm",
1558 };
1559
1560 /*
1561 * Merged cm2_dm11_mux into gptimer11
1562 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1563 */
1564 static struct clk gpt11_fck = {
1565 .name = "gpt11_fck",
1566 .parent = &sys_clkin_ck,
1567 .clksel = dmt1_clk_mux_sel,
1568 .init = &omap2_init_clksel_parent,
1569 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1571 .ops = &clkops_omap2_dflt,
1572 .recalc = &omap2_clksel_recalc,
1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1575 .clkdm_name = "l4_per_clkdm",
1576 };
1577
1578 /*
1579 * Merged cm2_dm2_mux into gptimer2
1580 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1581 */
1582 static struct clk gpt2_fck = {
1583 .name = "gpt2_fck",
1584 .parent = &sys_clkin_ck,
1585 .clksel = dmt1_clk_mux_sel,
1586 .init = &omap2_init_clksel_parent,
1587 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1588 .clksel_mask = OMAP4430_CLKSEL_MASK,
1589 .ops = &clkops_omap2_dflt,
1590 .recalc = &omap2_clksel_recalc,
1591 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1593 .clkdm_name = "l4_per_clkdm",
1594 };
1595
1596 /*
1597 * Merged cm2_dm3_mux into gptimer3
1598 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1599 */
1600 static struct clk gpt3_fck = {
1601 .name = "gpt3_fck",
1602 .parent = &sys_clkin_ck,
1603 .clksel = dmt1_clk_mux_sel,
1604 .init = &omap2_init_clksel_parent,
1605 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1606 .clksel_mask = OMAP4430_CLKSEL_MASK,
1607 .ops = &clkops_omap2_dflt,
1608 .recalc = &omap2_clksel_recalc,
1609 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1610 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1611 .clkdm_name = "l4_per_clkdm",
1612 };
1613
1614 /*
1615 * Merged cm2_dm4_mux into gptimer4
1616 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1617 */
1618 static struct clk gpt4_fck = {
1619 .name = "gpt4_fck",
1620 .parent = &sys_clkin_ck,
1621 .clksel = dmt1_clk_mux_sel,
1622 .init = &omap2_init_clksel_parent,
1623 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1624 .clksel_mask = OMAP4430_CLKSEL_MASK,
1625 .ops = &clkops_omap2_dflt,
1626 .recalc = &omap2_clksel_recalc,
1627 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1628 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1629 .clkdm_name = "l4_per_clkdm",
1630 };
1631
1632 static const struct clksel timer5_sync_mux_sel[] = {
1633 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1634 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1635 { .parent = NULL },
1636 };
1637
1638 /*
1639 * Merged timer5_sync_mux into gptimer5
1640 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention
1641 */
1642 static struct clk gpt5_fck = {
1643 .name = "gpt5_fck",
1644 .parent = &syc_clk_div_ck,
1645 .clksel = timer5_sync_mux_sel,
1646 .init = &omap2_init_clksel_parent,
1647 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1648 .clksel_mask = OMAP4430_CLKSEL_MASK,
1649 .ops = &clkops_omap2_dflt,
1650 .recalc = &omap2_clksel_recalc,
1651 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1653 .clkdm_name = "abe_clkdm",
1654 };
1655
1656 /*
1657 * Merged timer6_sync_mux into gptimer6
1658 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1659 */
1660 static struct clk gpt6_fck = {
1661 .name = "gpt6_fck",
1662 .parent = &syc_clk_div_ck,
1663 .clksel = timer5_sync_mux_sel,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1667 .ops = &clkops_omap2_dflt,
1668 .recalc = &omap2_clksel_recalc,
1669 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "abe_clkdm",
1672 };
1673
1674 /*
1675 * Merged timer7_sync_mux into gptimer7
1676 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1677 */
1678 static struct clk gpt7_fck = {
1679 .name = "gpt7_fck",
1680 .parent = &syc_clk_div_ck,
1681 .clksel = timer5_sync_mux_sel,
1682 .init = &omap2_init_clksel_parent,
1683 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1684 .clksel_mask = OMAP4430_CLKSEL_MASK,
1685 .ops = &clkops_omap2_dflt,
1686 .recalc = &omap2_clksel_recalc,
1687 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1688 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1689 .clkdm_name = "abe_clkdm",
1690 };
1691
1692 /*
1693 * Merged timer8_sync_mux into gptimer8
1694 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1695 */
1696 static struct clk gpt8_fck = {
1697 .name = "gpt8_fck",
1698 .parent = &syc_clk_div_ck,
1699 .clksel = timer5_sync_mux_sel,
1700 .init = &omap2_init_clksel_parent,
1701 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1702 .clksel_mask = OMAP4430_CLKSEL_MASK,
1703 .ops = &clkops_omap2_dflt,
1704 .recalc = &omap2_clksel_recalc,
1705 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1706 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1707 .clkdm_name = "abe_clkdm",
1708 };
1709
1710 /*
1711 * Merged cm2_dm9_mux into gptimer9
1712 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1713 */
1714 static struct clk gpt9_fck = {
1715 .name = "gpt9_fck",
1716 .parent = &sys_clkin_ck,
1717 .clksel = dmt1_clk_mux_sel,
1718 .init = &omap2_init_clksel_parent,
1719 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1720 .clksel_mask = OMAP4430_CLKSEL_MASK,
1721 .ops = &clkops_omap2_dflt,
1722 .recalc = &omap2_clksel_recalc,
1723 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
1724 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1725 .clkdm_name = "l4_per_clkdm",
1726 };
1727
1728 static struct clk hdq1w_fck = {
1729 .name = "hdq1w_fck",
1730 .ops = &clkops_omap2_dflt,
1731 .enable_reg = OMAP4430_CM_L4PER_HDQ1W_CLKCTRL,
1732 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1733 .clkdm_name = "l4_per_clkdm",
1734 .parent = &func_12m_fclk,
1735 .recalc = &followparent_recalc,
1736 };
1737
1738 /* Merged hsi_fclk into hsi */
1739 static struct clk hsi_ick = {
1740 .name = "hsi_ick",
1741 .parent = &dpll_per_m2x2_ck,
1742 .clksel = per_sgx_fclk_div,
1743 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1744 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1745 .ops = &clkops_omap2_dflt,
1746 .recalc = &omap2_clksel_recalc,
1747 .round_rate = &omap2_clksel_round_rate,
1748 .set_rate = &omap2_clksel_set_rate,
1749 .enable_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1750 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1751 .clkdm_name = "l3_init_clkdm",
1752 };
1753
1754 static struct clk i2c1_fck = {
1755 .name = "i2c1_fck",
1756 .ops = &clkops_omap2_dflt,
1757 .enable_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
1758 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1759 .clkdm_name = "l4_per_clkdm",
1760 .parent = &func_96m_fclk,
1761 .recalc = &followparent_recalc,
1762 };
1763
1764 static struct clk i2c2_fck = {
1765 .name = "i2c2_fck",
1766 .ops = &clkops_omap2_dflt,
1767 .enable_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
1768 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1769 .clkdm_name = "l4_per_clkdm",
1770 .parent = &func_96m_fclk,
1771 .recalc = &followparent_recalc,
1772 };
1773
1774 static struct clk i2c3_fck = {
1775 .name = "i2c3_fck",
1776 .ops = &clkops_omap2_dflt,
1777 .enable_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
1778 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1779 .clkdm_name = "l4_per_clkdm",
1780 .parent = &func_96m_fclk,
1781 .recalc = &followparent_recalc,
1782 };
1783
1784 static struct clk i2c4_fck = {
1785 .name = "i2c4_fck",
1786 .ops = &clkops_omap2_dflt,
1787 .enable_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
1788 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1789 .clkdm_name = "l4_per_clkdm",
1790 .parent = &func_96m_fclk,
1791 .recalc = &followparent_recalc,
1792 };
1793
1794 static struct clk iss_fck = {
1795 .name = "iss_fck",
1796 .ops = &clkops_omap2_dflt,
1797 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1798 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1799 .clkdm_name = "iss_clkdm",
1800 .parent = &ducati_clk_mux_ck,
1801 .recalc = &followparent_recalc,
1802 };
1803
1804 static struct clk ivahd_ick = {
1805 .name = "ivahd_ick",
1806 .ops = &clkops_omap2_dflt,
1807 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1808 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1809 .clkdm_name = "ivahd_clkdm",
1810 .parent = &dpll_iva_m5_ck,
1811 .recalc = &followparent_recalc,
1812 };
1813
1814 static struct clk keyboard_fck = {
1815 .name = "keyboard_fck",
1816 .ops = &clkops_omap2_dflt,
1817 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1818 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1819 .clkdm_name = "l4_wkup_clkdm",
1820 .parent = &sys_32k_ck,
1821 .recalc = &followparent_recalc,
1822 };
1823
1824 static struct clk l3_instr_interconnect_ick = {
1825 .name = "l3_instr_interconnect_ick",
1826 .ops = &clkops_omap2_dflt,
1827 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1828 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1829 .clkdm_name = "l3_instr_clkdm",
1830 .parent = &l3_div_ck,
1831 .recalc = &followparent_recalc,
1832 };
1833
1834 static struct clk l3_interconnect_3_ick = {
1835 .name = "l3_interconnect_3_ick",
1836 .ops = &clkops_omap2_dflt,
1837 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1838 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1839 .clkdm_name = "l3_instr_clkdm",
1840 .parent = &l3_div_ck,
1841 .recalc = &followparent_recalc,
1842 };
1843
1844 static struct clk mcasp_sync_mux_ck = {
1845 .name = "mcasp_sync_mux_ck",
1846 .parent = &abe_24m_fclk,
1847 .clksel = dmic_sync_mux_sel,
1848 .init = &omap2_init_clksel_parent,
1849 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1850 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1851 .ops = &clkops_null,
1852 .recalc = &omap2_clksel_recalc,
1853 };
1854
1855 static const struct clksel func_mcasp_abe_gfclk_sel[] = {
1856 { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
1857 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1858 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1859 { .parent = NULL },
1860 };
1861
1862 /* Merged func_mcasp_abe_gfclk into mcasp */
1863 static struct clk mcasp_fck = {
1864 .name = "mcasp_fck",
1865 .parent = &mcasp_sync_mux_ck,
1866 .clksel = func_mcasp_abe_gfclk_sel,
1867 .init = &omap2_init_clksel_parent,
1868 .clksel_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1869 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1870 .ops = &clkops_omap2_dflt,
1871 .recalc = &omap2_clksel_recalc,
1872 .enable_reg = OMAP4430_CM1_ABE_MCASP_CLKCTRL,
1873 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1874 .clkdm_name = "abe_clkdm",
1875 };
1876
1877 static struct clk mcbsp1_sync_mux_ck = {
1878 .name = "mcbsp1_sync_mux_ck",
1879 .parent = &abe_24m_fclk,
1880 .clksel = dmic_sync_mux_sel,
1881 .init = &omap2_init_clksel_parent,
1882 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1883 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1884 .ops = &clkops_null,
1885 .recalc = &omap2_clksel_recalc,
1886 };
1887
1888 static const struct clksel func_mcbsp1_gfclk_sel[] = {
1889 { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
1890 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1891 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1892 { .parent = NULL },
1893 };
1894
1895 /* Merged func_mcbsp1_gfclk into mcbsp1 */
1896 static struct clk mcbsp1_fck = {
1897 .name = "mcbsp1_fck",
1898 .parent = &mcbsp1_sync_mux_ck,
1899 .clksel = func_mcbsp1_gfclk_sel,
1900 .init = &omap2_init_clksel_parent,
1901 .clksel_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1902 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1903 .ops = &clkops_omap2_dflt,
1904 .recalc = &omap2_clksel_recalc,
1905 .enable_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
1906 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1907 .clkdm_name = "abe_clkdm",
1908 };
1909
1910 static struct clk mcbsp2_sync_mux_ck = {
1911 .name = "mcbsp2_sync_mux_ck",
1912 .parent = &abe_24m_fclk,
1913 .clksel = dmic_sync_mux_sel,
1914 .init = &omap2_init_clksel_parent,
1915 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1916 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1917 .ops = &clkops_null,
1918 .recalc = &omap2_clksel_recalc,
1919 };
1920
1921 static const struct clksel func_mcbsp2_gfclk_sel[] = {
1922 { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
1923 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1924 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1925 { .parent = NULL },
1926 };
1927
1928 /* Merged func_mcbsp2_gfclk into mcbsp2 */
1929 static struct clk mcbsp2_fck = {
1930 .name = "mcbsp2_fck",
1931 .parent = &mcbsp2_sync_mux_ck,
1932 .clksel = func_mcbsp2_gfclk_sel,
1933 .init = &omap2_init_clksel_parent,
1934 .clksel_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1935 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1936 .ops = &clkops_omap2_dflt,
1937 .recalc = &omap2_clksel_recalc,
1938 .enable_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
1939 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1940 .clkdm_name = "abe_clkdm",
1941 };
1942
1943 static struct clk mcbsp3_sync_mux_ck = {
1944 .name = "mcbsp3_sync_mux_ck",
1945 .parent = &abe_24m_fclk,
1946 .clksel = dmic_sync_mux_sel,
1947 .init = &omap2_init_clksel_parent,
1948 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1949 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1950 .ops = &clkops_null,
1951 .recalc = &omap2_clksel_recalc,
1952 };
1953
1954 static const struct clksel func_mcbsp3_gfclk_sel[] = {
1955 { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
1956 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1957 { .parent = &slimbus_clk, .rates = div_1_2_rates },
1958 { .parent = NULL },
1959 };
1960
1961 /* Merged func_mcbsp3_gfclk into mcbsp3 */
1962 static struct clk mcbsp3_fck = {
1963 .name = "mcbsp3_fck",
1964 .parent = &mcbsp3_sync_mux_ck,
1965 .clksel = func_mcbsp3_gfclk_sel,
1966 .init = &omap2_init_clksel_parent,
1967 .clksel_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1968 .clksel_mask = OMAP4430_CLKSEL_SOURCE_MASK,
1969 .ops = &clkops_omap2_dflt,
1970 .recalc = &omap2_clksel_recalc,
1971 .enable_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
1972 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1973 .clkdm_name = "abe_clkdm",
1974 };
1975
1976 static struct clk mcbsp4_sync_mux_ck = {
1977 .name = "mcbsp4_sync_mux_ck",
1978 .parent = &func_96m_fclk,
1979 .clksel = mcasp2_fclk_sel,
1980 .init = &omap2_init_clksel_parent,
1981 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
1982 .clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
1983 .ops = &clkops_null,
1984 .recalc = &omap2_clksel_recalc,
1985 };
1986
1987 static const struct clksel per_mcbsp4_gfclk_sel[] = {
1988 { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
1989 { .parent = &pad_clks_ck, .rates = div_1_1_rates },
1990 { .parent = NULL },
1991 };
1992
1993 /* Merged per_mcbsp4_gfclk into mcbsp4 */
1994 static struct clk mcbsp4_fck = {
1995 .name = "mcbsp4_fck",
1996 .parent = &mcbsp4_sync_mux_ck,
1997 .clksel = per_mcbsp4_gfclk_sel,
1998 .init = &omap2_init_clksel_parent,
1999 .clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2000 .clksel_mask = OMAP4430_CLKSEL_SOURCE_24_24_MASK,
2001 .ops = &clkops_omap2_dflt,
2002 .recalc = &omap2_clksel_recalc,
2003 .enable_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
2004 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2005 .clkdm_name = "l4_per_clkdm",
2006 };
2007
2008 static struct clk mcspi1_fck = {
2009 .name = "mcspi1_fck",
2010 .ops = &clkops_omap2_dflt,
2011 .enable_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
2012 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2013 .clkdm_name = "l4_per_clkdm",
2014 .parent = &func_48m_fclk,
2015 .recalc = &followparent_recalc,
2016 };
2017
2018 static struct clk mcspi2_fck = {
2019 .name = "mcspi2_fck",
2020 .ops = &clkops_omap2_dflt,
2021 .enable_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
2022 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2023 .clkdm_name = "l4_per_clkdm",
2024 .parent = &func_48m_fclk,
2025 .recalc = &followparent_recalc,
2026 };
2027
2028 static struct clk mcspi3_fck = {
2029 .name = "mcspi3_fck",
2030 .ops = &clkops_omap2_dflt,
2031 .enable_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
2032 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2033 .clkdm_name = "l4_per_clkdm",
2034 .parent = &func_48m_fclk,
2035 .recalc = &followparent_recalc,
2036 };
2037
2038 static struct clk mcspi4_fck = {
2039 .name = "mcspi4_fck",
2040 .ops = &clkops_omap2_dflt,
2041 .enable_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
2042 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2043 .clkdm_name = "l4_per_clkdm",
2044 .parent = &func_48m_fclk,
2045 .recalc = &followparent_recalc,
2046 };
2047
2048 /* Merged hsmmc1_fclk into mmc1 */
2049 static struct clk mmc1_fck = {
2050 .name = "mmc1_fck",
2051 .parent = &func_64m_fclk,
2052 .clksel = hsmmc6_fclk_sel,
2053 .init = &omap2_init_clksel_parent,
2054 .clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2055 .clksel_mask = OMAP4430_CLKSEL_MASK,
2056 .ops = &clkops_omap2_dflt,
2057 .recalc = &omap2_clksel_recalc,
2058 .enable_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
2059 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2060 .clkdm_name = "l3_init_clkdm",
2061 };
2062
2063 /* Merged hsmmc2_fclk into mmc2 */
2064 static struct clk mmc2_fck = {
2065 .name = "mmc2_fck",
2066 .parent = &func_64m_fclk,
2067 .clksel = hsmmc6_fclk_sel,
2068 .init = &omap2_init_clksel_parent,
2069 .clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2070 .clksel_mask = OMAP4430_CLKSEL_MASK,
2071 .ops = &clkops_omap2_dflt,
2072 .recalc = &omap2_clksel_recalc,
2073 .enable_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
2074 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2075 .clkdm_name = "l3_init_clkdm",
2076 };
2077
2078 static struct clk mmc3_fck = {
2079 .name = "mmc3_fck",
2080 .ops = &clkops_omap2_dflt,
2081 .enable_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
2082 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2083 .clkdm_name = "l4_per_clkdm",
2084 .parent = &func_48m_fclk,
2085 .recalc = &followparent_recalc,
2086 };
2087
2088 static struct clk mmc4_fck = {
2089 .name = "mmc4_fck",
2090 .ops = &clkops_omap2_dflt,
2091 .enable_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
2092 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2093 .clkdm_name = "l4_per_clkdm",
2094 .parent = &func_48m_fclk,
2095 .recalc = &followparent_recalc,
2096 };
2097
2098 static struct clk mmc5_fck = {
2099 .name = "mmc5_fck",
2100 .ops = &clkops_omap2_dflt,
2101 .enable_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
2102 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2103 .clkdm_name = "l4_per_clkdm",
2104 .parent = &func_48m_fclk,
2105 .recalc = &followparent_recalc,
2106 };
2107
2108 static struct clk ocp_wp1_ick = {
2109 .name = "ocp_wp1_ick",
2110 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2112 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2113 .clkdm_name = "l3_instr_clkdm",
2114 .parent = &l3_div_ck,
2115 .recalc = &followparent_recalc,
2116 };
2117
2118 static struct clk pdm_fck = {
2119 .name = "pdm_fck",
2120 .ops = &clkops_omap2_dflt,
2121 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
2122 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2123 .clkdm_name = "abe_clkdm",
2124 .parent = &pad_clks_ck,
2125 .recalc = &followparent_recalc,
2126 };
2127
2128 static struct clk pkaeip29_fck = {
2129 .name = "pkaeip29_fck",
2130 .ops = &clkops_omap2_dflt,
2131 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2133 .clkdm_name = "l4_secure_clkdm",
2134 .parent = &l4_div_ck,
2135 .recalc = &followparent_recalc,
2136 };
2137
2138 static struct clk rng_ick = {
2139 .name = "rng_ick",
2140 .ops = &clkops_omap2_dflt,
2141 .enable_reg = OMAP4430_CM_L4SEC_RNG_CLKCTRL,
2142 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2143 .clkdm_name = "l4_secure_clkdm",
2144 .parent = &l4_div_ck,
2145 .recalc = &followparent_recalc,
2146 };
2147
2148 static struct clk sha2md51_fck = {
2149 .name = "sha2md51_fck",
2150 .ops = &clkops_omap2_dflt,
2151 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2152 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2153 .clkdm_name = "l4_secure_clkdm",
2154 .parent = &l3_div_ck,
2155 .recalc = &followparent_recalc,
2156 };
2157
2158 static struct clk sl2_ick = {
2159 .name = "sl2_ick",
2160 .ops = &clkops_omap2_dflt,
2161 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2162 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2163 .clkdm_name = "ivahd_clkdm",
2164 .parent = &dpll_iva_m5_ck,
2165 .recalc = &followparent_recalc,
2166 };
2167
2168 static struct clk slimbus1_fck = {
2169 .name = "slimbus1_fck",
2170 .ops = &clkops_omap2_dflt,
2171 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2172 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2173 .clkdm_name = "abe_clkdm",
2174 .parent = &ocp_abe_iclk,
2175 .recalc = &followparent_recalc,
2176 };
2177
2178 static struct clk slimbus2_fck = {
2179 .name = "slimbus2_fck",
2180 .ops = &clkops_omap2_dflt,
2181 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2182 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2183 .clkdm_name = "l4_per_clkdm",
2184 .parent = &l4_div_ck,
2185 .recalc = &followparent_recalc,
2186 };
2187
2188 static struct clk sr_core_fck = {
2189 .name = "sr_core_fck",
2190 .ops = &clkops_omap2_dflt,
2191 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2192 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2193 .clkdm_name = "l4_ao_clkdm",
2194 .parent = &l4_wkup_clk_mux_ck,
2195 .recalc = &followparent_recalc,
2196 };
2197
2198 static struct clk sr_iva_fck = {
2199 .name = "sr_iva_fck",
2200 .ops = &clkops_omap2_dflt,
2201 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2202 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2203 .clkdm_name = "l4_ao_clkdm",
2204 .parent = &l4_wkup_clk_mux_ck,
2205 .recalc = &followparent_recalc,
2206 };
2207
2208 static struct clk sr_mpu_fck = {
2209 .name = "sr_mpu_fck",
2210 .ops = &clkops_omap2_dflt,
2211 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2212 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2213 .clkdm_name = "l4_ao_clkdm",
2214 .parent = &l4_wkup_clk_mux_ck,
2215 .recalc = &followparent_recalc,
2216 };
2217
2218 static struct clk tesla_ick = {
2219 .name = "tesla_ick",
2220 .ops = &clkops_omap2_dflt,
2221 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
2222 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2223 .clkdm_name = "tesla_clkdm",
2224 .parent = &dpll_iva_m4_ck,
2225 .recalc = &followparent_recalc,
2226 };
2227
2228 static struct clk uart1_fck = {
2229 .name = "uart1_fck",
2230 .ops = &clkops_omap2_dflt,
2231 .enable_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
2232 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2233 .clkdm_name = "l4_per_clkdm",
2234 .parent = &func_48m_fclk,
2235 .recalc = &followparent_recalc,
2236 };
2237
2238 static struct clk uart2_fck = {
2239 .name = "uart2_fck",
2240 .ops = &clkops_omap2_dflt,
2241 .enable_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
2242 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2243 .clkdm_name = "l4_per_clkdm",
2244 .parent = &func_48m_fclk,
2245 .recalc = &followparent_recalc,
2246 };
2247
2248 static struct clk uart3_fck = {
2249 .name = "uart3_fck",
2250 .ops = &clkops_omap2_dflt,
2251 .enable_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
2252 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2253 .clkdm_name = "l4_per_clkdm",
2254 .parent = &func_48m_fclk,
2255 .recalc = &followparent_recalc,
2256 };
2257
2258 static struct clk uart4_fck = {
2259 .name = "uart4_fck",
2260 .ops = &clkops_omap2_dflt,
2261 .enable_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
2262 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2263 .clkdm_name = "l4_per_clkdm",
2264 .parent = &func_48m_fclk,
2265 .recalc = &followparent_recalc,
2266 };
2267
2268 static struct clk unipro1_fck = {
2269 .name = "unipro1_fck",
2270 .ops = &clkops_omap2_dflt,
2271 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL,
2272 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2273 .clkdm_name = "l3_init_clkdm",
2274 .parent = &func_96m_fclk,
2275 .recalc = &followparent_recalc,
2276 };
2277
2278 static struct clk usb_host_fck = {
2279 .name = "usb_host_fck",
2280 .ops = &clkops_omap2_dflt,
2281 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2282 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2283 .clkdm_name = "l3_init_clkdm",
2284 .parent = &init_60m_fclk,
2285 .recalc = &followparent_recalc,
2286 };
2287
2288 static struct clk usb_host_fs_fck = {
2289 .name = "usb_host_fs_fck",
2290 .ops = &clkops_omap2_dflt,
2291 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2292 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2293 .clkdm_name = "l3_init_clkdm",
2294 .parent = &func_48mc_fclk,
2295 .recalc = &followparent_recalc,
2296 };
2297
2298 static struct clk usb_otg_ick = {
2299 .name = "usb_otg_ick",
2300 .ops = &clkops_omap2_dflt,
2301 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2302 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2303 .clkdm_name = "l3_init_clkdm",
2304 .parent = &l3_div_ck,
2305 .recalc = &followparent_recalc,
2306 };
2307
2308 static struct clk usb_tll_ick = {
2309 .name = "usb_tll_ick",
2310 .ops = &clkops_omap2_dflt,
2311 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2312 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2313 .clkdm_name = "l3_init_clkdm",
2314 .parent = &l4_div_ck,
2315 .recalc = &followparent_recalc,
2316 };
2317
2318 static struct clk usbphyocp2scp_ick = {
2319 .name = "usbphyocp2scp_ick",
2320 .ops = &clkops_omap2_dflt,
2321 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2322 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2323 .clkdm_name = "l3_init_clkdm",
2324 .parent = &l4_div_ck,
2325 .recalc = &followparent_recalc,
2326 };
2327
2328 static struct clk usim_fck = {
2329 .name = "usim_fck",
2330 .ops = &clkops_omap2_dflt,
2331 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2332 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2333 .clkdm_name = "l4_wkup_clkdm",
2334 .parent = &sys_32k_ck,
2335 .recalc = &followparent_recalc,
2336 };
2337
2338 static struct clk wdt2_fck = {
2339 .name = "wdt2_fck",
2340 .ops = &clkops_omap2_dflt,
2341 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2343 .clkdm_name = "l4_wkup_clkdm",
2344 .parent = &sys_32k_ck,
2345 .recalc = &followparent_recalc,
2346 };
2347
2348 static struct clk wdt3_fck = {
2349 .name = "wdt3_fck",
2350 .ops = &clkops_omap2_dflt,
2351 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2352 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2353 .clkdm_name = "abe_clkdm",
2354 .parent = &sys_32k_ck,
2355 .recalc = &followparent_recalc,
2356 };
2357
2358 /* Remaining optional clocks */
2359 static const struct clksel otg_60m_gfclk_sel[] = {
2360 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2361 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2362 { .parent = NULL },
2363 };
2364
2365 static struct clk otg_60m_gfclk_ck = {
2366 .name = "otg_60m_gfclk_ck",
2367 .parent = &utmi_phy_clkout_ck,
2368 .clksel = otg_60m_gfclk_sel,
2369 .init = &omap2_init_clksel_parent,
2370 .clksel_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2371 .clksel_mask = OMAP4430_CLKSEL_60M_MASK,
2372 .ops = &clkops_null,
2373 .recalc = &omap2_clksel_recalc,
2374 };
2375
2376 static const struct clksel stm_clk_div_div[] = {
2377 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2378 { .parent = NULL },
2379 };
2380
2381 static struct clk stm_clk_div_ck = {
2382 .name = "stm_clk_div_ck",
2383 .parent = &pmd_stm_clock_mux_ck,
2384 .clksel = stm_clk_div_div,
2385 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2386 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2387 .ops = &clkops_null,
2388 .recalc = &omap2_clksel_recalc,
2389 .round_rate = &omap2_clksel_round_rate,
2390 .set_rate = &omap2_clksel_set_rate,
2391 };
2392
2393 static const struct clksel trace_clk_div_div[] = {
2394 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2395 { .parent = NULL },
2396 };
2397
2398 static struct clk trace_clk_div_ck = {
2399 .name = "trace_clk_div_ck",
2400 .parent = &pmd_trace_clk_mux_ck,
2401 .clksel = trace_clk_div_div,
2402 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2403 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2404 .ops = &clkops_null,
2405 .recalc = &omap2_clksel_recalc,
2406 .round_rate = &omap2_clksel_round_rate,
2407 .set_rate = &omap2_clksel_set_rate,
2408 };
2409
2410 static const struct clksel_rate div2_14to18_rates[] = {
2411 { .div = 14, .val = 0, .flags = RATE_IN_4430 },
2412 { .div = 18, .val = 1, .flags = RATE_IN_4430 },
2413 { .div = 0 },
2414 };
2415
2416 static const struct clksel usim_fclk_div[] = {
2417 { .parent = &dpll_per_m4_ck, .rates = div2_14to18_rates },
2418 { .parent = NULL },
2419 };
2420
2421 static struct clk usim_fclk = {
2422 .name = "usim_fclk",
2423 .parent = &dpll_per_m4_ck,
2424 .clksel = usim_fclk_div,
2425 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2426 .clksel_mask = OMAP4430_CLKSEL_DIV_MASK,
2427 .ops = &clkops_null,
2428 .recalc = &omap2_clksel_recalc,
2429 .round_rate = &omap2_clksel_round_rate,
2430 .set_rate = &omap2_clksel_set_rate,
2431 };
2432
2433 static const struct clksel utmi_p1_gfclk_sel[] = {
2434 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2435 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2436 { .parent = NULL },
2437 };
2438
2439 static struct clk utmi_p1_gfclk_ck = {
2440 .name = "utmi_p1_gfclk_ck",
2441 .parent = &init_60m_fclk,
2442 .clksel = utmi_p1_gfclk_sel,
2443 .init = &omap2_init_clksel_parent,
2444 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2445 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2446 .ops = &clkops_null,
2447 .recalc = &omap2_clksel_recalc,
2448 };
2449
2450 static const struct clksel utmi_p2_gfclk_sel[] = {
2451 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2452 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2453 { .parent = NULL },
2454 };
2455
2456 static struct clk utmi_p2_gfclk_ck = {
2457 .name = "utmi_p2_gfclk_ck",
2458 .parent = &init_60m_fclk,
2459 .clksel = utmi_p2_gfclk_sel,
2460 .init = &omap2_init_clksel_parent,
2461 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2462 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2463 .ops = &clkops_null,
2464 .recalc = &omap2_clksel_recalc,
2465 };
2466
2467 /*
2468 * clkdev
2469 */
2470
2471 static struct omap_clk omap44xx_clks[] = {
2472 CLK(NULL, "extalt_clkin_ck", &extalt_clkin_ck, CK_443X),
2473 CLK(NULL, "pad_clks_ck", &pad_clks_ck, CK_443X),
2474 CLK(NULL, "pad_slimbus_core_clks_ck", &pad_slimbus_core_clks_ck, CK_443X),
2475 CLK(NULL, "secure_32k_clk_src_ck", &secure_32k_clk_src_ck, CK_443X),
2476 CLK(NULL, "slimbus_clk", &slimbus_clk, CK_443X),
2477 CLK(NULL, "sys_32k_ck", &sys_32k_ck, CK_443X),
2478 CLK(NULL, "virt_12000000_ck", &virt_12000000_ck, CK_443X),
2479 CLK(NULL, "virt_13000000_ck", &virt_13000000_ck, CK_443X),
2480 CLK(NULL, "virt_16800000_ck", &virt_16800000_ck, CK_443X),
2481 CLK(NULL, "virt_19200000_ck", &virt_19200000_ck, CK_443X),
2482 CLK(NULL, "virt_26000000_ck", &virt_26000000_ck, CK_443X),
2483 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2484 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2485 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
2486 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2487 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2488 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2489 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2490 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X),
2491 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2492 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2493 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
2494 CLK(NULL, "abe_24m_fclk", &abe_24m_fclk, CK_443X),
2495 CLK(NULL, "abe_clk", &abe_clk, CK_443X),
2496 CLK(NULL, "aess_fclk", &aess_fclk, CK_443X),
2497 CLK(NULL, "dpll_abe_m3_ck", &dpll_abe_m3_ck, CK_443X),
2498 CLK(NULL, "core_hsd_byp_clk_mux_ck", &core_hsd_byp_clk_mux_ck, CK_443X),
2499 CLK(NULL, "dpll_core_ck", &dpll_core_ck, CK_443X),
2500 CLK(NULL, "dpll_core_m6_ck", &dpll_core_m6_ck, CK_443X),
2501 CLK(NULL, "dbgclk_mux_ck", &dbgclk_mux_ck, CK_443X),
2502 CLK(NULL, "dpll_core_m2_ck", &dpll_core_m2_ck, CK_443X),
2503 CLK(NULL, "ddrphy_ck", &ddrphy_ck, CK_443X),
2504 CLK(NULL, "dpll_core_m5_ck", &dpll_core_m5_ck, CK_443X),
2505 CLK(NULL, "div_core_ck", &div_core_ck, CK_443X),
2506 CLK(NULL, "div_iva_hs_clk", &div_iva_hs_clk, CK_443X),
2507 CLK(NULL, "div_mpu_hs_clk", &div_mpu_hs_clk, CK_443X),
2508 CLK(NULL, "dpll_core_m4_ck", &dpll_core_m4_ck, CK_443X),
2509 CLK(NULL, "dll_clk_div_ck", &dll_clk_div_ck, CK_443X),
2510 CLK(NULL, "dpll_abe_m2_ck", &dpll_abe_m2_ck, CK_443X),
2511 CLK(NULL, "dpll_core_m3_ck", &dpll_core_m3_ck, CK_443X),
2512 CLK(NULL, "dpll_core_m7_ck", &dpll_core_m7_ck, CK_443X),
2513 CLK(NULL, "iva_hsd_byp_clk_mux_ck", &iva_hsd_byp_clk_mux_ck, CK_443X),
2514 CLK(NULL, "dpll_iva_ck", &dpll_iva_ck, CK_443X),
2515 CLK(NULL, "dpll_iva_m4_ck", &dpll_iva_m4_ck, CK_443X),
2516 CLK(NULL, "dpll_iva_m5_ck", &dpll_iva_m5_ck, CK_443X),
2517 CLK(NULL, "dpll_mpu_ck", &dpll_mpu_ck, CK_443X),
2518 CLK(NULL, "dpll_mpu_m2_ck", &dpll_mpu_m2_ck, CK_443X),
2519 CLK(NULL, "per_hs_clk_div_ck", &per_hs_clk_div_ck, CK_443X),
2520 CLK(NULL, "per_hsd_byp_clk_mux_ck", &per_hsd_byp_clk_mux_ck, CK_443X),
2521 CLK(NULL, "dpll_per_ck", &dpll_per_ck, CK_443X),
2522 CLK(NULL, "dpll_per_m2_ck", &dpll_per_m2_ck, CK_443X),
2523 CLK(NULL, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, CK_443X),
2524 CLK(NULL, "dpll_per_m3_ck", &dpll_per_m3_ck, CK_443X),
2525 CLK(NULL, "dpll_per_m4_ck", &dpll_per_m4_ck, CK_443X),
2526 CLK(NULL, "dpll_per_m5_ck", &dpll_per_m5_ck, CK_443X),
2527 CLK(NULL, "dpll_per_m6_ck", &dpll_per_m6_ck, CK_443X),
2528 CLK(NULL, "dpll_per_m7_ck", &dpll_per_m7_ck, CK_443X),
2529 CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
2530 CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
2531 CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
2532 CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
2533 CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
2534 CLK(NULL, "dpll_usb_m2_ck", &dpll_usb_m2_ck, CK_443X),
2535 CLK(NULL, "ducati_clk_mux_ck", &ducati_clk_mux_ck, CK_443X),
2536 CLK(NULL, "func_12m_fclk", &func_12m_fclk, CK_443X),
2537 CLK(NULL, "func_24m_clk", &func_24m_clk, CK_443X),
2538 CLK(NULL, "func_24mc_fclk", &func_24mc_fclk, CK_443X),
2539 CLK(NULL, "func_48m_fclk", &func_48m_fclk, CK_443X),
2540 CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
2541 CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
2542 CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
2543 CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
2544 CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
2545 CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
2546 CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
2547 CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
2548 CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
2549 CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
2550 CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
2551 CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
2552 CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
2553 CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
2554 CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
2555 CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
2556 CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
2557 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2558 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2559 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2560 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X),
2561 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2562 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2563 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2564 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2565 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X),
2566 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X),
2567 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X),
2568 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2569 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X),
2570 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X),
2571 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2572 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2573 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2574 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2575 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2576 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2577 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2578 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X),
2579 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2580 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2581 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2582 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2583 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2584 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2585 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2586 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2587 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2588 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2589 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2590 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X),
2591 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2592 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2593 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2594 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2595 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2596 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X),
2597 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X),
2598 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X),
2599 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X),
2600 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2601 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2602 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
2603 CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
2604 CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
2605 CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
2606 CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
2607 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2608 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2609 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
2610 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2611 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2612 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
2613 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
2614 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X),
2615 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X),
2616 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2617 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2618 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2619 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X),
2620 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X),
2621 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X),
2622 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2623 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X),
2624 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X),
2625 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2626 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2627 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X),
2628 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X),
2629 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X),
2630 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X),
2631 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2632 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2633 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2634 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2635 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2636 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2637 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2638 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X),
2639 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X),
2640 CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X),
2641 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2642 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X),
2643 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X),
2644 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2645 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2646 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2647 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2648 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2649 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2650 CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
2651 CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
2652 CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
2653 CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
2654 CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
2655 CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
2656 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2657 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2658 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
2659 CLK(NULL, "gpt3_ick", &dummy_ck, CK_443X),
2660 CLK(NULL, "gpt4_ick", &dummy_ck, CK_443X),
2661 CLK(NULL, "gpt5_ick", &dummy_ck, CK_443X),
2662 CLK(NULL, "gpt6_ick", &dummy_ck, CK_443X),
2663 CLK(NULL, "gpt7_ick", &dummy_ck, CK_443X),
2664 CLK(NULL, "gpt8_ick", &dummy_ck, CK_443X),
2665 CLK(NULL, "gpt9_ick", &dummy_ck, CK_443X),
2666 CLK(NULL, "gpt10_ick", &dummy_ck, CK_443X),
2667 CLK(NULL, "gpt11_ick", &dummy_ck, CK_443X),
2668 CLK("i2c_omap.1", "ick", &dummy_ck, CK_443X),
2669 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
2670 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
2671 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
2672 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2673 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2674 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2675 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
2676 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2677 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2678 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2679 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2680 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2681 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2682 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2683 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2684 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2685 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2686 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2687 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
2688 CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
2689 CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
2690 };
2691
2692 int __init omap4xxx_clk_init(void)
2693 {
2694 struct omap_clk *c;
2695 u32 cpu_clkflg;
2696
2697 if (cpu_is_omap44xx()) {
2698 cpu_mask = RATE_IN_4430;
2699 cpu_clkflg = CK_443X;
2700 }
2701
2702 clk_init(&omap2_clk_functions);
2703
2704 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2705 c++)
2706 clk_preinit(c->lk.clk);
2707
2708 for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
2709 c++)
2710 if (c->cpu & cpu_clkflg) {
2711 clkdev_add(&c->lk);
2712 clk_register(c->lk.clk);
2713 omap2_init_clk_clkdm(c->lk.clk);
2714 }
2715
2716 recalculate_root_clocks();
2717
2718 /*
2719 * Only enable those clocks we will need, let the drivers
2720 * enable other clocks as necessary
2721 */
2722 clk_enable_init_clocks();
2723
2724 return 0;
2725 }
Tomato firmware and modifications.