release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap2/clock2420_data.c

   1 /*
   2  *  linux/arch/arm/mach-omap2/clock2420_data.c
   3  *
   4  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
   5  *  Copyright (C) 2004-2010 Nokia Corporation
   6  *
   7  *  Contacts:
   8  *  Richard Woodruff <r-woodruff2@ti.com>
   9  *  Paul Walmsley
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/clk.h>
  18 #include <linux/list.h>
  19
  20 #include <plat/clkdev_omap.h>
  21
  22 #include "clock.h"
  23 #include "clock2xxx.h"
  24 #include "opp2xxx.h"
  25 #include "prm.h"
  26 #include "cm.h"
  27 #include "prm-regbits-24xx.h"
  28 #include "cm-regbits-24xx.h"
  29 #include "sdrc.h"
  30
  31 #define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR
  32
  33 /*
  34  * 2420 clock tree.
  35  *
  36  * NOTE:In many cases here we are assigning a 'default' parent. In many
  37  *      cases the parent is selectable. The get/set parent calls will also
  38  *      switch sources.
  39  *
  40  *      Many some clocks say always_enabled, but they can be auto idled for
  41  *      power savings. They will always be available upon clock request.
  42  *
  43  *      Several sources are given initial rates which may be wrong, this will
  44  *      be fixed up in the init func.
  45  *
  46  *      Things are broadly separated below by clock domains. It is
  47  *      noteworthy that most periferals have dependencies on multiple clock
  48  *      domains. Many get their interface clocks from the L4 domain, but get
  49  *      functional clocks from fixed sources or other core domain derived
  50  *      clocks.
  51  */
  52
  53 /* Base external input clocks */
  54 static struct clk func_32k_ck = {
  55         .name           = "func_32k_ck",
  56         .ops            = &clkops_null,
  57         .rate           = 32000,
  58         .clkdm_name     = "wkup_clkdm",
  59 };
  60
  61 static struct clk secure_32k_ck = {
  62         .name           = "secure_32k_ck",
  63         .ops            = &clkops_null,
  64         .rate           = 32768,
  65         .clkdm_name     = "wkup_clkdm",
  66 };
  67
  68 /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
  69 static struct clk osc_ck = {            /* (*12, *13, 19.2, *26, 38.4)MHz */
  70         .name           = "osc_ck",
  71         .ops            = &clkops_oscck,
  72         .clkdm_name     = "wkup_clkdm",
  73         .recalc         = &omap2_osc_clk_recalc,
  74 };
  75
  76 /* Without modem likely 12MHz, with modem likely 13MHz */
  77 static struct clk sys_ck = {            /* (*12, *13, 19.2, 26, 38.4)MHz */
  78         .name           = "sys_ck",             /* ~ ref_clk also */
  79         .ops            = &clkops_null,
  80         .parent         = &osc_ck,
  81         .clkdm_name     = "wkup_clkdm",
  82         .recalc         = &omap2xxx_sys_clk_recalc,
  83 };
  84
  85 static struct clk alt_ck = {            /* Typical 54M or 48M, may not exist */
  86         .name           = "alt_ck",
  87         .ops            = &clkops_null,
  88         .rate           = 54000000,
  89         .clkdm_name     = "wkup_clkdm",
  90 };
  91
  92 /*
  93  * Analog domain root source clocks
  94  */
  95
  96 /* dpll_ck, is broken out in to special cases through clksel */
  97 /* REVISIT: Rate changes on dpll_ck trigger a full set change.  ...
  98  * deal with this
  99  */
 100
 101 static struct dpll_data dpll_dd = {
 102         .mult_div1_reg          = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 103         .mult_mask              = OMAP24XX_DPLL_MULT_MASK,
 104         .div1_mask              = OMAP24XX_DPLL_DIV_MASK,
 105         .clk_bypass             = &sys_ck,
 106         .clk_ref                = &sys_ck,
 107         .control_reg            = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 108         .enable_mask            = OMAP24XX_EN_DPLL_MASK,
 109         .max_multiplier         = 1023,
 110         .min_divider            = 1,
 111         .max_divider            = 16,
 112         .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 113 };
 114
 115 static struct clk dpll_ck = {
 116         .name           = "dpll_ck",
 117         .ops            = &clkops_null,
 118         .parent         = &sys_ck,              /* Can be func_32k also */
 119         .dpll_data      = &dpll_dd,
 120         .clkdm_name     = "wkup_clkdm",
 121         .recalc         = &omap2_dpllcore_recalc,
 122         .set_rate       = &omap2_reprogram_dpllcore,
 123 };
 124
 125 static struct clk apll96_ck = {
 126         .name           = "apll96_ck",
 127         .ops            = &clkops_apll96,
 128         .parent         = &sys_ck,
 129         .rate           = 96000000,
 130         .flags          = ENABLE_ON_INIT,
 131         .clkdm_name     = "wkup_clkdm",
 132         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 133         .enable_bit     = OMAP24XX_EN_96M_PLL_SHIFT,
 134 };
 135
 136 static struct clk apll54_ck = {
 137         .name           = "apll54_ck",
 138         .ops            = &clkops_apll54,
 139         .parent         = &sys_ck,
 140         .rate           = 54000000,
 141         .flags          = ENABLE_ON_INIT,
 142         .clkdm_name     = "wkup_clkdm",
 143         .enable_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
 144         .enable_bit     = OMAP24XX_EN_54M_PLL_SHIFT,
 145 };
 146
 147 /*
 148  * PRCM digital base sources
 149  */
 150
 151 /* func_54m_ck */
 152
 153 static const struct clksel_rate func_54m_apll54_rates[] = {
 154         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 155         { .div = 0 },
 156 };
 157
 158 static const struct clksel_rate func_54m_alt_rates[] = {
 159         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 160         { .div = 0 },
 161 };
 162
 163 static const struct clksel func_54m_clksel[] = {
 164         { .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
 165         { .parent = &alt_ck,    .rates = func_54m_alt_rates, },
 166         { .parent = NULL },
 167 };
 168
 169 static struct clk func_54m_ck = {
 170         .name           = "func_54m_ck",
 171         .ops            = &clkops_null,
 172         .parent         = &apll54_ck,   /* can also be alt_clk */
 173         .clkdm_name     = "wkup_clkdm",
 174         .init           = &omap2_init_clksel_parent,
 175         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 176         .clksel_mask    = OMAP24XX_54M_SOURCE_MASK,
 177         .clksel         = func_54m_clksel,
 178         .recalc         = &omap2_clksel_recalc,
 179 };
 180
 181 static struct clk core_ck = {
 182         .name           = "core_ck",
 183         .ops            = &clkops_null,
 184         .parent         = &dpll_ck,             /* can also be 32k */
 185         .clkdm_name     = "wkup_clkdm",
 186         .recalc         = &followparent_recalc,
 187 };
 188
 189 static struct clk func_96m_ck = {
 190         .name           = "func_96m_ck",
 191         .ops            = &clkops_null,
 192         .parent         = &apll96_ck,
 193         .clkdm_name     = "wkup_clkdm",
 194         .recalc         = &followparent_recalc,
 195 };
 196
 197 /* func_48m_ck */
 198
 199 static const struct clksel_rate func_48m_apll96_rates[] = {
 200         { .div = 2, .val = 0, .flags = RATE_IN_24XX },
 201         { .div = 0 },
 202 };
 203
 204 static const struct clksel_rate func_48m_alt_rates[] = {
 205         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 206         { .div = 0 },
 207 };
 208
 209 static const struct clksel func_48m_clksel[] = {
 210         { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
 211         { .parent = &alt_ck, .rates = func_48m_alt_rates },
 212         { .parent = NULL }
 213 };
 214
 215 static struct clk func_48m_ck = {
 216         .name           = "func_48m_ck",
 217         .ops            = &clkops_null,
 218         .parent         = &apll96_ck,    /* 96M or Alt */
 219         .clkdm_name     = "wkup_clkdm",
 220         .init           = &omap2_init_clksel_parent,
 221         .clksel_reg     = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
 222         .clksel_mask    = OMAP24XX_48M_SOURCE_MASK,
 223         .clksel         = func_48m_clksel,
 224         .recalc         = &omap2_clksel_recalc,
 225         .round_rate     = &omap2_clksel_round_rate,
 226         .set_rate       = &omap2_clksel_set_rate
 227 };
 228
 229 static struct clk func_12m_ck = {
 230         .name           = "func_12m_ck",
 231         .ops            = &clkops_null,
 232         .parent         = &func_48m_ck,
 233         .fixed_div      = 4,
 234         .clkdm_name     = "wkup_clkdm",
 235         .recalc         = &omap_fixed_divisor_recalc,
 236 };
 237
 238 /* Secure timer, only available in secure mode */
 239 static struct clk wdt1_osc_ck = {
 240         .name           = "ck_wdt1_osc",
 241         .ops            = &clkops_null, /* RMK: missing? */
 242         .parent         = &osc_ck,
 243         .recalc         = &followparent_recalc,
 244 };
 245
 246 /*
 247  * The common_clkout* clksel_rate structs are common to
 248  * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 249  * sys_clkout2_* are 2420-only, so the
 250  * clksel_rate flags fields are inaccurate for those clocks. This is
 251  * harmless since access to those clocks are gated by the struct clk
 252  * flags fields, which mark them as 2420-only.
 253  */
 254 static const struct clksel_rate common_clkout_src_core_rates[] = {
 255         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 256         { .div = 0 }
 257 };
 258
 259 static const struct clksel_rate common_clkout_src_sys_rates[] = {
 260         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 261         { .div = 0 }
 262 };
 263
 264 static const struct clksel_rate common_clkout_src_96m_rates[] = {
 265         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 266         { .div = 0 }
 267 };
 268
 269 static const struct clksel_rate common_clkout_src_54m_rates[] = {
 270         { .div = 1, .val = 3, .flags = RATE_IN_24XX },
 271         { .div = 0 }
 272 };
 273
 274 static const struct clksel common_clkout_src_clksel[] = {
 275         { .parent = &core_ck,     .rates = common_clkout_src_core_rates },
 276         { .parent = &sys_ck,      .rates = common_clkout_src_sys_rates },
 277         { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
 278         { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
 279         { .parent = NULL }
 280 };
 281
 282 static struct clk sys_clkout_src = {
 283         .name           = "sys_clkout_src",
 284         .ops            = &clkops_omap2_dflt,
 285         .parent         = &func_54m_ck,
 286         .clkdm_name     = "wkup_clkdm",
 287         .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 288         .enable_bit     = OMAP24XX_CLKOUT_EN_SHIFT,
 289         .init           = &omap2_init_clksel_parent,
 290         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 291         .clksel_mask    = OMAP24XX_CLKOUT_SOURCE_MASK,
 292         .clksel         = common_clkout_src_clksel,
 293         .recalc         = &omap2_clksel_recalc,
 294         .round_rate     = &omap2_clksel_round_rate,
 295         .set_rate       = &omap2_clksel_set_rate
 296 };
 297
 298 static const struct clksel_rate common_clkout_rates[] = {
 299         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 300         { .div = 2, .val = 1, .flags = RATE_IN_24XX },
 301         { .div = 4, .val = 2, .flags = RATE_IN_24XX },
 302         { .div = 8, .val = 3, .flags = RATE_IN_24XX },
 303         { .div = 16, .val = 4, .flags = RATE_IN_24XX },
 304         { .div = 0 },
 305 };
 306
 307 static const struct clksel sys_clkout_clksel[] = {
 308         { .parent = &sys_clkout_src, .rates = common_clkout_rates },
 309         { .parent = NULL }
 310 };
 311
 312 static struct clk sys_clkout = {
 313         .name           = "sys_clkout",
 314         .ops            = &clkops_null,
 315         .parent         = &sys_clkout_src,
 316         .clkdm_name     = "wkup_clkdm",
 317         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 318         .clksel_mask    = OMAP24XX_CLKOUT_DIV_MASK,
 319         .clksel         = sys_clkout_clksel,
 320         .recalc         = &omap2_clksel_recalc,
 321         .round_rate     = &omap2_clksel_round_rate,
 322         .set_rate       = &omap2_clksel_set_rate
 323 };
 324
 325 /* In 2430, new in 2420 ES2 */
 326 static struct clk sys_clkout2_src = {
 327         .name           = "sys_clkout2_src",
 328         .ops            = &clkops_omap2_dflt,
 329         .parent         = &func_54m_ck,
 330         .clkdm_name     = "wkup_clkdm",
 331         .enable_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 332         .enable_bit     = OMAP2420_CLKOUT2_EN_SHIFT,
 333         .init           = &omap2_init_clksel_parent,
 334         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 335         .clksel_mask    = OMAP2420_CLKOUT2_SOURCE_MASK,
 336         .clksel         = common_clkout_src_clksel,
 337         .recalc         = &omap2_clksel_recalc,
 338         .round_rate     = &omap2_clksel_round_rate,
 339         .set_rate       = &omap2_clksel_set_rate
 340 };
 341
 342 static const struct clksel sys_clkout2_clksel[] = {
 343         { .parent = &sys_clkout2_src, .rates = common_clkout_rates },
 344         { .parent = NULL }
 345 };
 346
 347 /* In 2430, new in 2420 ES2 */
 348 static struct clk sys_clkout2 = {
 349         .name           = "sys_clkout2",
 350         .ops            = &clkops_null,
 351         .parent         = &sys_clkout2_src,
 352         .clkdm_name     = "wkup_clkdm",
 353         .clksel_reg     = OMAP2420_PRCM_CLKOUT_CTRL,
 354         .clksel_mask    = OMAP2420_CLKOUT2_DIV_MASK,
 355         .clksel         = sys_clkout2_clksel,
 356         .recalc         = &omap2_clksel_recalc,
 357         .round_rate     = &omap2_clksel_round_rate,
 358         .set_rate       = &omap2_clksel_set_rate
 359 };
 360
 361 static struct clk emul_ck = {
 362         .name           = "emul_ck",
 363         .ops            = &clkops_omap2_dflt,
 364         .parent         = &func_54m_ck,
 365         .clkdm_name     = "wkup_clkdm",
 366         .enable_reg     = OMAP2420_PRCM_CLKEMUL_CTRL,
 367         .enable_bit     = OMAP24XX_EMULATION_EN_SHIFT,
 368         .recalc         = &followparent_recalc,
 369
 370 };
 371
 372 /*
 373  * MPU clock domain
 374  *      Clocks:
 375  *              MPU_FCLK, MPU_ICLK
 376  *              INT_M_FCLK, INT_M_I_CLK
 377  *
 378  * - Individual clocks are hardware managed.
 379  * - Base divider comes from: CM_CLKSEL_MPU
 380  *
 381  */
 382 static const struct clksel_rate mpu_core_rates[] = {
 383         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 384         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 385         { .div = 4, .val = 4, .flags = RATE_IN_242X },
 386         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 387         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 388         { .div = 0 },
 389 };
 390
 391 static const struct clksel mpu_clksel[] = {
 392         { .parent = &core_ck, .rates = mpu_core_rates },
 393         { .parent = NULL }
 394 };
 395
 396 static struct clk mpu_ck = {    /* Control cpu */
 397         .name           = "mpu_ck",
 398         .ops            = &clkops_null,
 399         .parent         = &core_ck,
 400         .clkdm_name     = "mpu_clkdm",
 401         .init           = &omap2_init_clksel_parent,
 402         .clksel_reg     = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
 403         .clksel_mask    = OMAP24XX_CLKSEL_MPU_MASK,
 404         .clksel         = mpu_clksel,
 405         .recalc         = &omap2_clksel_recalc,
 406 };
 407
 408 /*
 409  * DSP (2420-UMA+IVA1) clock domain
 410  * Clocks:
 411  *      2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
 412  *
 413  * Won't be too specific here. The core clock comes into this block
 414  * it is divided then tee'ed. One branch goes directly to xyz enable
 415  * controls. The other branch gets further divided by 2 then possibly
 416  * routed into a synchronizer and out of clocks abc.
 417  */
 418 static const struct clksel_rate dsp_fck_core_rates[] = {
 419         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 420         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 421         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 422         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 423         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 424         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 425         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 426         { .div = 0 },
 427 };
 428
 429 static const struct clksel dsp_fck_clksel[] = {
 430         { .parent = &core_ck, .rates = dsp_fck_core_rates },
 431         { .parent = NULL }
 432 };
 433
 434 static struct clk dsp_fck = {
 435         .name           = "dsp_fck",
 436         .ops            = &clkops_omap2_dflt_wait,
 437         .parent         = &core_ck,
 438         .clkdm_name     = "dsp_clkdm",
 439         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 440         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
 441         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 442         .clksel_mask    = OMAP24XX_CLKSEL_DSP_MASK,
 443         .clksel         = dsp_fck_clksel,
 444         .recalc         = &omap2_clksel_recalc,
 445 };
 446
 447 /* DSP interface clock */
 448 static const struct clksel_rate dsp_irate_ick_rates[] = {
 449         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 450         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 451         { .div = 0 },
 452 };
 453
 454 static const struct clksel dsp_irate_ick_clksel[] = {
 455         { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
 456         { .parent = NULL }
 457 };
 458
 459 /* This clock does not exist as such in the TRM. */
 460 static struct clk dsp_irate_ick = {
 461         .name           = "dsp_irate_ick",
 462         .ops            = &clkops_null,
 463         .parent         = &dsp_fck,
 464         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 465         .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
 466         .clksel         = dsp_irate_ick_clksel,
 467         .recalc         = &omap2_clksel_recalc,
 468 };
 469
 470 /* 2420 only */
 471 static struct clk dsp_ick = {
 472         .name           = "dsp_ick",     /* apparently ipi and isp */
 473         .ops            = &clkops_omap2_dflt_wait,
 474         .parent         = &dsp_irate_ick,
 475         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
 476         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
 477 };
 478
 479 /*
 480  * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
 481  * the C54x, but which is contained in the DSP powerdomain.  Does not
 482  * exist on later OMAPs.
 483  */
 484 static struct clk iva1_ifck = {
 485         .name           = "iva1_ifck",
 486         .ops            = &clkops_omap2_dflt_wait,
 487         .parent         = &core_ck,
 488         .clkdm_name     = "iva1_clkdm",
 489         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 490         .enable_bit     = OMAP2420_EN_IVA_COP_SHIFT,
 491         .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
 492         .clksel_mask    = OMAP2420_CLKSEL_IVA_MASK,
 493         .clksel         = dsp_fck_clksel,
 494         .recalc         = &omap2_clksel_recalc,
 495 };
 496
 497 /* IVA1 mpu/int/i/f clocks are /2 of parent */
 498 static struct clk iva1_mpu_int_ifck = {
 499         .name           = "iva1_mpu_int_ifck",
 500         .ops            = &clkops_omap2_dflt_wait,
 501         .parent         = &iva1_ifck,
 502         .clkdm_name     = "iva1_clkdm",
 503         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
 504         .enable_bit     = OMAP2420_EN_IVA_MPU_SHIFT,
 505         .fixed_div      = 2,
 506         .recalc         = &omap_fixed_divisor_recalc,
 507 };
 508
 509 /*
 510  * L3 clock domain
 511  * L3 clocks are used for both interface and functional clocks to
 512  * multiple entities. Some of these clocks are completely managed
 513  * by hardware, and some others allow software control. Hardware
 514  * managed ones general are based on directly CLK_REQ signals and
 515  * various auto idle settings. The functional spec sets many of these
 516  * as 'tie-high' for their enables.
 517  *
 518  * I-CLOCKS:
 519  *      L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 520  *      CAM, HS-USB.
 521  * F-CLOCK
 522  *      SSI.
 523  *
 524  * GPMC memories and SDRC have timing and clock sensitive registers which
 525  * may very well need notification when the clock changes. Currently for low
 526  * operating points, these are taken care of in sleep.S.
 527  */
 528 static const struct clksel_rate core_l3_core_rates[] = {
 529         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 530         { .div = 2, .val = 2, .flags = RATE_IN_242X },
 531         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 532         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 533         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 534         { .div = 12, .val = 12, .flags = RATE_IN_242X },
 535         { .div = 16, .val = 16, .flags = RATE_IN_242X },
 536         { .div = 0 }
 537 };
 538
 539 static const struct clksel core_l3_clksel[] = {
 540         { .parent = &core_ck, .rates = core_l3_core_rates },
 541         { .parent = NULL }
 542 };
 543
 544 static struct clk core_l3_ck = {        /* Used for ick and fck, interconnect */
 545         .name           = "core_l3_ck",
 546         .ops            = &clkops_null,
 547         .parent         = &core_ck,
 548         .clkdm_name     = "core_l3_clkdm",
 549         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 550         .clksel_mask    = OMAP24XX_CLKSEL_L3_MASK,
 551         .clksel         = core_l3_clksel,
 552         .recalc         = &omap2_clksel_recalc,
 553 };
 554
 555 /* usb_l4_ick */
 556 static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
 557         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 558         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 559         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 560         { .div = 0 }
 561 };
 562
 563 static const struct clksel usb_l4_ick_clksel[] = {
 564         { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
 565         { .parent = NULL },
 566 };
 567
 568 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 569 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
 570         .name           = "usb_l4_ick",
 571         .ops            = &clkops_omap2_dflt_wait,
 572         .parent         = &core_l3_ck,
 573         .clkdm_name     = "core_l4_clkdm",
 574         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 575         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
 576         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 577         .clksel_mask    = OMAP24XX_CLKSEL_USB_MASK,
 578         .clksel         = usb_l4_ick_clksel,
 579         .recalc         = &omap2_clksel_recalc,
 580 };
 581
 582 /*
 583  * L4 clock management domain
 584  *
 585  * This domain contains lots of interface clocks from the L4 interface, some
 586  * functional clocks.   Fixed APLL functional source clocks are managed in
 587  * this domain.
 588  */
 589 static const struct clksel_rate l4_core_l3_rates[] = {
 590         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 591         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 592         { .div = 0 }
 593 };
 594
 595 static const struct clksel l4_clksel[] = {
 596         { .parent = &core_l3_ck, .rates = l4_core_l3_rates },
 597         { .parent = NULL }
 598 };
 599
 600 static struct clk l4_ck = {             /* used both as an ick and fck */
 601         .name           = "l4_ck",
 602         .ops            = &clkops_null,
 603         .parent         = &core_l3_ck,
 604         .clkdm_name     = "core_l4_clkdm",
 605         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 606         .clksel_mask    = OMAP24XX_CLKSEL_L4_MASK,
 607         .clksel         = l4_clksel,
 608         .recalc         = &omap2_clksel_recalc,
 609 };
 610
 611 /*
 612  * SSI is in L3 management domain, its direct parent is core not l3,
 613  * many core power domain entities are grouped into the L3 clock
 614  * domain.
 615  * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
 616  *
 617  * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 618  */
 619 static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
 620         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 621         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 622         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 623         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 624         { .div = 6, .val = 6, .flags = RATE_IN_242X },
 625         { .div = 8, .val = 8, .flags = RATE_IN_242X },
 626         { .div = 0 }
 627 };
 628
 629 static const struct clksel ssi_ssr_sst_fck_clksel[] = {
 630         { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
 631         { .parent = NULL }
 632 };
 633
 634 static struct clk ssi_ssr_sst_fck = {
 635         .name           = "ssi_fck",
 636         .ops            = &clkops_omap2_dflt_wait,
 637         .parent         = &core_ck,
 638         .clkdm_name     = "core_l3_clkdm",
 639         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
 640         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 641         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 642         .clksel_mask    = OMAP24XX_CLKSEL_SSI_MASK,
 643         .clksel         = ssi_ssr_sst_fck_clksel,
 644         .recalc         = &omap2_clksel_recalc,
 645 };
 646
 647 /*
 648  * Presumably this is the same as SSI_ICLK.
 649  * TRM contradicts itself on what clockdomain SSI_ICLK is in
 650  */
 651 static struct clk ssi_l4_ick = {
 652         .name           = "ssi_l4_ick",
 653         .ops            = &clkops_omap2_dflt_wait,
 654         .parent         = &l4_ck,
 655         .clkdm_name     = "core_l4_clkdm",
 656         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
 657         .enable_bit     = OMAP24XX_EN_SSI_SHIFT,
 658         .recalc         = &followparent_recalc,
 659 };
 660
 661
 662 /*
 663  * GFX clock domain
 664  *      Clocks:
 665  * GFX_FCLK, GFX_ICLK
 666  * GFX_CG1(2d), GFX_CG2(3d)
 667  *
 668  * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 669  * The 2d and 3d clocks run at a hardware determined
 670  * divided value of fclk.
 671  *
 672  */
 673
 674 /* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
 675 static const struct clksel gfx_fck_clksel[] = {
 676         { .parent = &core_l3_ck, .rates = gfx_l3_rates },
 677         { .parent = NULL },
 678 };
 679
 680 static struct clk gfx_3d_fck = {
 681         .name           = "gfx_3d_fck",
 682         .ops            = &clkops_omap2_dflt_wait,
 683         .parent         = &core_l3_ck,
 684         .clkdm_name     = "gfx_clkdm",
 685         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 686         .enable_bit     = OMAP24XX_EN_3D_SHIFT,
 687         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 688         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 689         .clksel         = gfx_fck_clksel,
 690         .recalc         = &omap2_clksel_recalc,
 691         .round_rate     = &omap2_clksel_round_rate,
 692         .set_rate       = &omap2_clksel_set_rate
 693 };
 694
 695 static struct clk gfx_2d_fck = {
 696         .name           = "gfx_2d_fck",
 697         .ops            = &clkops_omap2_dflt_wait,
 698         .parent         = &core_l3_ck,
 699         .clkdm_name     = "gfx_clkdm",
 700         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
 701         .enable_bit     = OMAP24XX_EN_2D_SHIFT,
 702         .clksel_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
 703         .clksel_mask    = OMAP_CLKSEL_GFX_MASK,
 704         .clksel         = gfx_fck_clksel,
 705         .recalc         = &omap2_clksel_recalc,
 706 };
 707
 708 static struct clk gfx_ick = {
 709         .name           = "gfx_ick",            /* From l3 */
 710         .ops            = &clkops_omap2_dflt_wait,
 711         .parent         = &core_l3_ck,
 712         .clkdm_name     = "gfx_clkdm",
 713         .enable_reg     = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
 714         .enable_bit     = OMAP_EN_GFX_SHIFT,
 715         .recalc         = &followparent_recalc,
 716 };
 717
 718 /*
 719  * DSS clock domain
 720  * CLOCKs:
 721  * DSS_L4_ICLK, DSS_L3_ICLK,
 722  * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
 723  *
 724  * DSS is both initiator and target.
 725  */
 726
 727 static const struct clksel_rate dss1_fck_sys_rates[] = {
 728         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 729         { .div = 0 }
 730 };
 731
 732 static const struct clksel_rate dss1_fck_core_rates[] = {
 733         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 734         { .div = 2, .val = 2, .flags = RATE_IN_24XX },
 735         { .div = 3, .val = 3, .flags = RATE_IN_24XX },
 736         { .div = 4, .val = 4, .flags = RATE_IN_24XX },
 737         { .div = 5, .val = 5, .flags = RATE_IN_24XX },
 738         { .div = 6, .val = 6, .flags = RATE_IN_24XX },
 739         { .div = 8, .val = 8, .flags = RATE_IN_24XX },
 740         { .div = 9, .val = 9, .flags = RATE_IN_24XX },
 741         { .div = 12, .val = 12, .flags = RATE_IN_24XX },
 742         { .div = 16, .val = 16, .flags = RATE_IN_24XX },
 743         { .div = 0 }
 744 };
 745
 746 static const struct clksel dss1_fck_clksel[] = {
 747         { .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
 748         { .parent = &core_ck, .rates = dss1_fck_core_rates },
 749         { .parent = NULL },
 750 };
 751
 752 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
 753         .name           = "dss_ick",
 754         .ops            = &clkops_omap2_dflt,
 755         .parent         = &l4_ck,       /* really both l3 and l4 */
 756         .clkdm_name     = "dss_clkdm",
 757         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 758         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 759         .recalc         = &followparent_recalc,
 760 };
 761
 762 static struct clk dss1_fck = {
 763         .name           = "dss1_fck",
 764         .ops            = &clkops_omap2_dflt,
 765         .parent         = &core_ck,             /* Core or sys */
 766         .clkdm_name     = "dss_clkdm",
 767         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 768         .enable_bit     = OMAP24XX_EN_DSS1_SHIFT,
 769         .init           = &omap2_init_clksel_parent,
 770         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 771         .clksel_mask    = OMAP24XX_CLKSEL_DSS1_MASK,
 772         .clksel         = dss1_fck_clksel,
 773         .recalc         = &omap2_clksel_recalc,
 774 };
 775
 776 static const struct clksel_rate dss2_fck_sys_rates[] = {
 777         { .div = 1, .val = 0, .flags = RATE_IN_24XX },
 778         { .div = 0 }
 779 };
 780
 781 static const struct clksel_rate dss2_fck_48m_rates[] = {
 782         { .div = 1, .val = 1, .flags = RATE_IN_24XX },
 783         { .div = 0 }
 784 };
 785
 786 static const struct clksel dss2_fck_clksel[] = {
 787         { .parent = &sys_ck,      .rates = dss2_fck_sys_rates },
 788         { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
 789         { .parent = NULL }
 790 };
 791
 792 static struct clk dss2_fck = {          /* Alt clk used in power management */
 793         .name           = "dss2_fck",
 794         .ops            = &clkops_omap2_dflt,
 795         .parent         = &sys_ck,              /* fixed at sys_ck or 48MHz */
 796         .clkdm_name     = "dss_clkdm",
 797         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 798         .enable_bit     = OMAP24XX_EN_DSS2_SHIFT,
 799         .init           = &omap2_init_clksel_parent,
 800         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
 801         .clksel_mask    = OMAP24XX_CLKSEL_DSS2_MASK,
 802         .clksel         = dss2_fck_clksel,
 803         .recalc         = &followparent_recalc,
 804 };
 805
 806 static struct clk dss_54m_fck = {       /* Alt clk used in power management */
 807         .name           = "dss_54m_fck",        /* 54m tv clk */
 808         .ops            = &clkops_omap2_dflt_wait,
 809         .parent         = &func_54m_ck,
 810         .clkdm_name     = "dss_clkdm",
 811         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 812         .enable_bit     = OMAP24XX_EN_TV_SHIFT,
 813         .recalc         = &followparent_recalc,
 814 };
 815
 816 /*
 817  * CORE power domain ICLK & FCLK defines.
 818  * Many of the these can have more than one possible parent. Entries
 819  * here will likely have an L4 interface parent, and may have multiple
 820  * functional clock parents.
 821  */
 822 static const struct clksel_rate gpt_alt_rates[] = {
 823         { .div = 1, .val = 2, .flags = RATE_IN_24XX },
 824         { .div = 0 }
 825 };
 826
 827 static const struct clksel omap24xx_gpt_clksel[] = {
 828         { .parent = &func_32k_ck, .rates = gpt_32k_rates },
 829         { .parent = &sys_ck,      .rates = gpt_sys_rates },
 830         { .parent = &alt_ck,      .rates = gpt_alt_rates },
 831         { .parent = NULL },
 832 };
 833
 834 static struct clk gpt1_ick = {
 835         .name           = "gpt1_ick",
 836         .ops            = &clkops_omap2_dflt_wait,
 837         .parent         = &l4_ck,
 838         .clkdm_name     = "core_l4_clkdm",
 839         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
 840         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 841         .recalc         = &followparent_recalc,
 842 };
 843
 844 static struct clk gpt1_fck = {
 845         .name           = "gpt1_fck",
 846         .ops            = &clkops_omap2_dflt_wait,
 847         .parent         = &func_32k_ck,
 848         .clkdm_name     = "core_l4_clkdm",
 849         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
 850         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
 851         .init           = &omap2_init_clksel_parent,
 852         .clksel_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
 853         .clksel_mask    = OMAP24XX_CLKSEL_GPT1_MASK,
 854         .clksel         = omap24xx_gpt_clksel,
 855         .recalc         = &omap2_clksel_recalc,
 856         .round_rate     = &omap2_clksel_round_rate,
 857         .set_rate       = &omap2_clksel_set_rate
 858 };
 859
 860 static struct clk gpt2_ick = {
 861         .name           = "gpt2_ick",
 862         .ops            = &clkops_omap2_dflt_wait,
 863         .parent         = &l4_ck,
 864         .clkdm_name     = "core_l4_clkdm",
 865         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 866         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 867         .recalc         = &followparent_recalc,
 868 };
 869
 870 static struct clk gpt2_fck = {
 871         .name           = "gpt2_fck",
 872         .ops            = &clkops_omap2_dflt_wait,
 873         .parent         = &func_32k_ck,
 874         .clkdm_name     = "core_l4_clkdm",
 875         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 876         .enable_bit     = OMAP24XX_EN_GPT2_SHIFT,
 877         .init           = &omap2_init_clksel_parent,
 878         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 879         .clksel_mask    = OMAP24XX_CLKSEL_GPT2_MASK,
 880         .clksel         = omap24xx_gpt_clksel,
 881         .recalc         = &omap2_clksel_recalc,
 882 };
 883
 884 static struct clk gpt3_ick = {
 885         .name           = "gpt3_ick",
 886         .ops            = &clkops_omap2_dflt_wait,
 887         .parent         = &l4_ck,
 888         .clkdm_name     = "core_l4_clkdm",
 889         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 890         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 891         .recalc         = &followparent_recalc,
 892 };
 893
 894 static struct clk gpt3_fck = {
 895         .name           = "gpt3_fck",
 896         .ops            = &clkops_omap2_dflt_wait,
 897         .parent         = &func_32k_ck,
 898         .clkdm_name     = "core_l4_clkdm",
 899         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 900         .enable_bit     = OMAP24XX_EN_GPT3_SHIFT,
 901         .init           = &omap2_init_clksel_parent,
 902         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 903         .clksel_mask    = OMAP24XX_CLKSEL_GPT3_MASK,
 904         .clksel         = omap24xx_gpt_clksel,
 905         .recalc         = &omap2_clksel_recalc,
 906 };
 907
 908 static struct clk gpt4_ick = {
 909         .name           = "gpt4_ick",
 910         .ops            = &clkops_omap2_dflt_wait,
 911         .parent         = &l4_ck,
 912         .clkdm_name     = "core_l4_clkdm",
 913         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 914         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 915         .recalc         = &followparent_recalc,
 916 };
 917
 918 static struct clk gpt4_fck = {
 919         .name           = "gpt4_fck",
 920         .ops            = &clkops_omap2_dflt_wait,
 921         .parent         = &func_32k_ck,
 922         .clkdm_name     = "core_l4_clkdm",
 923         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 924         .enable_bit     = OMAP24XX_EN_GPT4_SHIFT,
 925         .init           = &omap2_init_clksel_parent,
 926         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 927         .clksel_mask    = OMAP24XX_CLKSEL_GPT4_MASK,
 928         .clksel         = omap24xx_gpt_clksel,
 929         .recalc         = &omap2_clksel_recalc,
 930 };
 931
 932 static struct clk gpt5_ick = {
 933         .name           = "gpt5_ick",
 934         .ops            = &clkops_omap2_dflt_wait,
 935         .parent         = &l4_ck,
 936         .clkdm_name     = "core_l4_clkdm",
 937         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 938         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 939         .recalc         = &followparent_recalc,
 940 };
 941
 942 static struct clk gpt5_fck = {
 943         .name           = "gpt5_fck",
 944         .ops            = &clkops_omap2_dflt_wait,
 945         .parent         = &func_32k_ck,
 946         .clkdm_name     = "core_l4_clkdm",
 947         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 948         .enable_bit     = OMAP24XX_EN_GPT5_SHIFT,
 949         .init           = &omap2_init_clksel_parent,
 950         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 951         .clksel_mask    = OMAP24XX_CLKSEL_GPT5_MASK,
 952         .clksel         = omap24xx_gpt_clksel,
 953         .recalc         = &omap2_clksel_recalc,
 954 };
 955
 956 static struct clk gpt6_ick = {
 957         .name           = "gpt6_ick",
 958         .ops            = &clkops_omap2_dflt_wait,
 959         .parent         = &l4_ck,
 960         .clkdm_name     = "core_l4_clkdm",
 961         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 962         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 963         .recalc         = &followparent_recalc,
 964 };
 965
 966 static struct clk gpt6_fck = {
 967         .name           = "gpt6_fck",
 968         .ops            = &clkops_omap2_dflt_wait,
 969         .parent         = &func_32k_ck,
 970         .clkdm_name     = "core_l4_clkdm",
 971         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 972         .enable_bit     = OMAP24XX_EN_GPT6_SHIFT,
 973         .init           = &omap2_init_clksel_parent,
 974         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 975         .clksel_mask    = OMAP24XX_CLKSEL_GPT6_MASK,
 976         .clksel         = omap24xx_gpt_clksel,
 977         .recalc         = &omap2_clksel_recalc,
 978 };
 979
 980 static struct clk gpt7_ick = {
 981         .name           = "gpt7_ick",
 982         .ops            = &clkops_omap2_dflt_wait,
 983         .parent         = &l4_ck,
 984         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
 985         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 986         .recalc         = &followparent_recalc,
 987 };
 988
 989 static struct clk gpt7_fck = {
 990         .name           = "gpt7_fck",
 991         .ops            = &clkops_omap2_dflt_wait,
 992         .parent         = &func_32k_ck,
 993         .clkdm_name     = "core_l4_clkdm",
 994         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 995         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
 996         .init           = &omap2_init_clksel_parent,
 997         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
 998         .clksel_mask    = OMAP24XX_CLKSEL_GPT7_MASK,
 999         .clksel         = omap24xx_gpt_clksel,
1000         .recalc         = &omap2_clksel_recalc,
1001 };
1002
1003 static struct clk gpt8_ick = {
1004         .name           = "gpt8_ick",
1005         .ops            = &clkops_omap2_dflt_wait,
1006         .parent         = &l4_ck,
1007         .clkdm_name     = "core_l4_clkdm",
1008         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1009         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1010         .recalc         = &followparent_recalc,
1011 };
1012
1013 static struct clk gpt8_fck = {
1014         .name           = "gpt8_fck",
1015         .ops            = &clkops_omap2_dflt_wait,
1016         .parent         = &func_32k_ck,
1017         .clkdm_name     = "core_l4_clkdm",
1018         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1019         .enable_bit     = OMAP24XX_EN_GPT8_SHIFT,
1020         .init           = &omap2_init_clksel_parent,
1021         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1022         .clksel_mask    = OMAP24XX_CLKSEL_GPT8_MASK,
1023         .clksel         = omap24xx_gpt_clksel,
1024         .recalc         = &omap2_clksel_recalc,
1025 };
1026
1027 static struct clk gpt9_ick = {
1028         .name           = "gpt9_ick",
1029         .ops            = &clkops_omap2_dflt_wait,
1030         .parent         = &l4_ck,
1031         .clkdm_name     = "core_l4_clkdm",
1032         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1033         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1034         .recalc         = &followparent_recalc,
1035 };
1036
1037 static struct clk gpt9_fck = {
1038         .name           = "gpt9_fck",
1039         .ops            = &clkops_omap2_dflt_wait,
1040         .parent         = &func_32k_ck,
1041         .clkdm_name     = "core_l4_clkdm",
1042         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1043         .enable_bit     = OMAP24XX_EN_GPT9_SHIFT,
1044         .init           = &omap2_init_clksel_parent,
1045         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1046         .clksel_mask    = OMAP24XX_CLKSEL_GPT9_MASK,
1047         .clksel         = omap24xx_gpt_clksel,
1048         .recalc         = &omap2_clksel_recalc,
1049 };
1050
1051 static struct clk gpt10_ick = {
1052         .name           = "gpt10_ick",
1053         .ops            = &clkops_omap2_dflt_wait,
1054         .parent         = &l4_ck,
1055         .clkdm_name     = "core_l4_clkdm",
1056         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1057         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1058         .recalc         = &followparent_recalc,
1059 };
1060
1061 static struct clk gpt10_fck = {
1062         .name           = "gpt10_fck",
1063         .ops            = &clkops_omap2_dflt_wait,
1064         .parent         = &func_32k_ck,
1065         .clkdm_name     = "core_l4_clkdm",
1066         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1067         .enable_bit     = OMAP24XX_EN_GPT10_SHIFT,
1068         .init           = &omap2_init_clksel_parent,
1069         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1070         .clksel_mask    = OMAP24XX_CLKSEL_GPT10_MASK,
1071         .clksel         = omap24xx_gpt_clksel,
1072         .recalc         = &omap2_clksel_recalc,
1073 };
1074
1075 static struct clk gpt11_ick = {
1076         .name           = "gpt11_ick",
1077         .ops            = &clkops_omap2_dflt_wait,
1078         .parent         = &l4_ck,
1079         .clkdm_name     = "core_l4_clkdm",
1080         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1081         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1082         .recalc         = &followparent_recalc,
1083 };
1084
1085 static struct clk gpt11_fck = {
1086         .name           = "gpt11_fck",
1087         .ops            = &clkops_omap2_dflt_wait,
1088         .parent         = &func_32k_ck,
1089         .clkdm_name     = "core_l4_clkdm",
1090         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1091         .enable_bit     = OMAP24XX_EN_GPT11_SHIFT,
1092         .init           = &omap2_init_clksel_parent,
1093         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1094         .clksel_mask    = OMAP24XX_CLKSEL_GPT11_MASK,
1095         .clksel         = omap24xx_gpt_clksel,
1096         .recalc         = &omap2_clksel_recalc,
1097 };
1098
1099 static struct clk gpt12_ick = {
1100         .name           = "gpt12_ick",
1101         .ops            = &clkops_omap2_dflt_wait,
1102         .parent         = &l4_ck,
1103         .clkdm_name     = "core_l4_clkdm",
1104         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1105         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1106         .recalc         = &followparent_recalc,
1107 };
1108
1109 static struct clk gpt12_fck = {
1110         .name           = "gpt12_fck",
1111         .ops            = &clkops_omap2_dflt_wait,
1112         .parent         = &secure_32k_ck,
1113         .clkdm_name     = "core_l4_clkdm",
1114         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1115         .enable_bit     = OMAP24XX_EN_GPT12_SHIFT,
1116         .init           = &omap2_init_clksel_parent,
1117         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
1118         .clksel_mask    = OMAP24XX_CLKSEL_GPT12_MASK,
1119         .clksel         = omap24xx_gpt_clksel,
1120         .recalc         = &omap2_clksel_recalc,
1121 };
1122
1123 static struct clk mcbsp1_ick = {
1124         .name           = "mcbsp1_ick",
1125         .ops            = &clkops_omap2_dflt_wait,
1126         .parent         = &l4_ck,
1127         .clkdm_name     = "core_l4_clkdm",
1128         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1129         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1130         .recalc         = &followparent_recalc,
1131 };
1132
1133 static struct clk mcbsp1_fck = {
1134         .name           = "mcbsp1_fck",
1135         .ops            = &clkops_omap2_dflt_wait,
1136         .parent         = &func_96m_ck,
1137         .clkdm_name     = "core_l4_clkdm",
1138         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1139         .enable_bit     = OMAP24XX_EN_MCBSP1_SHIFT,
1140         .recalc         = &followparent_recalc,
1141 };
1142
1143 static struct clk mcbsp2_ick = {
1144         .name           = "mcbsp2_ick",
1145         .ops            = &clkops_omap2_dflt_wait,
1146         .parent         = &l4_ck,
1147         .clkdm_name     = "core_l4_clkdm",
1148         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1149         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1150         .recalc         = &followparent_recalc,
1151 };
1152
1153 static struct clk mcbsp2_fck = {
1154         .name           = "mcbsp2_fck",
1155         .ops            = &clkops_omap2_dflt_wait,
1156         .parent         = &func_96m_ck,
1157         .clkdm_name     = "core_l4_clkdm",
1158         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1159         .enable_bit     = OMAP24XX_EN_MCBSP2_SHIFT,
1160         .recalc         = &followparent_recalc,
1161 };
1162
1163 static struct clk mcspi1_ick = {
1164         .name           = "mcspi1_ick",
1165         .ops            = &clkops_omap2_dflt_wait,
1166         .parent         = &l4_ck,
1167         .clkdm_name     = "core_l4_clkdm",
1168         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1169         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1170         .recalc         = &followparent_recalc,
1171 };
1172
1173 static struct clk mcspi1_fck = {
1174         .name           = "mcspi1_fck",
1175         .ops            = &clkops_omap2_dflt_wait,
1176         .parent         = &func_48m_ck,
1177         .clkdm_name     = "core_l4_clkdm",
1178         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1179         .enable_bit     = OMAP24XX_EN_MCSPI1_SHIFT,
1180         .recalc         = &followparent_recalc,
1181 };
1182
1183 static struct clk mcspi2_ick = {
1184         .name           = "mcspi2_ick",
1185         .ops            = &clkops_omap2_dflt_wait,
1186         .parent         = &l4_ck,
1187         .clkdm_name     = "core_l4_clkdm",
1188         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1189         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1190         .recalc         = &followparent_recalc,
1191 };
1192
1193 static struct clk mcspi2_fck = {
1194         .name           = "mcspi2_fck",
1195         .ops            = &clkops_omap2_dflt_wait,
1196         .parent         = &func_48m_ck,
1197         .clkdm_name     = "core_l4_clkdm",
1198         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1199         .enable_bit     = OMAP24XX_EN_MCSPI2_SHIFT,
1200         .recalc         = &followparent_recalc,
1201 };
1202
1203 static struct clk uart1_ick = {
1204         .name           = "uart1_ick",
1205         .ops            = &clkops_omap2_dflt_wait,
1206         .parent         = &l4_ck,
1207         .clkdm_name     = "core_l4_clkdm",
1208         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1209         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1210         .recalc         = &followparent_recalc,
1211 };
1212
1213 static struct clk uart1_fck = {
1214         .name           = "uart1_fck",
1215         .ops            = &clkops_omap2_dflt_wait,
1216         .parent         = &func_48m_ck,
1217         .clkdm_name     = "core_l4_clkdm",
1218         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1219         .enable_bit     = OMAP24XX_EN_UART1_SHIFT,
1220         .recalc         = &followparent_recalc,
1221 };
1222
1223 static struct clk uart2_ick = {
1224         .name           = "uart2_ick",
1225         .ops            = &clkops_omap2_dflt_wait,
1226         .parent         = &l4_ck,
1227         .clkdm_name     = "core_l4_clkdm",
1228         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1229         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1230         .recalc         = &followparent_recalc,
1231 };
1232
1233 static struct clk uart2_fck = {
1234         .name           = "uart2_fck",
1235         .ops            = &clkops_omap2_dflt_wait,
1236         .parent         = &func_48m_ck,
1237         .clkdm_name     = "core_l4_clkdm",
1238         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1239         .enable_bit     = OMAP24XX_EN_UART2_SHIFT,
1240         .recalc         = &followparent_recalc,
1241 };
1242
1243 static struct clk uart3_ick = {
1244         .name           = "uart3_ick",
1245         .ops            = &clkops_omap2_dflt_wait,
1246         .parent         = &l4_ck,
1247         .clkdm_name     = "core_l4_clkdm",
1248         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1249         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1250         .recalc         = &followparent_recalc,
1251 };
1252
1253 static struct clk uart3_fck = {
1254         .name           = "uart3_fck",
1255         .ops            = &clkops_omap2_dflt_wait,
1256         .parent         = &func_48m_ck,
1257         .clkdm_name     = "core_l4_clkdm",
1258         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1259         .enable_bit     = OMAP24XX_EN_UART3_SHIFT,
1260         .recalc         = &followparent_recalc,
1261 };
1262
1263 static struct clk gpios_ick = {
1264         .name           = "gpios_ick",
1265         .ops            = &clkops_omap2_dflt_wait,
1266         .parent         = &l4_ck,
1267         .clkdm_name     = "core_l4_clkdm",
1268         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1269         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1270         .recalc         = &followparent_recalc,
1271 };
1272
1273 static struct clk gpios_fck = {
1274         .name           = "gpios_fck",
1275         .ops            = &clkops_omap2_dflt_wait,
1276         .parent         = &func_32k_ck,
1277         .clkdm_name     = "wkup_clkdm",
1278         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1279         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
1280         .recalc         = &followparent_recalc,
1281 };
1282
1283 static struct clk mpu_wdt_ick = {
1284         .name           = "mpu_wdt_ick",
1285         .ops            = &clkops_omap2_dflt_wait,
1286         .parent         = &l4_ck,
1287         .clkdm_name     = "core_l4_clkdm",
1288         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1289         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1290         .recalc         = &followparent_recalc,
1291 };
1292
1293 static struct clk mpu_wdt_fck = {
1294         .name           = "mpu_wdt_fck",
1295         .ops            = &clkops_omap2_dflt_wait,
1296         .parent         = &func_32k_ck,
1297         .clkdm_name     = "wkup_clkdm",
1298         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1299         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
1300         .recalc         = &followparent_recalc,
1301 };
1302
1303 static struct clk sync_32k_ick = {
1304         .name           = "sync_32k_ick",
1305         .ops            = &clkops_omap2_dflt_wait,
1306         .parent         = &l4_ck,
1307         .flags          = ENABLE_ON_INIT,
1308         .clkdm_name     = "core_l4_clkdm",
1309         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1310         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
1311         .recalc         = &followparent_recalc,
1312 };
1313
1314 static struct clk wdt1_ick = {
1315         .name           = "wdt1_ick",
1316         .ops            = &clkops_omap2_dflt_wait,
1317         .parent         = &l4_ck,
1318         .clkdm_name     = "core_l4_clkdm",
1319         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1320         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
1321         .recalc         = &followparent_recalc,
1322 };
1323
1324 static struct clk omapctrl_ick = {
1325         .name           = "omapctrl_ick",
1326         .ops            = &clkops_omap2_dflt_wait,
1327         .parent         = &l4_ck,
1328         .flags          = ENABLE_ON_INIT,
1329         .clkdm_name     = "core_l4_clkdm",
1330         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1331         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
1332         .recalc         = &followparent_recalc,
1333 };
1334
1335 static struct clk cam_ick = {
1336         .name           = "cam_ick",
1337         .ops            = &clkops_omap2_dflt,
1338         .parent         = &l4_ck,
1339         .clkdm_name     = "core_l4_clkdm",
1340         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1341         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1342         .recalc         = &followparent_recalc,
1343 };
1344
1345 /*
1346  * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
1347  * split into two separate clocks, since the parent clocks are different
1348  * and the clockdomains are also different.
1349  */
1350 static struct clk cam_fck = {
1351         .name           = "cam_fck",
1352         .ops            = &clkops_omap2_dflt,
1353         .parent         = &func_96m_ck,
1354         .clkdm_name     = "core_l3_clkdm",
1355         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1356         .enable_bit     = OMAP24XX_EN_CAM_SHIFT,
1357         .recalc         = &followparent_recalc,
1358 };
1359
1360 static struct clk mailboxes_ick = {
1361         .name           = "mailboxes_ick",
1362         .ops            = &clkops_omap2_dflt_wait,
1363         .parent         = &l4_ck,
1364         .clkdm_name     = "core_l4_clkdm",
1365         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1366         .enable_bit     = OMAP24XX_EN_MAILBOXES_SHIFT,
1367         .recalc         = &followparent_recalc,
1368 };
1369
1370 static struct clk wdt4_ick = {
1371         .name           = "wdt4_ick",
1372         .ops            = &clkops_omap2_dflt_wait,
1373         .parent         = &l4_ck,
1374         .clkdm_name     = "core_l4_clkdm",
1375         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1376         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1377         .recalc         = &followparent_recalc,
1378 };
1379
1380 static struct clk wdt4_fck = {
1381         .name           = "wdt4_fck",
1382         .ops            = &clkops_omap2_dflt_wait,
1383         .parent         = &func_32k_ck,
1384         .clkdm_name     = "core_l4_clkdm",
1385         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1386         .enable_bit     = OMAP24XX_EN_WDT4_SHIFT,
1387         .recalc         = &followparent_recalc,
1388 };
1389
1390 static struct clk wdt3_ick = {
1391         .name           = "wdt3_ick",
1392         .ops            = &clkops_omap2_dflt_wait,
1393         .parent         = &l4_ck,
1394         .clkdm_name     = "core_l4_clkdm",
1395         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1396         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1397         .recalc         = &followparent_recalc,
1398 };
1399
1400 static struct clk wdt3_fck = {
1401         .name           = "wdt3_fck",
1402         .ops            = &clkops_omap2_dflt_wait,
1403         .parent         = &func_32k_ck,
1404         .clkdm_name     = "core_l4_clkdm",
1405         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1406         .enable_bit     = OMAP2420_EN_WDT3_SHIFT,
1407         .recalc         = &followparent_recalc,
1408 };
1409
1410 static struct clk mspro_ick = {
1411         .name           = "mspro_ick",
1412         .ops            = &clkops_omap2_dflt_wait,
1413         .parent         = &l4_ck,
1414         .clkdm_name     = "core_l4_clkdm",
1415         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1416         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1417         .recalc         = &followparent_recalc,
1418 };
1419
1420 static struct clk mspro_fck = {
1421         .name           = "mspro_fck",
1422         .ops            = &clkops_omap2_dflt_wait,
1423         .parent         = &func_96m_ck,
1424         .clkdm_name     = "core_l4_clkdm",
1425         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1426         .enable_bit     = OMAP24XX_EN_MSPRO_SHIFT,
1427         .recalc         = &followparent_recalc,
1428 };
1429
1430 static struct clk mmc_ick = {
1431         .name           = "mmc_ick",
1432         .ops            = &clkops_omap2_dflt_wait,
1433         .parent         = &l4_ck,
1434         .clkdm_name     = "core_l4_clkdm",
1435         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1436         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1437         .recalc         = &followparent_recalc,
1438 };
1439
1440 static struct clk mmc_fck = {
1441         .name           = "mmc_fck",
1442         .ops            = &clkops_omap2_dflt_wait,
1443         .parent         = &func_96m_ck,
1444         .clkdm_name     = "core_l4_clkdm",
1445         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1446         .enable_bit     = OMAP2420_EN_MMC_SHIFT,
1447         .recalc         = &followparent_recalc,
1448 };
1449
1450 static struct clk fac_ick = {
1451         .name           = "fac_ick",
1452         .ops            = &clkops_omap2_dflt_wait,
1453         .parent         = &l4_ck,
1454         .clkdm_name     = "core_l4_clkdm",
1455         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1456         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1457         .recalc         = &followparent_recalc,
1458 };
1459
1460 static struct clk fac_fck = {
1461         .name           = "fac_fck",
1462         .ops            = &clkops_omap2_dflt_wait,
1463         .parent         = &func_12m_ck,
1464         .clkdm_name     = "core_l4_clkdm",
1465         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1466         .enable_bit     = OMAP24XX_EN_FAC_SHIFT,
1467         .recalc         = &followparent_recalc,
1468 };
1469
1470 static struct clk eac_ick = {
1471         .name           = "eac_ick",
1472         .ops            = &clkops_omap2_dflt_wait,
1473         .parent         = &l4_ck,
1474         .clkdm_name     = "core_l4_clkdm",
1475         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1476         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1477         .recalc         = &followparent_recalc,
1478 };
1479
1480 static struct clk eac_fck = {
1481         .name           = "eac_fck",
1482         .ops            = &clkops_omap2_dflt_wait,
1483         .parent         = &func_96m_ck,
1484         .clkdm_name     = "core_l4_clkdm",
1485         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1486         .enable_bit     = OMAP2420_EN_EAC_SHIFT,
1487         .recalc         = &followparent_recalc,
1488 };
1489
1490 static struct clk hdq_ick = {
1491         .name           = "hdq_ick",
1492         .ops            = &clkops_omap2_dflt_wait,
1493         .parent         = &l4_ck,
1494         .clkdm_name     = "core_l4_clkdm",
1495         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1496         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1497         .recalc         = &followparent_recalc,
1498 };
1499
1500 static struct clk hdq_fck = {
1501         .name           = "hdq_fck",
1502         .ops            = &clkops_omap2_dflt_wait,
1503         .parent         = &func_12m_ck,
1504         .clkdm_name     = "core_l4_clkdm",
1505         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1506         .enable_bit     = OMAP24XX_EN_HDQ_SHIFT,
1507         .recalc         = &followparent_recalc,
1508 };
1509
1510 static struct clk i2c2_ick = {
1511         .name           = "i2c2_ick",
1512         .ops            = &clkops_omap2_dflt_wait,
1513         .parent         = &l4_ck,
1514         .clkdm_name     = "core_l4_clkdm",
1515         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1516         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1517         .recalc         = &followparent_recalc,
1518 };
1519
1520 static struct clk i2c2_fck = {
1521         .name           = "i2c2_fck",
1522         .ops            = &clkops_omap2_dflt_wait,
1523         .parent         = &func_12m_ck,
1524         .clkdm_name     = "core_l4_clkdm",
1525         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1526         .enable_bit     = OMAP2420_EN_I2C2_SHIFT,
1527         .recalc         = &followparent_recalc,
1528 };
1529
1530 static struct clk i2c1_ick = {
1531         .name           = "i2c1_ick",
1532         .ops            = &clkops_omap2_dflt_wait,
1533         .parent         = &l4_ck,
1534         .clkdm_name     = "core_l4_clkdm",
1535         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1536         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1537         .recalc         = &followparent_recalc,
1538 };
1539
1540 static struct clk i2c1_fck = {
1541         .name           = "i2c1_fck",
1542         .ops            = &clkops_omap2_dflt_wait,
1543         .parent         = &func_12m_ck,
1544         .clkdm_name     = "core_l4_clkdm",
1545         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1546         .enable_bit     = OMAP2420_EN_I2C1_SHIFT,
1547         .recalc         = &followparent_recalc,
1548 };
1549
1550 static struct clk gpmc_fck = {
1551         .name           = "gpmc_fck",
1552         .ops            = &clkops_null, /* RMK: missing? */
1553         .parent         = &core_l3_ck,
1554         .flags          = ENABLE_ON_INIT,
1555         .clkdm_name     = "core_l3_clkdm",
1556         .recalc         = &followparent_recalc,
1557 };
1558
1559 static struct clk sdma_fck = {
1560         .name           = "sdma_fck",
1561         .ops            = &clkops_null, /* RMK: missing? */
1562         .parent         = &core_l3_ck,
1563         .clkdm_name     = "core_l3_clkdm",
1564         .recalc         = &followparent_recalc,
1565 };
1566
1567 static struct clk sdma_ick = {
1568         .name           = "sdma_ick",
1569         .ops            = &clkops_null, /* RMK: missing? */
1570         .parent         = &l4_ck,
1571         .clkdm_name     = "core_l3_clkdm",
1572         .recalc         = &followparent_recalc,
1573 };
1574
1575 static struct clk vlynq_ick = {
1576         .name           = "vlynq_ick",
1577         .ops            = &clkops_omap2_dflt_wait,
1578         .parent         = &core_l3_ck,
1579         .clkdm_name     = "core_l3_clkdm",
1580         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1581         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1582         .recalc         = &followparent_recalc,
1583 };
1584
1585 static const struct clksel_rate vlynq_fck_96m_rates[] = {
1586         { .div = 1, .val = 0, .flags = RATE_IN_242X },
1587         { .div = 0 }
1588 };
1589
1590 static const struct clksel_rate vlynq_fck_core_rates[] = {
1591         { .div = 1, .val = 1, .flags = RATE_IN_242X },
1592         { .div = 2, .val = 2, .flags = RATE_IN_242X },
1593         { .div = 3, .val = 3, .flags = RATE_IN_242X },
1594         { .div = 4, .val = 4, .flags = RATE_IN_242X },
1595         { .div = 6, .val = 6, .flags = RATE_IN_242X },
1596         { .div = 8, .val = 8, .flags = RATE_IN_242X },
1597         { .div = 9, .val = 9, .flags = RATE_IN_242X },
1598         { .div = 12, .val = 12, .flags = RATE_IN_242X },
1599         { .div = 16, .val = 16, .flags = RATE_IN_242X },
1600         { .div = 18, .val = 18, .flags = RATE_IN_242X },
1601         { .div = 0 }
1602 };
1603
1604 static const struct clksel vlynq_fck_clksel[] = {
1605         { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1606         { .parent = &core_ck,     .rates = vlynq_fck_core_rates },
1607         { .parent = NULL }
1608 };
1609
1610 static struct clk vlynq_fck = {
1611         .name           = "vlynq_fck",
1612         .ops            = &clkops_omap2_dflt_wait,
1613         .parent         = &func_96m_ck,
1614         .clkdm_name     = "core_l3_clkdm",
1615         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1616         .enable_bit     = OMAP2420_EN_VLYNQ_SHIFT,
1617         .init           = &omap2_init_clksel_parent,
1618         .clksel_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1619         .clksel_mask    = OMAP2420_CLKSEL_VLYNQ_MASK,
1620         .clksel         = vlynq_fck_clksel,
1621         .recalc         = &omap2_clksel_recalc,
1622 };
1623
1624 static struct clk des_ick = {
1625         .name           = "des_ick",
1626         .ops            = &clkops_omap2_dflt_wait,
1627         .parent         = &l4_ck,
1628         .clkdm_name     = "core_l4_clkdm",
1629         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1630         .enable_bit     = OMAP24XX_EN_DES_SHIFT,
1631         .recalc         = &followparent_recalc,
1632 };
1633
1634 static struct clk sha_ick = {
1635         .name           = "sha_ick",
1636         .ops            = &clkops_omap2_dflt_wait,
1637         .parent         = &l4_ck,
1638         .clkdm_name     = "core_l4_clkdm",
1639         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1640         .enable_bit     = OMAP24XX_EN_SHA_SHIFT,
1641         .recalc         = &followparent_recalc,
1642 };
1643
1644 static struct clk rng_ick = {
1645         .name           = "rng_ick",
1646         .ops            = &clkops_omap2_dflt_wait,
1647         .parent         = &l4_ck,
1648         .clkdm_name     = "core_l4_clkdm",
1649         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1650         .enable_bit     = OMAP24XX_EN_RNG_SHIFT,
1651         .recalc         = &followparent_recalc,
1652 };
1653
1654 static struct clk aes_ick = {
1655         .name           = "aes_ick",
1656         .ops            = &clkops_omap2_dflt_wait,
1657         .parent         = &l4_ck,
1658         .clkdm_name     = "core_l4_clkdm",
1659         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1660         .enable_bit     = OMAP24XX_EN_AES_SHIFT,
1661         .recalc         = &followparent_recalc,
1662 };
1663
1664 static struct clk pka_ick = {
1665         .name           = "pka_ick",
1666         .ops            = &clkops_omap2_dflt_wait,
1667         .parent         = &l4_ck,
1668         .clkdm_name     = "core_l4_clkdm",
1669         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1670         .enable_bit     = OMAP24XX_EN_PKA_SHIFT,
1671         .recalc         = &followparent_recalc,
1672 };
1673
1674 static struct clk usb_fck = {
1675         .name           = "usb_fck",
1676         .ops            = &clkops_omap2_dflt_wait,
1677         .parent         = &func_48m_ck,
1678         .clkdm_name     = "core_l3_clkdm",
1679         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1680         .enable_bit     = OMAP24XX_EN_USB_SHIFT,
1681         .recalc         = &followparent_recalc,
1682 };
1683
1684 /*
1685  * This clock is a composite clock which does entire set changes then
1686  * forces a rebalance. It keys on the MPU speed, but it really could
1687  * be any key speed part of a set in the rate table.
1688  *
1689  * to really change a set, you need memory table sets which get changed
1690  * in sram, pre-notifiers & post notifiers, changing the top set, without
1691  * having low level display recalc's won't work... this is why dpm notifiers
1692  * work, isr's off, walk a list of clocks already _off_ and not messing with
1693  * the bus.
1694  *
1695  * This clock should have no parent. It embodies the entire upper level
1696  * active set. A parent will mess up some of the init also.
1697  */
1698 static struct clk virt_prcm_set = {
1699         .name           = "virt_prcm_set",
1700         .ops            = &clkops_null,
1701         .parent         = &mpu_ck,      /* Indexed by mpu speed, no parent */
1702         .recalc         = &omap2_table_mpu_recalc,      /* sets are keyed on mpu rate */
1703         .set_rate       = &omap2_select_table_rate,
1704         .round_rate     = &omap2_round_to_table_rate,
1705 };
1706
1707
1708 /*
1709  * clkdev integration
1710  */
1711
1712 static struct omap_clk omap2420_clks[] = {
1713         /* external root sources */
1714         CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
1715         CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
1716         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
1717         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
1718         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
1719         /* internal analog sources */
1720         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
1721         CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
1722         CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
1723         /* internal prcm root sources */
1724         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
1725         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
1726         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
1727         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
1728         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
1729         CLK(NULL,       "ck_wdt1_osc",  &wdt1_osc_ck,   CK_242X),
1730         CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
1731         CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
1732         CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
1733         CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
1734         CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
1735         /* mpu domain clocks */
1736         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
1737         /* dsp domain clocks */
1738         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
1739         CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_242X),
1740         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
1741         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
1742         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
1743         /* GFX domain clocks */
1744         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
1745         CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
1746         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
1747         /* DSS domain clocks */
1748         CLK("omapdss",  "ick",          &dss_ick,       CK_242X),
1749         CLK("omapdss",  "dss1_fck",     &dss1_fck,      CK_242X),
1750         CLK("omapdss",  "dss2_fck",     &dss2_fck,      CK_242X),
1751         CLK("omapdss",  "tv_fck",       &dss_54m_fck,   CK_242X),
1752         /* L3 domain clocks */
1753         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
1754         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
1755         CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
1756         /* L4 domain clocks */
1757         CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
1758         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
1759         /* virtual meta-group clock */
1760         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
1761         /* general l4 interface ck, multi-parent functional clk */
1762         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
1763         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
1764         CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
1765         CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
1766         CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
1767         CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
1768         CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
1769         CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
1770         CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
1771         CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
1772         CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
1773         CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
1774         CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
1775         CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
1776         CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
1777         CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
1778         CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
1779         CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
1780         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
1781         CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
1782         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
1783         CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
1784         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
1785         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
1786         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
1787         CLK("omap-mcbsp.1", "fck",      &mcbsp1_fck,    CK_242X),
1788         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
1789         CLK("omap-mcbsp.2", "fck",      &mcbsp2_fck,    CK_242X),
1790         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
1791         CLK("omap2_mcspi.1", "fck",     &mcspi1_fck,    CK_242X),
1792         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
1793         CLK("omap2_mcspi.2", "fck",     &mcspi2_fck,    CK_242X),
1794         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
1795         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
1796         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
1797         CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
1798         CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
1799         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
1800         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
1801         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
1802         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
1803         CLK("omap_wdt", "fck",          &mpu_wdt_fck,   CK_242X),
1804         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
1805         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
1806         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
1807         CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
1808         CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
1809         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
1810         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
1811         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
1812         CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
1813         CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
1814         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
1815         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
1816         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
1817         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
1818         CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
1819         CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
1820         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
1821         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
1822         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
1823         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_242X),
1824         CLK("i2c_omap.1", "ick",        &i2c1_ick,      CK_242X),
1825         CLK("i2c_omap.1", "fck",        &i2c1_fck,      CK_242X),
1826         CLK("i2c_omap.2", "ick",        &i2c2_ick,      CK_242X),
1827         CLK("i2c_omap.2", "fck",        &i2c2_fck,      CK_242X),
1828         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
1829         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
1830         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
1831         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
1832         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
1833         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
1834         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
1835         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
1836         CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
1837         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
1838         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
1839         CLK("musb_hdrc",        "fck",  &osc_ck,        CK_242X),
1840 };
1841
1842 /*
1843  * init code
1844  */
1845
1846 int __init omap2420_clk_init(void)
1847 {
1848         const struct prcm_config *prcm;
1849         struct omap_clk *c;
1850         u32 clkrate;
1851
1852         prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1853         cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
1854         cpu_mask = RATE_IN_242X;
1855         rate_table = omap2420_rate_table;
1856
1857         clk_init(&omap2_clk_functions);
1858
1859         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1860              c++)
1861                 clk_preinit(c->lk.clk);
1862
1863         osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
1864         propagate_rate(&osc_ck);
1865         sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1866         propagate_rate(&sys_ck);
1867
1868         for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
1869              c++) {
1870                 clkdev_add(&c->lk);
1871                 clk_register(c->lk.clk);
1872                 omap2_init_clk_clkdm(c->lk.clk);
1873         }
1874
1875         /* Check the MPU rate set by bootloader */
1876         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
1877         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
1878                 if (!(prcm->flags & cpu_mask))
1879                         continue;
1880                 if (prcm->xtal_speed != sys_ck.rate)
1881                         continue;
1882                 if (prcm->dpll_speed <= clkrate)
1883                         break;
1884         }
1885         curr_prcm_set = prcm;
1886
1887         recalculate_root_clocks();
1888
1889         pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1890                 (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
1891                 (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1892
1893         /*
1894          * Only enable those clocks we will need, let the drivers
1895          * enable other clocks as necessary
1896          */
1897         clk_enable_init_clocks();
1898
1899         /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
1900         vclk = clk_get(NULL, "virt_prcm_set");
1901         sclk = clk_get(NULL, "sys_ck");
1902         dclk = clk_get(NULL, "dpll_ck");
1903
1904         return 0;
1905 }