2 * DA8XX/OMAP L1XX platform device data
4 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
5 * Derived from code that was:
6 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/serial_8250.h>
18 #include <mach/cputype.h>
19 #include <mach/common.h>
20 #include <mach/time.h>
21 #include <mach/da8xx.h>
22 #include <mach/cpuidle.h>
26 #define DA8XX_TPCC_BASE 0x01c00000
27 #define DA850_TPCC1_BASE 0x01e30000
28 #define DA8XX_TPTC0_BASE 0x01c08000
29 #define DA8XX_TPTC1_BASE 0x01c08400
30 #define DA850_TPTC2_BASE 0x01e38000
31 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
32 #define DA8XX_I2C0_BASE 0x01c22000
33 #define DA8XX_RTC_BASE 0x01C23000
34 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
35 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
36 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
37 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
38 #define DA8XX_GPIO_BASE 0x01e26000
39 #define DA8XX_I2C1_BASE 0x01e28000
41 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
42 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
43 #define DA8XX_EMAC_RAM_OFFSET 0x0000
44 #define DA8XX_MDIO_REG_OFFSET 0x4000
45 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
47 void __iomem
*da8xx_syscfg0_base
;
48 void __iomem
*da8xx_syscfg1_base
;
50 static struct plat_serial8250_port da8xx_serial_pdata
[] = {
52 .mapbase
= DA8XX_UART0_BASE
,
53 .irq
= IRQ_DA8XX_UARTINT0
,
54 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
60 .mapbase
= DA8XX_UART1_BASE
,
61 .irq
= IRQ_DA8XX_UARTINT1
,
62 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
68 .mapbase
= DA8XX_UART2_BASE
,
69 .irq
= IRQ_DA8XX_UARTINT2
,
70 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
80 struct platform_device da8xx_serial_device
= {
82 .id
= PLAT8250_DEV_PLATFORM
,
84 .platform_data
= da8xx_serial_pdata
,
88 static const s8 da8xx_queue_tc_mapping
[][2] = {
89 /* {event queue no, TC no} */
95 static const s8 da8xx_queue_priority_mapping
[][2] = {
96 /* {event queue no, Priority} */
102 static const s8 da850_queue_tc_mapping
[][2] = {
103 /* {event queue no, TC no} */
108 static const s8 da850_queue_priority_mapping
[][2] = {
109 /* {event queue no, Priority} */
114 static struct edma_soc_info da830_edma_cc0_info
= {
120 .queue_tc_mapping
= da8xx_queue_tc_mapping
,
121 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
124 static struct edma_soc_info
*da830_edma_info
[EDMA_MAX_CC
] = {
125 &da830_edma_cc0_info
,
128 static struct edma_soc_info da850_edma_cc_info
[] = {
135 .queue_tc_mapping
= da8xx_queue_tc_mapping
,
136 .queue_priority_mapping
= da8xx_queue_priority_mapping
,
144 .queue_tc_mapping
= da850_queue_tc_mapping
,
145 .queue_priority_mapping
= da850_queue_priority_mapping
,
149 static struct edma_soc_info
*da850_edma_info
[EDMA_MAX_CC
] = {
150 &da850_edma_cc_info
[0],
151 &da850_edma_cc_info
[1],
154 static struct resource da830_edma_resources
[] = {
157 .start
= DA8XX_TPCC_BASE
,
158 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
159 .flags
= IORESOURCE_MEM
,
163 .start
= DA8XX_TPTC0_BASE
,
164 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
165 .flags
= IORESOURCE_MEM
,
169 .start
= DA8XX_TPTC1_BASE
,
170 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
171 .flags
= IORESOURCE_MEM
,
175 .start
= IRQ_DA8XX_CCINT0
,
176 .flags
= IORESOURCE_IRQ
,
180 .start
= IRQ_DA8XX_CCERRINT
,
181 .flags
= IORESOURCE_IRQ
,
185 static struct resource da850_edma_resources
[] = {
188 .start
= DA8XX_TPCC_BASE
,
189 .end
= DA8XX_TPCC_BASE
+ SZ_32K
- 1,
190 .flags
= IORESOURCE_MEM
,
194 .start
= DA8XX_TPTC0_BASE
,
195 .end
= DA8XX_TPTC0_BASE
+ SZ_1K
- 1,
196 .flags
= IORESOURCE_MEM
,
200 .start
= DA8XX_TPTC1_BASE
,
201 .end
= DA8XX_TPTC1_BASE
+ SZ_1K
- 1,
202 .flags
= IORESOURCE_MEM
,
206 .start
= DA850_TPCC1_BASE
,
207 .end
= DA850_TPCC1_BASE
+ SZ_32K
- 1,
208 .flags
= IORESOURCE_MEM
,
212 .start
= DA850_TPTC2_BASE
,
213 .end
= DA850_TPTC2_BASE
+ SZ_1K
- 1,
214 .flags
= IORESOURCE_MEM
,
218 .start
= IRQ_DA8XX_CCINT0
,
219 .flags
= IORESOURCE_IRQ
,
223 .start
= IRQ_DA8XX_CCERRINT
,
224 .flags
= IORESOURCE_IRQ
,
228 .start
= IRQ_DA850_CCINT1
,
229 .flags
= IORESOURCE_IRQ
,
233 .start
= IRQ_DA850_CCERRINT1
,
234 .flags
= IORESOURCE_IRQ
,
238 static struct platform_device da830_edma_device
= {
242 .platform_data
= da830_edma_info
,
244 .num_resources
= ARRAY_SIZE(da830_edma_resources
),
245 .resource
= da830_edma_resources
,
248 static struct platform_device da850_edma_device
= {
252 .platform_data
= da850_edma_info
,
254 .num_resources
= ARRAY_SIZE(da850_edma_resources
),
255 .resource
= da850_edma_resources
,
258 int __init
da830_register_edma(struct edma_rsv_info
*rsv
)
260 da830_edma_cc0_info
.rsv
= rsv
;
262 return platform_device_register(&da830_edma_device
);
265 int __init
da850_register_edma(struct edma_rsv_info
*rsv
[2])
268 da850_edma_cc_info
[0].rsv
= rsv
[0];
269 da850_edma_cc_info
[1].rsv
= rsv
[1];
272 return platform_device_register(&da850_edma_device
);
275 static struct resource da8xx_i2c_resources0
[] = {
277 .start
= DA8XX_I2C0_BASE
,
278 .end
= DA8XX_I2C0_BASE
+ SZ_4K
- 1,
279 .flags
= IORESOURCE_MEM
,
282 .start
= IRQ_DA8XX_I2CINT0
,
283 .end
= IRQ_DA8XX_I2CINT0
,
284 .flags
= IORESOURCE_IRQ
,
288 static struct platform_device da8xx_i2c_device0
= {
289 .name
= "i2c_davinci",
291 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources0
),
292 .resource
= da8xx_i2c_resources0
,
295 static struct resource da8xx_i2c_resources1
[] = {
297 .start
= DA8XX_I2C1_BASE
,
298 .end
= DA8XX_I2C1_BASE
+ SZ_4K
- 1,
299 .flags
= IORESOURCE_MEM
,
302 .start
= IRQ_DA8XX_I2CINT1
,
303 .end
= IRQ_DA8XX_I2CINT1
,
304 .flags
= IORESOURCE_IRQ
,
308 static struct platform_device da8xx_i2c_device1
= {
309 .name
= "i2c_davinci",
311 .num_resources
= ARRAY_SIZE(da8xx_i2c_resources1
),
312 .resource
= da8xx_i2c_resources1
,
315 int __init
da8xx_register_i2c(int instance
,
316 struct davinci_i2c_platform_data
*pdata
)
318 struct platform_device
*pdev
;
321 pdev
= &da8xx_i2c_device0
;
322 else if (instance
== 1)
323 pdev
= &da8xx_i2c_device1
;
327 pdev
->dev
.platform_data
= pdata
;
328 return platform_device_register(pdev
);
331 static struct resource da8xx_watchdog_resources
[] = {
333 .start
= DA8XX_WDOG_BASE
,
334 .end
= DA8XX_WDOG_BASE
+ SZ_4K
- 1,
335 .flags
= IORESOURCE_MEM
,
339 struct platform_device da8xx_wdt_device
= {
342 .num_resources
= ARRAY_SIZE(da8xx_watchdog_resources
),
343 .resource
= da8xx_watchdog_resources
,
346 int __init
da8xx_register_watchdog(void)
348 return platform_device_register(&da8xx_wdt_device
);
351 static struct resource da8xx_emac_resources
[] = {
353 .start
= DA8XX_EMAC_CPPI_PORT_BASE
,
354 .end
= DA8XX_EMAC_CPPI_PORT_BASE
+ 0x5000 - 1,
355 .flags
= IORESOURCE_MEM
,
358 .start
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
359 .end
= IRQ_DA8XX_C0_RX_THRESH_PULSE
,
360 .flags
= IORESOURCE_IRQ
,
363 .start
= IRQ_DA8XX_C0_RX_PULSE
,
364 .end
= IRQ_DA8XX_C0_RX_PULSE
,
365 .flags
= IORESOURCE_IRQ
,
368 .start
= IRQ_DA8XX_C0_TX_PULSE
,
369 .end
= IRQ_DA8XX_C0_TX_PULSE
,
370 .flags
= IORESOURCE_IRQ
,
373 .start
= IRQ_DA8XX_C0_MISC_PULSE
,
374 .end
= IRQ_DA8XX_C0_MISC_PULSE
,
375 .flags
= IORESOURCE_IRQ
,
379 struct emac_platform_data da8xx_emac_pdata
= {
380 .ctrl_reg_offset
= DA8XX_EMAC_CTRL_REG_OFFSET
,
381 .ctrl_mod_reg_offset
= DA8XX_EMAC_MOD_REG_OFFSET
,
382 .ctrl_ram_offset
= DA8XX_EMAC_RAM_OFFSET
,
383 .mdio_reg_offset
= DA8XX_MDIO_REG_OFFSET
,
384 .ctrl_ram_size
= DA8XX_EMAC_CTRL_RAM_SIZE
,
385 .version
= EMAC_VERSION_2
,
388 static struct platform_device da8xx_emac_device
= {
389 .name
= "davinci_emac",
392 .platform_data
= &da8xx_emac_pdata
,
394 .num_resources
= ARRAY_SIZE(da8xx_emac_resources
),
395 .resource
= da8xx_emac_resources
,
398 int __init
da8xx_register_emac(void)
400 return platform_device_register(&da8xx_emac_device
);
403 static struct resource da830_mcasp1_resources
[] = {
406 .start
= DAVINCI_DA830_MCASP1_REG_BASE
,
407 .end
= DAVINCI_DA830_MCASP1_REG_BASE
+ (SZ_1K
* 12) - 1,
408 .flags
= IORESOURCE_MEM
,
412 .start
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
413 .end
= DAVINCI_DA830_DMA_MCASP1_AXEVT
,
414 .flags
= IORESOURCE_DMA
,
418 .start
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
419 .end
= DAVINCI_DA830_DMA_MCASP1_AREVT
,
420 .flags
= IORESOURCE_DMA
,
424 static struct platform_device da830_mcasp1_device
= {
425 .name
= "davinci-mcasp",
427 .num_resources
= ARRAY_SIZE(da830_mcasp1_resources
),
428 .resource
= da830_mcasp1_resources
,
431 static struct resource da850_mcasp_resources
[] = {
434 .start
= DAVINCI_DA8XX_MCASP0_REG_BASE
,
435 .end
= DAVINCI_DA8XX_MCASP0_REG_BASE
+ (SZ_1K
* 12) - 1,
436 .flags
= IORESOURCE_MEM
,
440 .start
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
441 .end
= DAVINCI_DA8XX_DMA_MCASP0_AXEVT
,
442 .flags
= IORESOURCE_DMA
,
446 .start
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
447 .end
= DAVINCI_DA8XX_DMA_MCASP0_AREVT
,
448 .flags
= IORESOURCE_DMA
,
452 static struct platform_device da850_mcasp_device
= {
453 .name
= "davinci-mcasp",
455 .num_resources
= ARRAY_SIZE(da850_mcasp_resources
),
456 .resource
= da850_mcasp_resources
,
459 void __init
da8xx_register_mcasp(int id
, struct snd_platform_data
*pdata
)
461 /* DA830/OMAP-L137 has 3 instances of McASP */
462 if (cpu_is_davinci_da830() && id
== 1) {
463 da830_mcasp1_device
.dev
.platform_data
= pdata
;
464 platform_device_register(&da830_mcasp1_device
);
465 } else if (cpu_is_davinci_da850()) {
466 da850_mcasp_device
.dev
.platform_data
= pdata
;
467 platform_device_register(&da850_mcasp_device
);
471 static const struct display_panel disp_panel
= {
478 static struct lcd_ctrl_config lcd_cfg
= {
488 .invert_line_clock
= 1,
489 .invert_frm_clock
= 1,
495 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata
= {
496 .manu_name
= "sharp",
497 .controller_data
= &lcd_cfg
,
498 .type
= "Sharp_LCD035Q3DG01",
501 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata
= {
502 .manu_name
= "sharp",
503 .controller_data
= &lcd_cfg
,
504 .type
= "Sharp_LK043T1DG01",
507 static struct resource da8xx_lcdc_resources
[] = {
508 [0] = { /* registers */
509 .start
= DA8XX_LCD_CNTRL_BASE
,
510 .end
= DA8XX_LCD_CNTRL_BASE
+ SZ_4K
- 1,
511 .flags
= IORESOURCE_MEM
,
513 [1] = { /* interrupt */
514 .start
= IRQ_DA8XX_LCDINT
,
515 .end
= IRQ_DA8XX_LCDINT
,
516 .flags
= IORESOURCE_IRQ
,
520 static struct platform_device da8xx_lcdc_device
= {
521 .name
= "da8xx_lcdc",
523 .num_resources
= ARRAY_SIZE(da8xx_lcdc_resources
),
524 .resource
= da8xx_lcdc_resources
,
527 int __init
da8xx_register_lcdc(struct da8xx_lcdc_platform_data
*pdata
)
529 da8xx_lcdc_device
.dev
.platform_data
= pdata
;
530 return platform_device_register(&da8xx_lcdc_device
);
533 static struct resource da8xx_mmcsd0_resources
[] = {
535 .start
= DA8XX_MMCSD0_BASE
,
536 .end
= DA8XX_MMCSD0_BASE
+ SZ_4K
- 1,
537 .flags
= IORESOURCE_MEM
,
540 .start
= IRQ_DA8XX_MMCSDINT0
,
541 .end
= IRQ_DA8XX_MMCSDINT0
,
542 .flags
= IORESOURCE_IRQ
,
545 .start
= EDMA_CTLR_CHAN(0, 16),
546 .end
= EDMA_CTLR_CHAN(0, 16),
547 .flags
= IORESOURCE_DMA
,
550 .start
= EDMA_CTLR_CHAN(0, 17),
551 .end
= EDMA_CTLR_CHAN(0, 17),
552 .flags
= IORESOURCE_DMA
,
556 static struct platform_device da8xx_mmcsd0_device
= {
557 .name
= "davinci_mmc",
559 .num_resources
= ARRAY_SIZE(da8xx_mmcsd0_resources
),
560 .resource
= da8xx_mmcsd0_resources
,
563 int __init
da8xx_register_mmcsd0(struct davinci_mmc_config
*config
)
565 da8xx_mmcsd0_device
.dev
.platform_data
= config
;
566 return platform_device_register(&da8xx_mmcsd0_device
);
569 static struct resource da8xx_rtc_resources
[] = {
571 .start
= DA8XX_RTC_BASE
,
572 .end
= DA8XX_RTC_BASE
+ SZ_4K
- 1,
573 .flags
= IORESOURCE_MEM
,
576 .start
= IRQ_DA8XX_RTC
,
577 .end
= IRQ_DA8XX_RTC
,
578 .flags
= IORESOURCE_IRQ
,
581 .start
= IRQ_DA8XX_RTC
,
582 .end
= IRQ_DA8XX_RTC
,
583 .flags
= IORESOURCE_IRQ
,
587 static struct platform_device da8xx_rtc_device
= {
590 .num_resources
= ARRAY_SIZE(da8xx_rtc_resources
),
591 .resource
= da8xx_rtc_resources
,
594 int da8xx_register_rtc(void)
599 base
= ioremap(DA8XX_RTC_BASE
, SZ_4K
);
603 /* Unlock the rtc's registers */
604 __raw_writel(0x83e70b13, base
+ 0x6c);
605 __raw_writel(0x95a4f1e0, base
+ 0x70);
609 ret
= platform_device_register(&da8xx_rtc_device
);
611 /* Atleast on DA850, RTC is a wakeup source */
612 device_init_wakeup(&da8xx_rtc_device
.dev
, true);
617 static void __iomem
*da8xx_ddr2_ctlr_base
;
618 void __iomem
* __init
da8xx_get_mem_ctlr(void)
620 if (da8xx_ddr2_ctlr_base
)
621 return da8xx_ddr2_ctlr_base
;
623 da8xx_ddr2_ctlr_base
= ioremap(DA8XX_DDR2_CTL_BASE
, SZ_32K
);
624 if (!da8xx_ddr2_ctlr_base
)
625 pr_warning("%s: Unable to map DDR2 controller", __func__
);
627 return da8xx_ddr2_ctlr_base
;
630 static struct resource da8xx_cpuidle_resources
[] = {
632 .start
= DA8XX_DDR2_CTL_BASE
,
633 .end
= DA8XX_DDR2_CTL_BASE
+ SZ_32K
- 1,
634 .flags
= IORESOURCE_MEM
,
638 /* DA8XX devices support DDR2 power down */
639 static struct davinci_cpuidle_config da8xx_cpuidle_pdata
= {
644 static struct platform_device da8xx_cpuidle_device
= {
645 .name
= "cpuidle-davinci",
646 .num_resources
= ARRAY_SIZE(da8xx_cpuidle_resources
),
647 .resource
= da8xx_cpuidle_resources
,
649 .platform_data
= &da8xx_cpuidle_pdata
,
653 int __init
da8xx_register_cpuidle(void)
655 da8xx_cpuidle_pdata
.ddr2_ctlr_base
= da8xx_get_mem_ctlr();
657 return platform_device_register(&da8xx_cpuidle_device
);