release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-davinci/board-neuros-osd2.c

   1 /*
   2  * Neuros Technologies OSD2 board support
   3  *
   4  * Modified from original 644X-EVM board support.
   5  * 2008 (c) Neuros Technology, LLC.
   6  * 2009 (c) Jorge Luis Zapata Muga <jorgeluis.zapata@gmail.com>
   7  * 2009 (c) Andrey A. Porodko <Andrey.Porodko@gmail.com>
   8  *
   9  * The Neuros OSD 2.0 is the hardware component of the Neuros Open
  10  * Internet Television Platform. Hardware is very close to TI
  11  * DM644X-EVM board. It has:
  12  *      DM6446M02 module with 256MB NAND, 256MB RAM, TLV320AIC32 AIC,
  13  *      USB, Ethernet, SD/MMC, UART, THS8200, TVP7000 for video.
  14  *      Additionaly realtime clock, IR remote control receiver,
  15  *      IR Blaster based on MSP430 (firmware although is different
  16  *      from used in DM644X-EVM), internal ATA-6 3.5” HDD drive
  17  *      with PATA interface, two muxed red-green leds.
  18  *
  19  * For more information please refer to
  20  *              http://wiki.neurostechnology.com/index.php/OSD_2.0_HD
  21  *
  22  * This file is licensed under the terms of the GNU General Public
  23  * License version 2. This program is licensed "as is" without any
  24  * warranty of any kind, whether express or implied.
  25  */
  26 #include <linux/platform_device.h>
  27 #include <linux/gpio.h>
  28 #include <linux/mtd/partitions.h>
  29
  30 #include <asm/mach-types.h>
  31 #include <asm/mach/arch.h>
  32
  33 #include <mach/dm644x.h>
  34 #include <mach/common.h>
  35 #include <mach/i2c.h>
  36 #include <mach/serial.h>
  37 #include <mach/mux.h>
  38 #include <mach/nand.h>
  39 #include <mach/mmc.h>
  40 #include <mach/usb.h>
  41
  42 #define NEUROS_OSD2_PHY_MASK            0x2
  43 #define NEUROS_OSD2_MDIO_FREQUENCY      2200000 /* PHY bus frequency */
  44
  45 #define LXT971_PHY_ID                   0x001378e2
  46 #define LXT971_PHY_MASK                 0xfffffff0
  47
  48 #define NTOSD2_AUDIOSOC_I2C_ADDR        0x18
  49 #define NTOSD2_MSP430_I2C_ADDR          0x59
  50 #define NTOSD2_MSP430_IRQ               2
  51
  52 /* Neuros OSD2 has a Samsung 256 MByte NAND flash (Dev ID of 0xAA,
  53  * 2048 blocks in the device, 64 pages per block, 2048 bytes per
  54  * page.
  55  */
  56
  57 #define NAND_BLOCK_SIZE         SZ_128K
  58
  59 static struct mtd_partition davinci_ntosd2_nandflash_partition[] = {
  60         {
  61                 /* UBL (a few copies) plus U-Boot */
  62                 .name           = "bootloader",
  63                 .offset         = 0,
  64                 .size           = 15 * NAND_BLOCK_SIZE,
  65                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
  66         }, {
  67                 /* U-Boot environment */
  68                 .name           = "params",
  69                 .offset         = MTDPART_OFS_APPEND,
  70                 .size           = 1 * NAND_BLOCK_SIZE,
  71                 .mask_flags     = 0,
  72         }, {
  73                 /* Kernel */
  74                 .name           = "kernel",
  75                 .offset         = MTDPART_OFS_APPEND,
  76                 .size           = SZ_4M,
  77                 .mask_flags     = 0,
  78         }, {
  79                 /* File System */
  80                 .name           = "filesystem",
  81                 .offset         = MTDPART_OFS_APPEND,
  82                 .size           = MTDPART_SIZ_FULL,
  83                 .mask_flags     = 0,
  84         }
  85         /* A few blocks at end hold a flash Bad Block Table. */
  86 };
  87
  88 static struct davinci_nand_pdata davinci_ntosd2_nandflash_data = {
  89         .parts          = davinci_ntosd2_nandflash_partition,
  90         .nr_parts       = ARRAY_SIZE(davinci_ntosd2_nandflash_partition),
  91         .ecc_mode       = NAND_ECC_HW,
  92         .options        = NAND_USE_FLASH_BBT,
  93 };
  94
  95 static struct resource davinci_ntosd2_nandflash_resource[] = {
  96         {
  97                 .start          = DM644X_ASYNC_EMIF_DATA_CE0_BASE,
  98                 .end            = DM644X_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
  99                 .flags          = IORESOURCE_MEM,
 100         }, {
 101                 .start          = DM644X_ASYNC_EMIF_CONTROL_BASE,
 102                 .end            = DM644X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 103                 .flags          = IORESOURCE_MEM,
 104         },
 105 };
 106
 107 static struct platform_device davinci_ntosd2_nandflash_device = {
 108         .name           = "davinci_nand",
 109         .id             = 0,
 110         .dev            = {
 111                 .platform_data  = &davinci_ntosd2_nandflash_data,
 112         },
 113         .num_resources  = ARRAY_SIZE(davinci_ntosd2_nandflash_resource),
 114         .resource       = davinci_ntosd2_nandflash_resource,
 115 };
 116
 117 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
 118
 119 static struct platform_device davinci_fb_device = {
 120         .name           = "davincifb",
 121         .id             = -1,
 122         .dev = {
 123                 .dma_mask               = &davinci_fb_dma_mask,
 124                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 125         },
 126         .num_resources = 0,
 127 };
 128
 129 static struct snd_platform_data dm644x_ntosd2_snd_data;
 130
 131 static struct gpio_led ntosd2_leds[] = {
 132         { .name = "led1_green", .gpio = GPIO(10), },
 133         { .name = "led1_red",   .gpio = GPIO(11), },
 134         { .name = "led2_green", .gpio = GPIO(12), },
 135         { .name = "led2_red",   .gpio = GPIO(13), },
 136 };
 137
 138 static struct gpio_led_platform_data ntosd2_leds_data = {
 139         .num_leds       = ARRAY_SIZE(ntosd2_leds),
 140         .leds           = ntosd2_leds,
 141 };
 142
 143 static struct platform_device ntosd2_leds_dev = {
 144         .name = "leds-gpio",
 145         .id   = -1,
 146         .dev = {
 147                 .platform_data          = &ntosd2_leds_data,
 148         },
 149 };
 150
 151
 152 static struct platform_device *davinci_ntosd2_devices[] __initdata = {
 153         &davinci_fb_device,
 154         &ntosd2_leds_dev,
 155 };
 156
 157 static struct davinci_uart_config uart_config __initdata = {
 158         .enabled_uarts = (1 << 0),
 159 };
 160
 161 static void __init davinci_ntosd2_map_io(void)
 162 {
 163         dm644x_init();
 164 }
 165
 166 /*
 167  I2C initialization
 168 */
 169 static struct davinci_i2c_platform_data ntosd2_i2c_pdata = {
 170         .bus_freq       = 20 /* kHz */,
 171         .bus_delay      = 100 /* usec */,
 172 };
 173
 174 static struct i2c_board_info __initdata ntosd2_i2c_info[] =  {
 175 };
 176
 177 static  int ntosd2_init_i2c(void)
 178 {
 179         int     status;
 180
 181         davinci_init_i2c(&ntosd2_i2c_pdata);
 182         status = gpio_request(NTOSD2_MSP430_IRQ, ntosd2_i2c_info[0].type);
 183         if (status == 0) {
 184                 status = gpio_direction_input(NTOSD2_MSP430_IRQ);
 185                 if (status == 0) {
 186                         status = gpio_to_irq(NTOSD2_MSP430_IRQ);
 187                         if (status > 0) {
 188                                 ntosd2_i2c_info[0].irq = status;
 189                                 i2c_register_board_info(1,
 190                                         ntosd2_i2c_info,
 191                                         ARRAY_SIZE(ntosd2_i2c_info));
 192                         }
 193                 }
 194         }
 195         return status;
 196 }
 197
 198 static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
 199         .wires          = 4,
 200         .version        = MMC_CTLR_VERSION_1
 201 };
 202
 203
 204 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
 205         defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
 206 #define HAS_ATA 1
 207 #else
 208 #define HAS_ATA 0
 209 #endif
 210
 211 #if defined(CONFIG_MTD_NAND_DAVINCI) || defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
 212 #define HAS_NAND 1
 213 #else
 214 #define HAS_NAND 0
 215 #endif
 216
 217 static __init void davinci_ntosd2_init(void)
 218 {
 219         struct clk *aemif_clk;
 220         struct davinci_soc_info *soc_info = &davinci_soc_info;
 221         int     status;
 222
 223         aemif_clk = clk_get(NULL, "aemif");
 224         clk_enable(aemif_clk);
 225
 226         if (HAS_ATA) {
 227                 if (HAS_NAND)
 228                         pr_warning("WARNING: both IDE and Flash are "
 229                                 "enabled, but they share AEMIF pins.\n"
 230                                 "\tDisable IDE for NAND/NOR support.\n");
 231                 davinci_init_ide();
 232         } else if (HAS_NAND) {
 233                 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
 234                 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
 235
 236                 /* only one device will be jumpered and detected */
 237                 if (HAS_NAND)
 238                         platform_device_register(
 239                                         &davinci_ntosd2_nandflash_device);
 240         }
 241
 242         platform_add_devices(davinci_ntosd2_devices,
 243                                 ARRAY_SIZE(davinci_ntosd2_devices));
 244
 245         /* Initialize I2C interface specific for this board */
 246         status = ntosd2_init_i2c();
 247         if (status < 0)
 248                 pr_warning("davinci_ntosd2_init: msp430 irq setup failed:"
 249                                                 "        %d\n", status);
 250
 251         davinci_serial_init(&uart_config);
 252         dm644x_init_asp(&dm644x_ntosd2_snd_data);
 253
 254         soc_info->emac_pdata->phy_mask = NEUROS_OSD2_PHY_MASK;
 255         soc_info->emac_pdata->mdio_max_freq = NEUROS_OSD2_MDIO_FREQUENCY;
 256
 257         davinci_setup_usb(1000, 8);
 258         /*
 259          * Mux the pins to be GPIOs, VLYNQEN is already done at startup.
 260          * The AEAWx are five new AEAW pins that can be muxed by separately.
 261          * They are a bitmask for GPIO management. According TI
 262          * documentation (http://www.ti.com/lit/gpn/tms320dm6446) to employ
 263          * gpio(10,11,12,13) for leds any combination of bits works except
 264          * four last. So we are to reset all five.
 265          */
 266         davinci_cfg_reg(DM644X_AEAW0);
 267         davinci_cfg_reg(DM644X_AEAW1);
 268         davinci_cfg_reg(DM644X_AEAW2);
 269         davinci_cfg_reg(DM644X_AEAW3);
 270         davinci_cfg_reg(DM644X_AEAW4);
 271
 272         davinci_setup_mmc(0, &davinci_ntosd2_mmc_config);
 273 }
 274
 275 MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
 276         /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
 277         .phys_io        = IO_PHYS,
 278         .io_pg_offst    = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 279         .boot_params    = (DAVINCI_DDR_BASE + 0x100),
 280         .map_io          = davinci_ntosd2_map_io,
 281         .init_irq       = davinci_irq_init,
 282         .timer          = &davinci_timer,
 283         .init_machine = davinci_ntosd2_init,
 284 MACHINE_END