release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h

   1 /*****************************************************************************
   2 * Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 #ifndef CHIPC_DEF_H
  16 #define CHIPC_DEF_H
  17
  18 /* ---- Include Files ----------------------------------------------------- */
  19
  20 #include <csp/stdint.h>
  21 #include <csp/errno.h>
  22 #include <csp/reg.h>
  23 #include <mach/csp/chipcHw_reg.h>
  24
  25 /* ---- Public Constants and Types ---------------------------------------- */
  26
  27 /* Set 1 to configure DDR/VPM phase alignment by HW */
  28 #define chipcHw_DDR_HW_PHASE_ALIGN    0
  29 #define chipcHw_VPM_HW_PHASE_ALIGN    0
  30
  31 typedef uint32_t chipcHw_freq;
  32
  33 /* Configurable miscellaneous clocks */
  34 typedef enum {
  35         chipcHw_CLOCK_DDR,      /* DDR PHY Clock */
  36         chipcHw_CLOCK_ARM,      /* ARM Clock */
  37         chipcHw_CLOCK_ESW,      /* Ethernet Switch Clock */
  38         chipcHw_CLOCK_VPM,      /* VPM Clock */
  39         chipcHw_CLOCK_ESW125,   /* Ethernet MII Clock */
  40         chipcHw_CLOCK_UART,     /* UART Clock */
  41         chipcHw_CLOCK_SDIO0,    /* SDIO 0 Clock */
  42         chipcHw_CLOCK_SDIO1,    /* SDIO 1 Clock */
  43         chipcHw_CLOCK_SPI,      /* SPI Clock */
  44         chipcHw_CLOCK_ETM,      /* ARM ETM Clock */
  45
  46         chipcHw_CLOCK_BUS,      /* BUS Clock */
  47         chipcHw_CLOCK_OTP,      /* OTP Clock */
  48         chipcHw_CLOCK_I2C,      /* I2C Host Clock */
  49         chipcHw_CLOCK_I2S0,     /* I2S 0 Host Clock */
  50         chipcHw_CLOCK_RTBUS,    /* DDR PHY Configuration Clock */
  51         chipcHw_CLOCK_APM100,   /* APM100 Clock */
  52         chipcHw_CLOCK_TSC,      /* Touch screen Clock */
  53         chipcHw_CLOCK_LED,      /* LED Clock */
  54
  55         chipcHw_CLOCK_USB,      /* USB Clock */
  56         chipcHw_CLOCK_LCD,      /* LCD CLock */
  57         chipcHw_CLOCK_APM,      /* APM Clock */
  58
  59         chipcHw_CLOCK_I2S1,     /* I2S 1 Host Clock */
  60 } chipcHw_CLOCK_e;
  61
  62 /* System booting strap options */
  63 typedef enum {
  64         chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
  65         chipcHw_BOOT_DEVICE_SERIAL_FLASH =
  66             chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
  67         chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
  68             chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
  69         chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
  70             chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
  71         chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
  72             chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
  73 } chipcHw_BOOT_DEVICE_e;
  74
  75 /* System booting modes */
  76 typedef enum {
  77         chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
  78         chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
  79         chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
  80         chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
  81 } chipcHw_BOOT_MODE_e;
  82
  83 /* NAND Flash page size strap options */
  84 typedef enum {
  85         chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
  86         chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
  87         chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
  88         chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
  89 } chipcHw_NAND_PAGESIZE_e;
  90
  91 /* GPIO Pin function */
  92 typedef enum {
  93         chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
  94         chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
  95         chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
  96         chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
  97         chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
  98         chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
  99         chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
 100         chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
 101         chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
 102         chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
 103         chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
 104         chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
 105         chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
 106         chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
 107 } chipcHw_GPIO_FUNCTION_e;
 108
 109 /* PIN Output slew rate */
 110 typedef enum {
 111         chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
 112         chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
 113 } chipcHw_PIN_SLEW_RATE_e;
 114
 115 /* PIN Current drive strength */
 116 typedef enum {
 117         chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
 118         chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
 119         chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
 120         chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
 121         chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
 122         chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
 123 } chipcHw_PIN_CURRENT_STRENGTH_e;
 124
 125 /* PIN Pull up register settings */
 126 typedef enum {
 127         chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
 128         chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
 129         chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
 130 } chipcHw_PIN_PULL_e;
 131
 132 /* PIN input type settings */
 133 typedef enum {
 134         chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
 135         chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
 136 } chipcHw_PIN_INPUTTYPE_e;
 137
 138 /* Allow/Disalow the support of spread spectrum  */
 139 typedef enum {
 140         chipcHw_SPREAD_SPECTRUM_DISALLOW,       /* Spread spectrum support is not allowed */
 141         chipcHw_SPREAD_SPECTRUM_ALLOW   /* Spread spectrum support is allowed */
 142 } chipcHw_SPREAD_SPECTRUM_e;
 143
 144 typedef struct {
 145         chipcHw_SPREAD_SPECTRUM_e ssSupport;    /* Allow/Disalow to support spread spectrum.
 146                                                    If supported, call chipcHw_enableSpreadSpectrum ()
 147                                                    to activate the spread spectrum with desired spread. */
 148         uint32_t pllVcoFreqHz;  /* PLL VCO frequency in Hz */
 149         uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
 150         uint32_t busClockFreqHz;        /* Bus clock frequency in Hz */
 151         uint32_t armBusRatio;   /* ARM clock : Bus clock */
 152         uint32_t vpmBusRatio;   /* VPM clock : Bus clock */
 153         uint32_t ddrBusRatio;   /* DDR clock : Bus clock */
 154 } chipcHw_INIT_PARAM_t;
 155
 156 /* CHIP revision number */
 157 typedef enum {
 158         chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
 159         chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
 160 } chipcHw_REV_NUMBER_e;
 161
 162 typedef enum {
 163         chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
 164         chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
 165         chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
 166         chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
 167 } chipcHw_VPM_HW_PHASE_INTR_e;
 168
 169 typedef enum {
 170         chipcHw_DDR_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for DDR phase align condition */
 171         chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for DDR phase align condition */
 172         chipcHw_DDR_HW_PHASE_MARGIN_WIDE        /*  Wider margin for DDR phase align condition */
 173 } chipcHw_DDR_HW_PHASE_MARGIN_e;
 174
 175 typedef enum {
 176         chipcHw_VPM_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for VPM phase align condition */
 177         chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for VPM phase align condition */
 178         chipcHw_VPM_HW_PHASE_MARGIN_WIDE        /*  Wider margin for VPM phase align condition */
 179 } chipcHw_VPM_HW_PHASE_MARGIN_e;
 180
 181 #define chipcHw_XTAL_FREQ_Hz                    25000000        /* Reference clock frequency in Hz */
 182
 183 /* Programable pin defines */
 184 #define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
 185                                                                              /* GPIO pin 0 - 60 */
 186 #define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)        /* UART Transmit */
 187 #define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 1)        /* NVI Interface */
 188 #define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 2)        /* NVI Interface */
 189 #define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 3)        /* NVI Interface */
 190 #define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 4)        /* NVI Interface */
 191 #define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 5)        /* NVI Interface */
 192 #define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 6)        /* NVI Interface */
 193 #define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 7)        /* NVI Interface */
 194 #define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 8)        /* NVI Interface */
 195 #define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 9)        /* LCD Data 0 - 17 */
 196 #define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 10)       /* LCD Data 18 - 20 */
 197 #define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 11)       /* LCD Data 21 - 23 */
 198 #define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 12)       /* LCD Power */
 199 #define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 13)       /* LCD Ack */
 200 #define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 14)       /* LCD FP */
 201 #define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 15)       /* LCD LP */
 202 #define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 16)       /* UART Receive */
 203
 204 /* ---- Public Variable Externs ------------------------------------------ */
 205 /* ---- Public Function Prototypes --------------------------------------- */
 206
 207 /****************************************************************************/
 208 /**
 209 *  @brief  Initializes the clock module
 210 *
 211 */
 212 /****************************************************************************/
 213 void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
 214     ) __attribute__ ((section(".aramtext")));
 215
 216 /****************************************************************************/
 217 /**
 218 *  @brief  Enables the PLL1
 219 *
 220 *  This function enables the PLL1
 221 *
 222 */
 223 /****************************************************************************/
 224 void chipcHw_pll1Enable(uint32_t vcoFreqHz,     /*  [ IN ] VCO frequency in Hz */
 225                         chipcHw_SPREAD_SPECTRUM_e ssSupport     /*  [ IN ] SS status */
 226     ) __attribute__ ((section(".aramtext")));
 227
 228 /****************************************************************************/
 229 /**
 230 *  @brief  Enables the PLL2
 231 *
 232 *  This function enables the PLL2
 233 *
 234 */
 235 /****************************************************************************/
 236 void chipcHw_pll2Enable(uint32_t vcoFreqHz      /*  [ IN ] VCO frequency in Hz */
 237     ) __attribute__ ((section(".aramtext")));
 238
 239 /****************************************************************************/
 240 /**
 241 *  @brief  Disable the PLL1
 242 *
 243 */
 244 /****************************************************************************/
 245 static inline void chipcHw_pll1Disable(void);
 246
 247 /****************************************************************************/
 248 /**
 249 *  @brief  Disable the PLL2
 250 *
 251 */
 252 /****************************************************************************/
 253 static inline void chipcHw_pll2Disable(void);
 254
 255 /****************************************************************************/
 256 /**
 257 *  @brief   Set clock fequency for miscellaneous configurable clocks
 258 *
 259 *  This function sets clock frequency
 260 *
 261 *  @return  Configured clock frequency in KHz
 262 *
 263 */
 264 /****************************************************************************/
 265 chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
 266     ) __attribute__ ((section(".aramtext")));
 267
 268 /****************************************************************************/
 269 /**
 270 *  @brief   Set clock fequency for miscellaneous configurable clocks
 271 *
 272 *  This function sets clock frequency
 273 *
 274 *  @return  Configured clock frequency in Hz
 275 *
 276 */
 277 /****************************************************************************/
 278 chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
 279                                        uint32_t freq    /*  [ IN ] Clock frequency in Hz */
 280     ) __attribute__ ((section(".aramtext")));
 281
 282 /****************************************************************************/
 283 /**
 284 *  @brief   Set VPM clock in sync with BUS clock
 285 *
 286 *  This function does the phase adjustment between VPM and BUS clock
 287 *
 288 *  @return >= 0 : On success ( # of adjustment required )
 289 *            -1 : On failure
 290 */
 291 /****************************************************************************/
 292 int chipcHw_vpmPhaseAlign(void);
 293
 294 /****************************************************************************/
 295 /**
 296 *  @brief   Enables core a clock of a certain device
 297 *
 298 *  This function enables a core clock
 299 *
 300 *  @return  void
 301 *
 302 *  @note    Doesnot affect the bus interface clock
 303 */
 304 /****************************************************************************/
 305 static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /*  [ IN ] Configurable clock */
 306     );
 307
 308 /****************************************************************************/
 309 /**
 310 *  @brief   Disabled a core clock of a certain device
 311 *
 312 *  This function disables a core clock
 313 *
 314 *  @return  void
 315 *
 316 *  @note    Doesnot affect the bus interface clock
 317 */
 318 /****************************************************************************/
 319 static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock        /*  [ IN ] Configurable clock */
 320     );
 321
 322 /****************************************************************************/
 323 /**
 324 *  @brief   Enables bypass clock of a certain device
 325 *
 326 *  This function enables bypass clock
 327 *
 328 *  @note    Doesnot affect the bus interface clock
 329 */
 330 /****************************************************************************/
 331 static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock      /*  [ IN ] Configurable clock */
 332     );
 333
 334 /****************************************************************************/
 335 /**
 336 *  @brief   Disabled bypass clock of a certain device
 337 *
 338 *  This function disables bypass clock
 339 *
 340 *  @note    Doesnot affect the bus interface clock
 341 */
 342 /****************************************************************************/
 343 static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock     /*  [ IN ] Configurable clock */
 344     );
 345
 346 /****************************************************************************/
 347 /**
 348 *  @brief   Get Numeric Chip ID
 349 *
 350 *  This function returns Chip ID that includes the revison number
 351 *
 352 *  @return  Complete numeric Chip ID
 353 *
 354 */
 355 /****************************************************************************/
 356 static inline uint32_t chipcHw_getChipId(void);
 357
 358 /****************************************************************************/
 359 /**
 360 *  @brief   Get Chip Product ID
 361 *
 362 *  This function returns Chip Product ID
 363 *
 364 *  @return  Chip Product ID
 365 */
 366 /****************************************************************************/
 367 static inline uint32_t chipcHw_getChipProductId(void);
 368
 369 /****************************************************************************/
 370 /**
 371 *  @brief   Get revision number
 372 *
 373 *  This function returns revision number of the chip
 374 *
 375 *  @return  Revision number
 376 */
 377 /****************************************************************************/
 378 static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
 379
 380 /****************************************************************************/
 381 /**
 382 *  @brief   Enables bus interface clock
 383 *
 384 *  Enables  bus interface clock of various device
 385 *
 386 *  @return  void
 387 *
 388 *  @note    use chipcHw_REG_BUS_CLOCK_XXXX
 389 */
 390 /****************************************************************************/
 391 static inline void chipcHw_busInterfaceClockEnable(uint32_t mask        /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
 392     );
 393
 394 /****************************************************************************/
 395 /**
 396 *  @brief   Disables bus interface clock
 397 *
 398 *  Disables  bus interface clock of various device
 399 *
 400 *  @return  void
 401 *
 402 *  @note    use chipcHw_REG_BUS_CLOCK_XXXX
 403 */
 404 /****************************************************************************/
 405 static inline void chipcHw_busInterfaceClockDisable(uint32_t mask       /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
 406     );
 407
 408 /****************************************************************************/
 409 /**
 410 *  @brief   Enables various audio channels
 411 *
 412 *  Enables audio channel
 413 *
 414 *  @return  void
 415 *
 416 *  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
 417 */
 418 /****************************************************************************/
 419 static inline void chipcHw_audioChannelEnable(uint32_t mask     /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
 420     );
 421
 422 /****************************************************************************/
 423 /**
 424 *  @brief   Disables various audio channels
 425 *
 426 *  Disables audio channel
 427 *
 428 *  @return  void
 429 *
 430 *  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
 431 */
 432 /****************************************************************************/
 433 static inline void chipcHw_audioChannelDisable(uint32_t mask    /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
 434     );
 435
 436 /****************************************************************************/
 437 /**
 438 *  @brief    Soft resets devices
 439 *
 440 *  Soft resets various devices
 441 *
 442 *  @return   void
 443 *
 444 *  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
 445 */
 446 /****************************************************************************/
 447 static inline void chipcHw_softReset(uint64_t mask      /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
 448     );
 449
 450 static inline void chipcHw_softResetDisable(uint64_t mask       /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
 451     );
 452
 453 static inline void chipcHw_softResetEnable(uint64_t mask        /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
 454     );
 455
 456 /****************************************************************************/
 457 /**
 458 *  @brief    Configures misc CHIP functionality
 459 *
 460 *  Configures CHIP functionality
 461 *
 462 *  @return   void
 463 *
 464 *  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
 465 */
 466 /****************************************************************************/
 467 static inline void chipcHw_miscControl(uint32_t mask    /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
 468     );
 469
 470 static inline void chipcHw_miscControlDisable(uint32_t mask     /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
 471     );
 472
 473 static inline void chipcHw_miscControlEnable(uint32_t mask      /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
 474     );
 475
 476 /****************************************************************************/
 477 /**
 478 *  @brief    Set OTP options
 479 *
 480 *  Set OTP options
 481 *
 482 *  @return   void
 483 *
 484 *  @note     use chipcHw_REG_OTP_XXXXXX
 485 */
 486 /****************************************************************************/
 487 static inline void chipcHw_setOTPOption(uint64_t mask   /*  [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
 488     );
 489
 490 /****************************************************************************/
 491 /**
 492 *  @brief    Get sticky bits
 493 *
 494 *  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
 495 *
 496 */
 497 /****************************************************************************/
 498 static inline uint32_t chipcHw_getStickyBits(void);
 499
 500 /****************************************************************************/
 501 /**
 502 *  @brief    Set sticky bits
 503 *
 504 *  @return   void
 505 *
 506 *  @note     use chipcHw_REG_STICKY_XXXXXX
 507 */
 508 /****************************************************************************/
 509 static inline void chipcHw_setStickyBits(uint32_t mask  /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
 510     );
 511
 512 /****************************************************************************/
 513 /**
 514 *  @brief    Clear sticky bits
 515 *
 516 *  @return   void
 517 *
 518 *  @note     use chipcHw_REG_STICKY_XXXXXX
 519 */
 520 /****************************************************************************/
 521 static inline void chipcHw_clearStickyBits(uint32_t mask        /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
 522     );
 523
 524 /****************************************************************************/
 525 /**
 526 *  @brief    Get software override strap options
 527 *
 528 *  Retrieves software override strap options
 529 *
 530 *  @return   Software override strap value
 531 *
 532 */
 533 /****************************************************************************/
 534 static inline uint32_t chipcHw_getSoftStraps(void);
 535
 536 /****************************************************************************/
 537 /**
 538 *  @brief    Set software override strap options
 539 *
 540 *  set software override strap options
 541 *
 542 *  @return   nothing
 543 *
 544 */
 545 /****************************************************************************/
 546 static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
 547
 548 /****************************************************************************/
 549 /**
 550 *  @brief    Get pin strap options
 551 *
 552 *  Retrieves pin strap options
 553 *
 554 *  @return   Pin strap value
 555 *
 556 */
 557 /****************************************************************************/
 558 static inline uint32_t chipcHw_getPinStraps(void);
 559
 560 /****************************************************************************/
 561 /**
 562 *  @brief    Get valid pin strap options
 563 *
 564 *  Retrieves valid pin strap options
 565 *
 566 *  @return   valid Pin strap value
 567 *
 568 */
 569 /****************************************************************************/
 570 static inline uint32_t chipcHw_getValidStraps(void);
 571
 572 /****************************************************************************/
 573 /**
 574 *  @brief    Initialize valid pin strap options
 575 *
 576 *  Retrieves valid pin strap options by copying HW strap options to soft register
 577 *  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
 578 *
 579 *  @return   nothing
 580 *
 581 */
 582 /****************************************************************************/
 583 static inline void chipcHw_initValidStraps(void);
 584
 585 /****************************************************************************/
 586 /**
 587 *  @brief   Get status (enabled/disabled) of bus interface clock
 588 *
 589 *  This function returns the status of devices' bus interface clock
 590 *
 591 *  @return  Bus interface clock
 592 *
 593 */
 594 /****************************************************************************/
 595 static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
 596
 597 /****************************************************************************/
 598 /**
 599 *  @brief   Get boot device
 600 *
 601 *  This function returns the device type used in booting the system
 602 *
 603 *  @return  Boot device of type chipcHw_BOOT_DEVICE_e
 604 *
 605 */
 606 /****************************************************************************/
 607 static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
 608
 609 /****************************************************************************/
 610 /**
 611 *  @brief   Get boot mode
 612 *
 613 *  This function returns the way the system was booted
 614 *
 615 *  @return  Boot mode of type chipcHw_BOOT_MODE_e
 616 *
 617 */
 618 /****************************************************************************/
 619 static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
 620
 621 /****************************************************************************/
 622 /**
 623 *  @brief   Get NAND flash page size
 624 *
 625 *  This function returns the NAND device page size
 626 *
 627 *  @return  Boot NAND device page size
 628 *
 629 */
 630 /****************************************************************************/
 631 static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
 632
 633 /****************************************************************************/
 634 /**
 635 *  @brief   Get NAND flash address cycle configuration
 636 *
 637 *  This function returns the NAND flash address cycle configuration
 638 *
 639 *  @return  0 = Do not extra address cycle, 1 = Add extra cycle
 640 *
 641 */
 642 /****************************************************************************/
 643 static inline int chipcHw_getNandExtraCycle(void);
 644
 645 /****************************************************************************/
 646 /**
 647 *  @brief   Activates PIF interface
 648 *
 649 *  This function activates PIF interface by taking control of LCD pins
 650 *
 651 *  @note
 652 *       When activated, LCD pins will be defined as follows for PIF operation
 653 *
 654 *       CLD[17:0]  = pif_data[17:0]
 655 *       CLD[23:18] = pif_address[5:0]
 656 *       CLPOWER    = pif_wr_str
 657 *       CLCP       = pif_rd_str
 658 *       CLAC       = pif_hat1
 659 *       CLFP       = pif_hrdy1
 660 *       CLLP       = pif_hat2
 661 *       GPIO[42]   = pif_hrdy2
 662 *
 663 *       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
 664 *
 665 */
 666 /****************************************************************************/
 667 static inline void chipcHw_activatePifInterface(void);
 668
 669 /****************************************************************************/
 670 /**
 671 *  @brief   Activates LCD interface
 672 *
 673 *  This function activates LCD interface
 674 *
 675 *  @note
 676 *       When activated, LCD pins will be defined as follows
 677 *
 678 *       CLD[17:0]  = LCD data
 679 *       CLD[23:18] = LCD data
 680 *       CLPOWER    = LCD power
 681 *       CLCP       =
 682 *       CLAC       = LCD ack
 683 *       CLFP       =
 684 *       CLLP       =
 685 */
 686 /****************************************************************************/
 687 static inline void chipcHw_activateLcdInterface(void);
 688
 689 /****************************************************************************/
 690 /**
 691 *  @brief   Deactivates PIF/LCD interface
 692 *
 693 *  This function deactivates PIF/LCD interface
 694 *
 695 *  @note
 696 *       When deactivated LCD pins will be in rti-stated
 697 *
 698 */
 699 /****************************************************************************/
 700 static inline void chipcHw_deactivatePifLcdInterface(void);
 701
 702 /****************************************************************************/
 703 /**
 704 *  @brief   Get to know the configuration of GPIO pin
 705 *
 706 */
 707 /****************************************************************************/
 708 static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin        /* GPIO Pin number */
 709     );
 710
 711 /****************************************************************************/
 712 /**
 713 *  @brief   Configure GPIO pin function
 714 *
 715 */
 716 /****************************************************************************/
 717 static inline void chipcHw_setGpioPinFunction(int pin,  /* GPIO Pin number */
 718                                               chipcHw_GPIO_FUNCTION_e func      /* Configuration function */
 719     );
 720
 721 /****************************************************************************/
 722 /**
 723 *  @brief   Set Pin slew rate
 724 *
 725 *  This function sets the slew of individual pin
 726 *
 727 */
 728 /****************************************************************************/
 729 static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
 730                                           chipcHw_PIN_SLEW_RATE_e slewRate      /* Pin slew rate */
 731     );
 732
 733 /****************************************************************************/
 734 /**
 735 *  @brief   Set Pin output drive current
 736 *
 737 *  This function sets output drive current of individual pin
 738 *
 739 *  Note: Avoid the use of the word 'current' since linux headers define this
 740 *        to be the current task.
 741 */
 742 /****************************************************************************/
 743 static inline void chipcHw_setPinOutputCurrent(uint32_t pin,    /* Pin of type chipcHw_PIN_XXXXX */
 744                                                chipcHw_PIN_CURRENT_STRENGTH_e curr      /* Pin current rating */
 745     );
 746
 747 /****************************************************************************/
 748 /**
 749 *  @brief   Set Pin pullup register
 750 *
 751 *  This function sets pullup register of individual  pin
 752 *
 753 */
 754 /****************************************************************************/
 755 static inline void chipcHw_setPinPullup(uint32_t pin,   /* Pin of type chipcHw_PIN_XXXXX */
 756                                         chipcHw_PIN_PULL_e pullup       /* Pullup register settings */
 757     );
 758
 759 /****************************************************************************/
 760 /**
 761 *  @brief   Set Pin input type
 762 *
 763 *  This function sets input type of individual Pin
 764 *
 765 */
 766 /****************************************************************************/
 767 static inline void chipcHw_setPinInputType(uint32_t pin,        /* Pin of type chipcHw_PIN_XXXXX */
 768                                            chipcHw_PIN_INPUTTYPE_e inputType    /* Pin input type */
 769     );
 770
 771 /****************************************************************************/
 772 /**
 773 *  @brief   Retrieves a string representation of the mux setting for a pin.
 774 *
 775 *  @return  Pointer to a character string.
 776 */
 777 /****************************************************************************/
 778
 779 const char *chipcHw_getGpioPinFunctionStr(int pin);
 780
 781 /****************************************************************************/
 782 /**  @brief issue warmReset
 783  */
 784 /****************************************************************************/
 785 void chipcHw_reset(uint32_t mask);
 786
 787 /****************************************************************************/
 788 /**  @brief clock reconfigure
 789  */
 790 /****************************************************************************/
 791 void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
 792                            uint32_t ddrRatio);
 793
 794 /****************************************************************************/
 795 /**
 796 *  @brief   Enable Spread Spectrum
 797 *
 798 *  @note chipcHw_Init() must be called earlier
 799 */
 800 /****************************************************************************/
 801 static inline void chipcHw_enableSpreadSpectrum(void);
 802
 803 /****************************************************************************/
 804 /**
 805 *  @brief   Disable Spread Spectrum
 806 *
 807 */
 808 /****************************************************************************/
 809 static inline void chipcHw_disableSpreadSpectrum(void);
 810
 811 /****************************************************************************/
 812 /**  @brief Checks if software strap is enabled
 813  *
 814  *   @return 1 : When enable
 815  *           0 : When disable
 816  */
 817 /****************************************************************************/
 818 static inline int chipcHw_isSoftwareStrapsEnable(void);
 819
 820 /****************************************************************************/
 821 /**  @brief Enable software strap
 822  */
 823 /****************************************************************************/
 824 static inline void chipcHw_softwareStrapsEnable(void);
 825
 826 /****************************************************************************/
 827 /**  @brief Disable software strap
 828  */
 829 /****************************************************************************/
 830 static inline void chipcHw_softwareStrapsDisable(void);
 831
 832 /****************************************************************************/
 833 /**  @brief PLL test enable
 834  */
 835 /****************************************************************************/
 836 static inline void chipcHw_pllTestEnable(void);
 837
 838 /****************************************************************************/
 839 /**  @brief PLL2 test enable
 840  */
 841 /****************************************************************************/
 842 static inline void chipcHw_pll2TestEnable(void);
 843
 844 /****************************************************************************/
 845 /**  @brief PLL test disable
 846  */
 847 /****************************************************************************/
 848 static inline void chipcHw_pllTestDisable(void);
 849
 850 /****************************************************************************/
 851 /**  @brief PLL2 test disable
 852  */
 853 /****************************************************************************/
 854 static inline void chipcHw_pll2TestDisable(void);
 855
 856 /****************************************************************************/
 857 /**  @brief Get PLL test status
 858  */
 859 /****************************************************************************/
 860 static inline int chipcHw_isPllTestEnable(void);
 861
 862 /****************************************************************************/
 863 /**  @brief Get PLL2 test status
 864  */
 865 /****************************************************************************/
 866 static inline int chipcHw_isPll2TestEnable(void);
 867
 868 /****************************************************************************/
 869 /**  @brief PLL test select
 870  */
 871 /****************************************************************************/
 872 static inline void chipcHw_pllTestSelect(uint32_t val);
 873
 874 /****************************************************************************/
 875 /**  @brief PLL2 test select
 876  */
 877 /****************************************************************************/
 878 static inline void chipcHw_pll2TestSelect(uint32_t val);
 879
 880 /****************************************************************************/
 881 /**  @brief Get PLL test selected option
 882  */
 883 /****************************************************************************/
 884 static inline uint8_t chipcHw_getPllTestSelected(void);
 885
 886 /****************************************************************************/
 887 /**  @brief Get PLL2 test selected option
 888  */
 889 /****************************************************************************/
 890 static inline uint8_t chipcHw_getPll2TestSelected(void);
 891
 892 /****************************************************************************/
 893 /**
 894 *  @brief   Enables DDR SW phase alignment interrupt
 895 */
 896 /****************************************************************************/
 897 static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
 898
 899 /****************************************************************************/
 900 /**
 901 *  @brief   Disables DDR SW phase alignment interrupt
 902 */
 903 /****************************************************************************/
 904 static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
 905
 906 /****************************************************************************/
 907 /**
 908 *  @brief   Set VPM SW phase alignment interrupt mode
 909 *
 910 *  This function sets VPM phase alignment interrupt
 911 *
 912 */
 913 /****************************************************************************/
 914 static inline void
 915 chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
 916
 917 /****************************************************************************/
 918 /**
 919 *  @brief   Enable DDR phase alignment in software
 920 *
 921 */
 922 /****************************************************************************/
 923 static inline void chipcHw_ddrSwPhaseAlignEnable(void);
 924
 925 /****************************************************************************/
 926 /**
 927 *  @brief   Disable DDR phase alignment in software
 928 *
 929 */
 930 /****************************************************************************/
 931 static inline void chipcHw_ddrSwPhaseAlignDisable(void);
 932
 933 /****************************************************************************/
 934 /**
 935 *  @brief   Enable DDR phase alignment in hardware
 936 *
 937 */
 938 /****************************************************************************/
 939 static inline void chipcHw_ddrHwPhaseAlignEnable(void);
 940
 941 /****************************************************************************/
 942 /**
 943 *  @brief   Disable DDR phase alignment in hardware
 944 *
 945 */
 946 /****************************************************************************/
 947 static inline void chipcHw_ddrHwPhaseAlignDisable(void);
 948
 949 /****************************************************************************/
 950 /**
 951 *  @brief   Enable VPM phase alignment in software
 952 *
 953 */
 954 /****************************************************************************/
 955 static inline void chipcHw_vpmSwPhaseAlignEnable(void);
 956
 957 /****************************************************************************/
 958 /**
 959 *  @brief   Disable VPM phase alignment in software
 960 *
 961 */
 962 /****************************************************************************/
 963 static inline void chipcHw_vpmSwPhaseAlignDisable(void);
 964
 965 /****************************************************************************/
 966 /**
 967 *  @brief   Enable VPM phase alignment in hardware
 968 *
 969 */
 970 /****************************************************************************/
 971 static inline void chipcHw_vpmHwPhaseAlignEnable(void);
 972
 973 /****************************************************************************/
 974 /**
 975 *  @brief   Disable VPM phase alignment in hardware
 976 *
 977 */
 978 /****************************************************************************/
 979 static inline void chipcHw_vpmHwPhaseAlignDisable(void);
 980
 981 /****************************************************************************/
 982 /**
 983 *  @brief   Set DDR phase alignment margin in hardware
 984 *
 985 */
 986 /****************************************************************************/
 987 static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin        /* Margin alinging DDR  phase */
 988     );
 989
 990 /****************************************************************************/
 991 /**
 992 *  @brief   Set VPM phase alignment margin in hardware
 993 *
 994 */
 995 /****************************************************************************/
 996 static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin        /* Margin alinging VPM  phase */
 997     );
 998
 999 /****************************************************************************/
1000 /**
1001 *  @brief   Checks DDR phase aligned status done by HW
1002 *
1003 *  @return  1: When aligned
1004 *           0: When not aligned
1005 */
1006 /****************************************************************************/
1007 static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
1008
1009 /****************************************************************************/
1010 /**
1011 *  @brief   Checks VPM phase aligned status done by HW
1012 *
1013 *  @return  1: When aligned
1014 *           0: When not aligned
1015 */
1016 /****************************************************************************/
1017 static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
1018
1019 /****************************************************************************/
1020 /**
1021 *  @brief   Get DDR phase aligned status done by HW
1022 *
1023 */
1024 /****************************************************************************/
1025 static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
1026
1027 /****************************************************************************/
1028 /**
1029 *  @brief   Get VPM phase aligned status done by HW
1030 *
1031 */
1032 /****************************************************************************/
1033 static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
1034
1035 /****************************************************************************/
1036 /**
1037 *  @brief   Get DDR phase control value
1038 *
1039 */
1040 /****************************************************************************/
1041 static inline uint32_t chipcHw_getDdrPhaseControl(void);
1042
1043 /****************************************************************************/
1044 /**
1045 *  @brief   Get VPM phase control value
1046 *
1047 */
1048 /****************************************************************************/
1049 static inline uint32_t chipcHw_getVpmPhaseControl(void);
1050
1051 /****************************************************************************/
1052 /**
1053 *  @brief   DDR phase alignment timeout count
1054 *
1055 *  @note    If HW fails to perform the phase alignment, it will trigger
1056 *           a DDR phase alignment timeout interrupt.
1057 */
1058 /****************************************************************************/
1059 static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
1060     );
1061
1062 /****************************************************************************/
1063 /**
1064 *  @brief   VPM phase alignment timeout count
1065 *
1066 *  @note    If HW fails to perform the phase alignment, it will trigger
1067 *           a VPM phase alignment timeout interrupt.
1068 */
1069 /****************************************************************************/
1070 static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
1071     );
1072
1073 /****************************************************************************/
1074 /**
1075 *  @brief   DDR phase alignment timeout interrupt enable
1076 *
1077 */
1078 /****************************************************************************/
1079 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
1080
1081 /****************************************************************************/
1082 /**
1083 *  @brief   VPM phase alignment timeout interrupt enable
1084 *
1085 */
1086 /****************************************************************************/
1087 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
1088
1089 /****************************************************************************/
1090 /**
1091 *  @brief   DDR phase alignment timeout interrupt disable
1092 *
1093 */
1094 /****************************************************************************/
1095 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
1096
1097 /****************************************************************************/
1098 /**
1099 *  @brief   VPM phase alignment timeout interrupt disable
1100 *
1101 */
1102 /****************************************************************************/
1103 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
1104
1105 /****************************************************************************/
1106 /**
1107 *  @brief   Clear DDR phase alignment timeout interrupt
1108 *
1109 */
1110 /****************************************************************************/
1111 static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
1112
1113 /****************************************************************************/
1114 /**
1115 *  @brief   Clear VPM phase alignment timeout interrupt
1116 *
1117 */
1118 /****************************************************************************/
1119 static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
1120
1121 /* ---- Private Constants and Types -------------------------------------- */
1122
1123 #endif /* CHIPC_DEF_H */