release/src-rt-6.x.4708/include/nicpci.h

   1 /*
   2  * BCM43XX PCI/E core sw API definitions.
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: nicpci.h 348160 2012-07-31 21:25:18Z $
  19  */
  20
  21 #ifndef _NICPCI_H
  22 #define _NICPCI_H
  23
  24 #if defined(BCMDHDUSB) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS))
  25 #define pcicore_find_pci_capability(a, b, c, d) (0)
  26 #define pcie_readreg(a, b, c, d) (0)
  27 #define pcie_writereg(a, b, c, d, e) (0)
  28
  29 #define pcie_clkreq(a, b, c)    (0)
  30 #define pcie_lcreg(a, b, c)     (0)
  31 #define pcie_ltrenable(a, b, c) (0)
  32
  33 #define pcicore_init(a, b, c) (0x0dadbeef)
  34 #define pcicore_deinit(a)       do { } while (0)
  35 #define pcicore_attach(a, b, c) do { } while (0)
  36 #define pcicore_hwup(a)         do { } while (0)
  37 #define pcicore_up(a, b)        do { } while (0)
  38 #define pcicore_sleep(a)        do { } while (0)
  39 #define pcicore_down(a, b)      do { } while (0)
  40
  41 #define pcie_war_ovr_aspm_update(a, b)  do { } while (0)
  42 #define pcie_power_save_enable(a, b)    do { } while (0)
  43
  44 #define pcicore_pcieserdesreg(a, b, c, d, e) (0)
  45 #define pcicore_pciereg(a, b, c, d, e) (0)
  46 #ifdef BCMDBG
  47 #define pcie_lcreg(a, b, c) (0)
  48 #define pcicore_dump(a, b)      do { } while (0)
  49 #endif
  50
  51 #define pcicore_pmecap_fast(a)  (FALSE)
  52 #define pcicore_pmeen(a)        do { } while (0)
  53 #define pcicore_pmeclr(a)       do { } while (0)
  54 #define pcicore_pmestat(a)      (FALSE)
  55 #define pcicore_pmestatclr(a)   do { } while (0)
  56 #define pcie_set_request_size(pch, size) do { } while (0)
  57 #define pcie_get_request_size(pch) (0)
  58 #define pcie_set_maxpayload_size(pch, size) do { } while (0)
  59 #define pcie_get_maxpayload_size(pch) (0)
  60 #define pcie_get_ssid(a) (0)
  61 #define pcie_get_bar0(a) (0)
  62 #define pcie_configspace_cache(a) (0)
  63 #define pcie_configspace_restore(a) (0)
  64 #define pcie_configspace_get(a, b, c) (0)
  65 #define pcie_set_L1_entry_time(a, b) do { } while (0)
  66 #define pcie_disable_TL_clk_gating(a) do { } while (0)
  67 #define pcie_get_link_speed(a) do { } while (0)
  68 #define pcie_set_error_injection(a, b) do { } while (0)
  69 #else
  70 struct sbpcieregs;
  71
  72 extern uint8 pcicore_find_pci_capability(osl_t *osh, uint8 req_cap_id,
  73                                          uchar *buf, uint32 *buflen);
  74 extern uint pcie_readreg(si_t *sih, struct sbpcieregs *pcieregs, uint addrtype, uint offset);
  75 extern uint pcie_writereg(si_t *sih, struct sbpcieregs *pcieregs, uint addrtype, uint offset,
  76                           uint val);
  77
  78 extern uint8 pcie_clkreq(void *pch, uint32 mask, uint32 val);
  79 extern uint32 pcie_lcreg(void *pch, uint32 mask, uint32 val);
  80 extern void pcie_set_L1_entry_time(void *pch, uint32 val);
  81 extern void pcie_disable_TL_clk_gating(void *pch);
  82 extern void pcie_set_error_injection(void *pch, uint32 mode);
  83 extern uint8 pcie_ltrenable(void *pch, uint32 mask, uint32 val);
  84
  85 extern void *pcicore_init(si_t *sih, osl_t *osh, void *regs);
  86 extern void pcicore_deinit(void *pch);
  87 extern void pcicore_attach(void *pch, char *pvars, int state);
  88 extern void pcicore_hwup(void *pch);
  89 extern void pcicore_up(void *pch, int state);
  90 extern void pcicore_sleep(void *pch);
  91 extern void pcicore_down(void *pch, int state);
  92
  93 extern void pcie_war_ovr_aspm_update(void *pch, uint8 aspm);
  94 extern void pcie_power_save_enable(void *pch, bool enable);
  95
  96 extern uint32 pcicore_pcieserdesreg(void *pch, uint32 mdioslave, uint32 offset,
  97                                     uint32 mask, uint32 val);
  98
  99 extern uint32 pcicore_pciereg(void *pch, uint32 offset, uint32 mask, uint32 val, uint type);
 100
 101
 102 #ifdef BCMDBG
 103 extern void pcicore_dump(void *pch, struct bcmstrbuf *b);
 104 #endif
 105
 106 extern bool pcicore_pmecap_fast(osl_t *osh);
 107 extern void pcicore_pmeen(void *pch);
 108 extern void pcicore_pmeclr(void *pch);
 109 extern void pcicore_pmestatclr(void *pch);
 110 extern bool pcicore_pmestat(void *pch);
 111 extern void pcie_set_request_size(void *pch, uint16 size);
 112 extern uint16 pcie_get_request_size(void *pch);
 113 extern void pcie_set_maxpayload_size(void *pch, uint16 size);
 114 extern uint16 pcie_get_maxpayload_size(void *pch);
 115 extern uint16 pcie_get_ssid(void *pch);
 116 extern uint32 pcie_get_bar0(void *pch);
 117 extern int pcie_configspace_cache(void* pch);
 118 extern int pcie_configspace_restore(void* pch);
 119 extern int pcie_configspace_get(void* pch, uint8 *buf, uint size);
 120 extern uint32 pcie_get_link_speed(void* pch);
 121 #endif
 122
 123 #define PCIE_MRRS_OVERRIDE(sih) \
 124         ((pi->sih->boardvendor == VENDOR_APPLE) && \
 125          ((pi->sih->boardtype == BCM94331X19) || \
 126           (pi->sih->boardtype == BCM94331X28) || \
 127           (pi->sih->boardtype == BCM94331X28B) || \
 128           (pi->sih->boardtype == BCM94331X29B) || \
 129           (pi->sih->boardtype == BCM94331X29D) || \
 130           (pi->sih->boardtype == BCM94331X19C) || \
 131           (pi->sih->boardtype == BCM94331X33)))
 132
 133 #define PCIE_DRIVE_STRENGTH_OVERRIDE(sih) \
 134         ((CHIPID((sih)->chip) == BCM4331_CHIP_ID) && \
 135          ((sih)->boardtype == BCM94331X19 || \
 136           (sih)->boardtype == BCM94331X28 || \
 137           (sih)->boardtype == BCM94331X29B || \
 138           (sih)->boardtype == BCM94331X19C))
 139 #endif  /* _NICPCI_H */