1 /* *********************************************************************
2 * Broadcom Common Firmware Environment (CFE)
4 * NS DP83815 Ethernet Driver File: dev_dp83815.c
6 *********************************************************************
8 * Copyright 2000,2001,2002,2003
9 * Broadcom Corporation. All rights reserved.
11 * This software is furnished under license and may be used and
12 * copied only in accordance with the following terms and
13 * conditions. Subject to these conditions, you may download,
14 * copy, install, use, modify and distribute modified or unmodified
15 * copies of this software in source and/or binary form. No title
16 * or ownership is transferred hereby.
18 * 1) Any source code used, modified or distributed must reproduce
19 * and retain this copyright notice and list of conditions
20 * as they appear in the source file.
22 * 2) No right is granted to use any trade name, trademark, or
23 * logo of Broadcom Corporation. The "Broadcom Corporation"
24 * name may not be used to endorse or promote products derived
25 * from this software without the prior written permission of
26 * Broadcom Corporation.
28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
40 * THE POSSIBILITY OF SUCH DAMAGE.
41 ********************************************************************* */
46 #define _SB_MAKE64(x) ((uint64_t)(x))
49 #define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
52 #include "lib_types.h"
53 #include "lib_physio.h"
54 #include "lib_malloc.h"
55 #include "lib_string.h"
56 #define blockcopy memcpy
57 #include "lib_printf.h"
58 #include "lib_queue.h"
61 #include "cfe_device.h"
62 #include "cfe_ioctl.h"
63 #include "cfe_timer.h"
64 #include "cfe_error.h"
73 /* This is a driver for the National Semiconductor DP83815 (MacPhyter)
74 10/100 MAC with integrated PHY.
76 The current version has been developed for the Netgear FA311 and
77 FA312 NICs. These include an EEPROM with automatically loaded
78 setup information that includes station address filtering.
79 Operation without such an EEPROM has not been tested.
81 This SB1250 version takes advantage of DMA coherence and uses
82 "preserve bit lanes" addresses for all accesses that cross the
85 #ifndef MACPHYTER_DEBUG
86 #define MACPHYTER_DEBUG 0
88 #ifndef MACPHYTER_TEST
89 #define MACPHYTER_TEST 0
92 /* Set IPOLL to drive processing through the pseudo-interrupt
93 dispatcher. Set XPOLL to drive processing by an external polling
94 agent. Setting both is ok. */
103 #define ENET_ADDR_LEN 6 /* size of an ethernet address */
104 #define MIN_ETHER_PACK 64 /* min size of a packet */
105 #define MAX_ETHER_PACK 1518 /* max size of a packet */
106 #define CRC_SIZE 4 /* size of CRC field */
108 /* Packet buffers. For the DP83815, an rx packet must be aligned to a
109 32-bit word boundary, and we would like it aligned to a cache line
110 boundary for performance. Also, the buffers "should" be allocated
111 in 32 byte multiples (5.3.2). */
113 #define ETH_PKTBUF_LEN (((MAX_ETHER_PACK+31)/32)*32)
116 typedef struct eth_pkt_s
{
117 queue_t next
; /* 16 */
118 uint8_t *buffer
; /* 8 */
119 uint32_t flags
; /* 4 */
120 int32_t length
; /* 4 */
121 uint8_t data
[ETH_PKTBUF_LEN
];
124 typedef struct eth_pkt_s
{
125 queue_t next
; /* 8 */
126 uint8_t *buffer
; /* 4 */
127 uint32_t flags
; /* 4 */
128 int32_t length
; /* 4 */
129 uint32_t unused
[3]; /* 12 */
130 uint8_t data
[ETH_PKTBUF_LEN
];
134 #define CACHE_ALIGN 32
135 #define ETH_PKTBUF_LINES ((sizeof(eth_pkt_t) + (CACHE_ALIGN-1))/CACHE_ALIGN)
136 #define ETH_PKTBUF_SIZE (ETH_PKTBUF_LINES*CACHE_ALIGN)
137 #define ETH_PKTBUF_OFFSET (offsetof(eth_pkt_t, data))
139 #define ETH_PKT_BASE(data) ((eth_pkt_t *)((data) - ETH_PKTBUF_OFFSET))
142 #define ETH_TX_SETUP 1 /* assumes Perfect Filtering format */
145 show_packet(char c
, eth_pkt_t
*pkt
)
148 int n
= (pkt
->length
< 32 ? pkt
->length
: 32);
150 xprintf("%c[%4d]:", c
, pkt
->length
);
151 for (i
= 0; i
< n
; i
++) {
154 xprintf("%02x", pkt
->buffer
[i
]);
160 /* Descriptor structures. NOTE: To avoid having descriptors straddle
161 cache lines, we append a pad word, ignored by DMA, to each. */
163 typedef struct rx_dscr
{
166 pci_addr_t rxd_bufptr
;
170 typedef struct tx_dscr
{
173 pci_addr_t txd_bufptr
;
178 /* Driver data structures */
187 #define ETH_PKTPOOL_SIZE 32
189 typedef struct dp83815_softc
{
191 uint8_t irq
; /* interrupt mapping (used if IPOLL) */
192 pcitag_t tag
; /* tag for configuration registers */
194 uint8_t hwaddr
[ENET_ADDR_LEN
];
195 uint16_t device
; /* chip device code */
196 uint8_t revision
; /* chip revision and step */
198 eth_state_t state
; /* current state */
199 uint32_t intmask
; /* interrupt mask */
201 /* These fields are set before calling dp83815_hwinit */
202 int linkspeed
; /* encodings from cfe_ioctl */
205 /* Packet free list */
210 /* The descriptor tables */
211 uint8_t *rxdscrmem
; /* receive descriptors */
212 uint8_t *txdscrmem
; /* transmit descriptors */
214 /* These fields keep track of where we are in tx/rx processing */
215 volatile rx_dscr
*rxdscr_start
; /* beginning of ring */
216 volatile rx_dscr
*rxdscr_end
; /* end of ring */
217 volatile rx_dscr
*rxdscr_remove
; /* next one we expect DMA to use */
218 volatile rx_dscr
*rxdscr_add
; /* next place to put a buffer */
221 volatile tx_dscr
*txdscr_start
; /* beginning of ring */
222 volatile tx_dscr
*txdscr_end
; /* end of ring */
223 volatile tx_dscr
*txdscr_remove
; /* next one we will use for tx */
224 volatile tx_dscr
*txdscr_add
; /* next place to put a buffer */
226 cfe_devctx_t
*devctx
;
228 /* These fields describe the PHY */
237 uint32_t rx_interrupts
;
238 uint32_t tx_interrupts
;
243 /* Entry to and exit from critical sections (currently relative to
244 interrupts only, not SMP) */
247 #define CS_ENTER(sc) cfe_disable_irq(sc->irq)
248 #define CS_EXIT(sc) cfe_enable_irq(sc->irq)
250 #define CS_ENTER(sc) ((void)0)
251 #define CS_EXIT(sc) ((void)0)
255 /* Driver parameterization */
264 static void dp83815_ether_probe(cfe_driver_t
*drv
,
265 unsigned long probe_a
, unsigned long probe_b
,
269 /* Address mapping macros */
271 /* Note that PTR_TO_PHYS only works with 32-bit addresses, but then
272 so does the dp83815. */
273 #define PTR_TO_PHYS(x) (K0_TO_PHYS((uintptr_t)(x)))
274 #define PHYS_TO_PTR(a) ((uint8_t *)PHYS_TO_K0(a))
276 /* All mappings through the PCI host bridge use match bits mode. */
277 #define PHYS_TO_PCI(a) ((uint32_t) (a) | 0x20000000)
278 #define PCI_TO_PHYS(a) ((uint32_t) (a) & 0x1FFFFFFF)
280 #define PCI_TO_PTR(a) (PHYS_TO_PTR(PCI_TO_PHYS(a)))
281 #define PTR_TO_PCI(x) (PHYS_TO_PCI(PTR_TO_PHYS(x)))
283 #define READCSR(sc,csr) phys_read32((sc)->membase + (csr))
284 #define WRITECSR(sc,csr,val) phys_write32((sc)->membase + (csr), (val))
287 #define RESET_ADAPTER(sc) \
296 dumpstat(dp83815_softc
*sc
)
298 xprintf("-- CR = %08X CFG = %08x\n",
299 READCSR(sc
, R_CR
), READCSR(sc
, R_CFG
));
303 dumpcsrs(dp83815_softc
*sc
)
307 xprintf("-------------\n");
308 for (reg
= 0; reg
< R_MIBC
; reg
+= 4) {
309 xprintf("CSR %02X = %08X\n", reg
, READCSR(sc
, reg
));
311 xprintf("-------------\n");
315 /* Packet management */
317 /* *********************************************************************
320 * Allocate a packet from the free list.
326 * pointer to packet structure, or NULL if none available
327 ********************************************************************* */
329 eth_alloc_pkt(dp83815_softc
*sc
)
334 pkt
= (eth_pkt_t
*) q_deqnext(&sc
->freelist
);
336 if (!pkt
) return NULL
;
338 pkt
->buffer
= pkt
->data
;
339 pkt
->length
= ETH_PKTBUF_LEN
;
346 /* *********************************************************************
347 * ETH_FREE_PKT(sc,pkt)
349 * Return a packet to the free list
352 * sc - sbmac structure
353 * pkt - packet to return
357 ********************************************************************* */
359 eth_free_pkt(dp83815_softc
*sc
, eth_pkt_t
*pkt
)
362 q_enqueue(&sc
->freelist
, &pkt
->next
);
367 /* *********************************************************************
368 * ETH_INITFREELIST(sc)
370 * Initialize the buffer free list for this mac. The memory
371 * allocated to the free list is carved up and placed on a linked
372 * list of buffers for use by the mac.
379 ********************************************************************* */
381 eth_initfreelist(dp83815_softc
*sc
)
387 q_init(&sc
->freelist
);
390 for (idx
= 0; idx
< ETH_PKTPOOL_SIZE
; idx
++) {
391 pkt
= (eth_pkt_t
*) ptr
;
392 eth_free_pkt(sc
, pkt
);
393 ptr
+= ETH_PKTBUF_SIZE
;
401 dp83815_devname(dp83815_softc
*sc
)
403 return (sc
->devctx
!= NULL
? cfe_device_name(sc
->devctx
) : "eth?");
407 /* Descriptor ring management */
410 dp83815_add_rcvbuf(dp83815_softc
*sc
, eth_pkt_t
*pkt
)
412 volatile rx_dscr
*rxd
;
413 volatile rx_dscr
*nextrxd
;
415 rxd
= sc
->rxdscr_add
;
417 /* Figure out where the next descriptor will go */
419 if (nextrxd
== sc
->rxdscr_end
) {
420 nextrxd
= sc
->rxdscr_start
;
424 * If the next one is the same as our remove pointer,
425 * the ring is considered full. (it actually has room for
426 * one more, but we reserve the remove == add case for "empty")
428 if (nextrxd
== sc
->rxdscr_remove
) return -1;
430 rxd
->rxd_bufptr
= PTR_TO_PCI(pkt
->buffer
);
431 rxd
->rxd_cmdsts
= M_DES1_INTR
| V_DES1_SIZE(ETH_PKTBUF_LEN
);
433 /* success, advance the pointer */
434 sc
->rxdscr_add
= nextrxd
;
443 dp83815_fillrxring(dp83815_softc
*sc
)
449 if (sc
->rxdscr_onring
>= MINRXRING
) {
454 pkt
= eth_alloc_pkt(sc
);
456 /* could not allocate a buffer */
459 if (dp83815_add_rcvbuf(sc
, pkt
) != 0) {
460 /* could not add buffer to ring */
461 eth_free_pkt(sc
, pkt
);
468 /* *********************************************************************
469 * DP83815_RX_CALLBACK(sc, pkt)
471 * Receive callback routine. This routine is invoked when a
472 * buffer queued for receives is filled. In this simple driver,
473 * all we do is add the packet to a per-MAC queue for later
474 * processing, and try to put a new packet in the place of the one
475 * that was removed from the queue.
479 * ptk - packet context (eth_pkt structure)
483 ********************************************************************* */
485 dp83815_rx_callback(dp83815_softc
*sc
, eth_pkt_t
*pkt
)
487 if (MACPHYTER_DEBUG
) show_packet('>', pkt
); /* debug */
490 q_enqueue(&sc
->rxqueue
, &pkt
->next
);
494 dp83815_fillrxring(sc
);
499 dp83815_procrxring(dp83815_softc
*sc
)
501 volatile rx_dscr
*rxd
;
507 rxd
= (volatile rx_dscr
*) sc
->rxdscr_remove
;
509 cmdsts
= rxd
->rxd_cmdsts
;
510 if ((cmdsts
& M_DES1_OWN
) == 0) {
511 /* end of ring, no more packets */
515 pkt
= ETH_PKT_BASE(PCI_TO_PTR(rxd
->rxd_bufptr
));
516 pkt
->length
= G_DES1_SIZE(cmdsts
) - CRC_SIZE
;
518 /* Drop error packets */
519 if (cmdsts
& M_DES1_RX_ERRORS
) {
521 if (pkt
->length
>= MIN_ETHER_PACK
- CRC_SIZE
)
522 xprintf("%s: rx error %08X\n", dp83815_devname(sc
), cmdsts
);
524 dp83815_add_rcvbuf(sc
, pkt
);
528 /* Pass up the packet */
529 dp83815_rx_callback(sc
, pkt
);
531 /* put a buffer back on the ring to replace this one */
532 newpkt
= eth_alloc_pkt(sc
);
533 if (newpkt
) dp83815_add_rcvbuf(sc
, newpkt
);
536 /* update the pointer, accounting for buffer wrap. */
538 if (rxd
== sc
->rxdscr_end
)
539 rxd
= sc
->rxdscr_start
;
541 sc
->rxdscr_remove
= (rx_dscr
*) rxd
;
550 dp83815_add_txbuf(dp83815_softc
*sc
, eth_pkt_t
*pkt
)
552 volatile tx_dscr
*txd
;
553 volatile tx_dscr
*nexttxd
;
555 txd
= sc
->txdscr_add
;
557 /* Figure out where the next descriptor will go */
559 if (nexttxd
== sc
->txdscr_end
) {
560 nexttxd
= sc
->txdscr_start
;
563 /* If the next one is the same as our remove pointer,
564 the ring is considered full. (it actually has room for
565 one more, but we reserve the remove == add case for "empty") */
567 if (nexttxd
== sc
->txdscr_remove
) return -1;
569 txd
->txd_bufptr
= PTR_TO_PCI(pkt
->buffer
);
570 txd
->txd_cmdsts
= M_DES1_INTR
| M_DES1_OWN
| V_DES1_SIZE(pkt
->length
);
572 /* success, advance the pointer */
573 sc
->txdscr_add
= nexttxd
;
580 dp83815_transmit(dp83815_softc
*sc
,eth_pkt_t
*pkt
)
584 if (MACPHYTER_DEBUG
) show_packet('<', pkt
); /* debug */
586 rv
= dp83815_add_txbuf(sc
, pkt
);
589 WRITECSR(sc
, R_CR
, M_CR_TXE
| M_CR_RXE
);
595 dp83815_proctxring(dp83815_softc
*sc
)
597 volatile tx_dscr
*txd
;
602 txd
= (volatile tx_dscr
*) sc
->txdscr_remove
;
604 if (txd
== sc
->txdscr_add
) {
605 /* ring is empty, no buffers to process */
609 cmdsts
= txd
->txd_cmdsts
;
610 if (cmdsts
& M_DES1_OWN
) {
611 /* Reached a packet still being transmitted */
615 /* Just free the packet */
616 pkt
= ETH_PKT_BASE(PCI_TO_PTR(txd
->txd_bufptr
));
617 eth_free_pkt(sc
, pkt
);
619 /* update the pointer, accounting for buffer wrap. */
621 if (txd
== sc
->txdscr_end
)
622 txd
= sc
->txdscr_start
;
624 sc
->txdscr_remove
= (tx_dscr
*) txd
;
630 dp83815_initrings(dp83815_softc
*sc
)
632 volatile tx_dscr
*txd
, *txn
;
633 volatile rx_dscr
*rxd
, *rxn
;
635 /* Claim ownership of all descriptors for the driver */
637 for (txd
= sc
->txdscr_start
; txd
!= sc
->txdscr_end
; txd
++) {
639 if (txn
== sc
->txdscr_end
) txn
= sc
->txdscr_start
;
640 txd
->txd_link
= PTR_TO_PCI(txn
);
644 for (rxd
= sc
->rxdscr_start
; rxd
!= sc
->rxdscr_end
; rxd
++) {
646 if (rxn
== sc
->rxdscr_end
) rxn
= sc
->rxdscr_start
;
647 rxd
->rxd_link
= PTR_TO_PCI(rxn
);
648 rxd
->rxd_cmdsts
= M_DES1_OWN
;
652 /* Init the ring pointers */
654 sc
->txdscr_add
= sc
->txdscr_remove
= sc
->txdscr_start
;
655 sc
->rxdscr_add
= sc
->rxdscr_remove
= sc
->rxdscr_start
;
656 sc
->rxdscr_onring
= 0;
658 /* Add stuff to the receive ring */
660 dp83815_fillrxring(sc
);
665 dp83815_init(dp83815_softc
*sc
)
667 /* Allocate descriptor rings */
668 sc
->rxdscrmem
= KMALLOC(MAXRXDSCR
*sizeof(rx_dscr
), sizeof(rx_dscr
));
669 sc
->txdscrmem
= KMALLOC(MAXTXDSCR
*sizeof(tx_dscr
), sizeof(tx_dscr
));
671 /* Allocate buffer pool */
672 sc
->pktpool
= KMALLOC(ETH_PKTPOOL_SIZE
*ETH_PKTBUF_SIZE
, CACHE_ALIGN
);
673 eth_initfreelist(sc
);
674 q_init(&sc
->rxqueue
);
676 /* Fill in pointers to the rings */
677 sc
->rxdscr_start
= (rx_dscr
*) (sc
->rxdscrmem
);
678 sc
->rxdscr_end
= sc
->rxdscr_start
+ MAXRXDSCR
;
679 sc
->rxdscr_add
= sc
->rxdscr_start
;
680 sc
->rxdscr_remove
= sc
->rxdscr_start
;
681 sc
->rxdscr_onring
= 0;
683 sc
->txdscr_start
= (tx_dscr
*) (sc
->txdscrmem
);
684 sc
->txdscr_end
= sc
->txdscr_start
+ MAXTXDSCR
;
685 sc
->txdscr_add
= sc
->txdscr_start
;
686 sc
->txdscr_remove
= sc
->txdscr_start
;
688 dp83815_initrings(sc
);
695 dp83815_resetrings(dp83815_softc
*sc
)
697 volatile tx_dscr
*txd
;
698 volatile rx_dscr
*rxd
;
701 /* Free already-sent descriptors and buffers */
702 dp83815_proctxring(sc
);
704 /* Free any pending but unsent */
705 txd
= (volatile tx_dscr
*) sc
->txdscr_remove
;
706 while (txd
!= sc
->txdscr_add
) {
707 txd
->txd_cmdsts
&=~ M_DES1_OWN
;
708 pkt
= ETH_PKT_BASE(PCI_TO_PTR(txd
->txd_bufptr
));
709 eth_free_pkt(sc
, pkt
);
712 if (txd
== sc
->txdscr_end
)
713 txd
= sc
->txdscr_start
;
715 sc
->txdscr_add
= sc
->txdscr_remove
;
717 /* Discard any received packets as well as all free buffers */
718 rxd
= (volatile rx_dscr
*) sc
->rxdscr_remove
;
719 while (rxd
!= sc
->rxdscr_add
) {
720 rxd
->rxd_cmdsts
|= M_DES1_OWN
;
721 pkt
= ETH_PKT_BASE(PCI_TO_PTR(rxd
->rxd_bufptr
));
722 eth_free_pkt(sc
, pkt
);
725 if (rxd
== sc
->rxdscr_end
)
726 rxd
= sc
->rxdscr_start
;
732 /* Reestablish the initial state. */
733 dp83815_initrings(sc
);
742 /* Current NICs use the EEPROM auto-load feature and there is no need
743 for explicit EEPROM access. The following routines are included
744 for future applications and have been tested (Netgear FA311). */
747 * The recommended EEPROM is the NM9306.
748 * Delays below are chosen to meet specs for NS93C64 (slow M variant).
749 * Current parts are faster.
750 * Reference: NS Memory Data Book, 1994
753 #define EEPROM_SIZE (2*0x0C)
754 #define EEPROM_MAX_CYCLES 32
756 #define EEPROM_CMD_BITS 3
757 #define EEPROM_ADDR_BITS 6
759 #define K_EEPROM_READ_CMD 06
760 #define K_EEPROM_WRITE_CMD 05
762 #define EEPROM_CRC_INDEX (EEPROM_SIZE-2)
764 #define EEPROM_WORD(rom,offset) ((rom)[offset] | ((rom)[offset+1] << 8))
767 eeprom_idle_state(dp83815_softc
*sc
)
772 ctrl
= READCSR(sc
, R_MEAR
);
774 ctrl
|= M_MEAR_EESEL
;
775 WRITECSR(sc
, R_MEAR
, ctrl
);
776 cfe_nsleep(100); /* CS setup (Tcss=100) */
778 /* Run the clock through the maximum number of pending read cycles */
779 for (i
= 0; i
< EEPROM_MAX_CYCLES
*2; i
++) {
780 ctrl
^= M_MEAR_EECLK
;
781 WRITECSR(sc
, R_MEAR
, ctrl
);
782 cfe_nsleep(1000); /* SK period (Fsk=0.5MHz) */
785 /* Deassert EEPROM Chip Select */
786 ctrl
&=~ M_MEAR_EESEL
;
787 WRITECSR(sc
, R_MEAR
, ctrl
);
788 cfe_nsleep(50); /* CS recovery (Tsks=50) */
792 eeprom_send_command_bit(dp83815_softc
*sc
, unsigned int data
)
796 ctrl
= READCSR(sc
, R_MEAR
);
798 /* Place the data bit on the bus */
802 ctrl
&=~ M_MEAR_EEDI
;
804 WRITECSR(sc
, R_MEAR
, ctrl
);
805 cfe_nsleep(360); /* setup: Tdis=200 */
807 /* Now clock the data into the EEPROM */
808 WRITECSR(sc
, R_MEAR
, ctrl
| M_MEAR_EECLK
);
809 cfe_nsleep(900); /* clock high, Tskh=500 */
810 WRITECSR(sc
, R_MEAR
, ctrl
);
811 cfe_nsleep(450); /* clock low, Tskl=250 */
813 /* Now clear the data bit */
814 ctrl
&=~ M_MEAR_EEDI
; /* data invalid, Tidh=20 for SK^ */
815 WRITECSR(sc
, R_MEAR
, ctrl
);
816 cfe_nsleep(270); /* min cycle, 1/Fsk=2000 */
820 eeprom_read_bit(dp83815_softc
*sc
)
824 ctrl
= READCSR(sc
, R_MEAR
);
826 /* Generate a clock cycle before doing a read */
827 WRITECSR(sc
, R_MEAR
, ctrl
| M_MEAR_EECLK
); /* rising edge */
828 cfe_nsleep(1000); /* clock high, Tskh=500, Tpd=1000 */
829 WRITECSR(sc
, R_MEAR
, ctrl
); /* falling edge */
830 cfe_nsleep(1000); /* clock low, 1/Fsk=2000 */
832 ctrl
= READCSR(sc
, R_MEAR
);
833 return ((ctrl
& M_MEAR_EEDO
) != 0 ? 1 : 0);
836 #define CMD_BIT_MASK (1 << (EEPROM_CMD_BITS+EEPROM_ADDR_BITS-1))
839 eeprom_read_word(dp83815_softc
*sc
, unsigned int index
)
841 uint16_t command
, word
;
845 ctrl
= READCSR(sc
, R_MEAR
) | M_MEAR_EESEL
;
847 /* Assert the EEPROM CS line */
848 WRITECSR(sc
, R_MEAR
, ctrl
);
849 cfe_nsleep(100); /* CS setup, Tcss = 100 */
851 /* Send the read command to the EEPROM */
852 command
= (K_EEPROM_READ_CMD
<< EEPROM_ADDR_BITS
) | index
;
853 for (i
= 0; i
< EEPROM_CMD_BITS
+EEPROM_ADDR_BITS
; i
++) {
854 eeprom_send_command_bit(sc
, (command
& CMD_BIT_MASK
) != 0 ? 1 : 0);
858 /* Now read the bits from the EEPROM (MSB first) */
860 for (i
= 0; i
< 16; ++i
) {
862 word
|= eeprom_read_bit(sc
);
865 /* Clear the EEPROM CS Line, CS hold, Tcsh = 0 */
866 WRITECSR(sc
, R_MEAR
, ctrl
&~ M_MEAR_EESEL
);
872 /****************************************************************************
875 * Calculate the checksum of the EEPROM and return it. See Section
876 * 4.2.4 for the algorithm.
877 ***************************************************************************/
880 eeprom_checksum(const uint8_t rom
[])
886 for (i
= 0; i
< EEPROM_SIZE
-1; i
++)
889 return (((sum
+ 1) & 0xFF) << 8) | 0x55;
893 /****************************************************************************
894 * eeprom_read_all(sc, uint8_t dest)
896 * Read the entire EEPROM into the srom array
900 ***************************************************************************/
903 eeprom_read_all(dp83815_softc
*sc
, uint8_t dest
[])
906 uint16_t cksum
, temp
;
908 WRITECSR(sc
, R_MEAR
, M_MEAR_EESEL
);
910 eeprom_idle_state(sc
);
912 for (i
= 0; i
< EEPROM_SIZE
/2; i
++) {
913 temp
= eeprom_read_word(sc
, i
);
914 dest
[2*i
] = temp
& 0xFF;
915 dest
[2*i
+1] = temp
>> 8;
918 WRITECSR(sc
, R_MEAR
, 0); /* CS hold, Tcsh=0 */
920 cksum
= eeprom_checksum(dest
);;
921 if (cksum
!= EEPROM_WORD(dest
, EEPROM_CRC_INDEX
)) {
922 xprintf("%s: Invalid EEPROM CHECKSUM, calc %04x, stored %04x\n",
924 cksum
, EEPROM_WORD(dest
, EEPROM_CRC_INDEX
));
931 eeprom_read_addr(const uint8_t rom
[], uint8_t buf
[])
934 unsigned offset
, mask
;
937 if (eeprom_checksum(rom
) != EEPROM_WORD(rom
, EEPROM_SIZE
-2))
941 offset
= 2*6; mask
= 0x1;
945 if ((EEPROM_WORD(rom
, offset
) & mask
) != 0) s
|= 0x8000;
948 offset
+=2; mask
= 0x8000;
956 } while (i
< ENET_ADDR_LEN
*8);
960 #endif /* MACPHYTER_TEST */
962 #define eeprom_dump(srom)
966 dp83815_get_pm_addr(dp83815_softc
*sc
, uint8_t buf
[])
973 rfcr
= READCSR(sc
, R_RFCR
);
974 rfaddr
= K_RFCR_PMATCH_ADDR
;
976 for (i
= 0; i
< ENET_ADDR_LEN
/2; i
++) {
977 rfcr
&=~ M_RFCR_RFADDR
;
978 rfcr
|= V_RFCR_RFADDR(rfaddr
);
979 WRITECSR(sc
, R_RFCR
, rfcr
);
980 rfdata
= READCSR(sc
, R_RFDR
);
981 buf
[2*i
] = rfdata
& 0xFF;
982 buf
[2*i
+1] = (rfdata
>> 8) & 0xFF;
993 /* Current NICs use the internal PHY, which can be accessed more
994 simply via internal registers. The following routines are
995 primarily for management access to an external PHY and are retained
996 for future applications. They have been tested on a Netgear FA311. */
998 /****************************************************************************
999 * MII access utility routines
1000 ***************************************************************************/
1002 /* MII clock limited to 2.5 MHz (DP83815 allows 25 MHz), transactions
1003 end with MDIO tristated */
1006 mii_write_bits(dp83815_softc
*sc
, uint32_t data
, unsigned int count
)
1011 ctrl
= READCSR(sc
, R_MEAR
) & ~M_MEAR_MDC
;
1012 ctrl
|= M_MEAR_MDDIR
;
1014 for (bitmask
= 1 << (count
-1); bitmask
!= 0; bitmask
>>= 1) {
1015 ctrl
&=~ M_MEAR_MDIO
;
1016 if ((data
& bitmask
) != 0) ctrl
|= M_MEAR_MDIO
;
1017 WRITECSR(sc
, R_MEAR
, ctrl
);
1019 cfe_nsleep(2000); /* setup */
1020 WRITECSR(sc
, R_MEAR
, ctrl
| M_MEAR_MDC
);
1021 cfe_nsleep(2000); /* hold */
1022 WRITECSR(sc
, R_MEAR
, ctrl
);
1027 mii_turnaround(dp83815_softc
*sc
)
1031 ctrl
= READCSR(sc
, R_MEAR
) &~ M_MEAR_MDDIR
;
1033 /* stop driving data */
1034 WRITECSR(sc
, R_MEAR
, ctrl
);
1035 cfe_nsleep(2000); /* setup */
1036 WRITECSR(sc
, R_MEAR
, ctrl
| M_MEAR_MDC
);
1037 cfe_nsleep(2000); /* clock high */
1038 WRITECSR(sc
, R_MEAR
, ctrl
);
1040 /* read back and check for 0 here? */
1043 /****************************************************************************
1046 * This routine reads a register from the PHY chip using the MII
1047 * serial management interface.
1050 * index - index of register to read (0-31)
1053 * word read from register
1054 ***************************************************************************/
1057 mii_read_register(dp83815_softc
*sc
, unsigned int index
)
1059 /* Send the command and address to the PHY. The sequence is
1060 a synchronization sequence (32 1 bits)
1061 a "start" command (2 bits)
1062 a "read" command (2 bits)
1063 the PHY addr (5 bits)
1064 the register index (5 bits)
1070 mii_write_bits(sc
, 0xFF, 8);
1071 mii_write_bits(sc
, 0xFFFFFFFF, 32);
1072 mii_write_bits(sc
, MII_COMMAND_START
, 2);
1073 mii_write_bits(sc
, MII_COMMAND_READ
, 2);
1074 mii_write_bits(sc
, sc
->phy_addr
, 5);
1075 mii_write_bits(sc
, index
, 5);
1079 ctrl
= READCSR(sc
, R_MEAR
) &~ (M_MEAR_MDC
| M_MEAR_MDDIR
);
1082 for (i
= 0; i
< 16; i
++) {
1083 WRITECSR(sc
, R_MEAR
, ctrl
);
1084 cfe_nsleep(2000); /* clock width low */
1085 WRITECSR(sc
, R_MEAR
, ctrl
| M_MEAR_MDC
);
1086 cfe_nsleep(2000); /* clock width high */
1087 WRITECSR(sc
, R_MEAR
, ctrl
);
1088 cfe_nsleep(1000); /* output delay */
1090 if ((READCSR(sc
, R_MEAR
) & M_MEAR_MDIO
) != 0)
1096 /* reset to output mode? */
1099 /****************************************************************************
1100 * mii_write_register
1102 * This routine writes a register in the PHY chip using the MII
1103 * serial management interface.
1106 * index - index of register to write (0-31)
1107 * value - word to write
1108 ***************************************************************************/
1111 mii_write_register(dp83815_softc
*sc
, unsigned int index
, uint16_t value
)
1113 mii_write_bits(sc
, 0xFF, 8);
1114 mii_write_bits(sc
, 0xFFFFFFFF, 32);
1115 mii_write_bits(sc
, MII_COMMAND_START
, 2);
1116 mii_write_bits(sc
, MII_COMMAND_WRITE
, 2);
1117 mii_write_bits(sc
, sc
->phy_addr
, 5);
1118 mii_write_bits(sc
, index
, 5);
1119 mii_write_bits(sc
, MII_COMMAND_ACK
, 2);
1120 mii_write_bits(sc
, value
, 16);
1122 /* reset to input mode? */
1127 mii_probe(dp83815_softc
*sc
)
1132 /* Empirically, bit-banged access will return register 0 of the
1133 integrated PHY for all registers of all unpopulated PHY
1135 for (i
= 0; i
< 32; i
++) {
1137 id1
= mii_read_register(sc
, MII_PHYIDR1
);
1138 id2
= mii_read_register(sc
, MII_PHYIDR2
);
1139 if ((id1
!= 0x0000 && id1
!= 0xFFFF) ||
1140 (id2
!= 0x0000 && id2
!= 0xFFFF)) {
1141 if (id1
!= id2
) return 0;
1147 #define mii_dump(sc,label)
1150 /* The following functions are suitable for explicit MII access. */
1153 mii_set_speed(dp83815_softc
*sc
, int speed
)
1157 control
= mii_read_register(sc
, MII_BMCR
);
1159 control
&=~ (BMCR_ANENABLE
| BMCR_RESTARTAN
);
1160 mii_write_register(sc
, MII_BMCR
, control
);
1161 control
&=~ (BMCR_SPEED0
| BMCR_SPEED1
| BMCR_DUPLEX
);
1164 case ETHER_SPEED_10HDX
:
1167 case ETHER_SPEED_10FDX
:
1168 control
|= BMCR_DUPLEX
;
1170 case ETHER_SPEED_100HDX
:
1171 control
|= BMCR_SPEED100
;
1173 case ETHER_SPEED_100FDX
:
1174 control
|= BMCR_SPEED100
| BMCR_DUPLEX
;
1178 mii_write_register(sc
, MII_BMCR
, control
);
1182 mii_autonegotiate(dp83815_softc
*sc
)
1184 uint16_t control
, status
, cap
;
1188 linkspeed
= ETHER_SPEED_UNKNOWN
;
1190 /* Read twice to clear latching bits */
1191 status
= mii_read_register(sc
, MII_BMSR
);
1192 status
= mii_read_register(sc
, MII_BMSR
);
1193 mii_dump(sc
, "query PHY");
1195 if ((status
& (BMSR_AUTONEG
| BMSR_LINKSTAT
)) ==
1196 (BMSR_AUTONEG
| BMSR_LINKSTAT
))
1197 control
= mii_read_register(sc
, MII_BMCR
);
1200 mii_write_register(sc
, MII_BMCR
, BMCR_RESET
);
1203 control
= mii_read_register(sc
, MII_BMCR
);
1204 if ((control
&& BMCR_RESET
) == 0 || timeout
<= 0)
1206 cfe_sleep(CFE_HZ
/2);
1207 timeout
-= CFE_HZ
/2;
1209 if ((control
& BMCR_RESET
) != 0) {
1210 xprintf("%s: PHY reset failed\n", dp83815_devname(sc
));
1214 status
= mii_read_register(sc
, MII_BMSR
);
1215 cap
= ((status
>> 6) & (ANAR_TXFD
| ANAR_TXHD
| ANAR_10FD
| ANAR_10HD
))
1217 mii_write_register(sc
, MII_ANAR
, cap
);
1218 control
|= (BMCR_ANENABLE
| BMCR_RESTARTAN
);
1219 mii_write_register(sc
, MII_BMCR
, control
);
1223 status
= mii_read_register(sc
, MII_BMSR
);
1224 if ((status
& BMSR_ANCOMPLETE
) != 0 || timeout
<= 0)
1226 cfe_sleep(CFE_HZ
/2);
1227 timeout
-= CFE_HZ
/2;
1229 mii_dump(sc
, "done PHY");
1232 xprintf("%s: Link speed: ", dp83815_devname(sc
));
1233 if ((status
& BMSR_ANCOMPLETE
) != 0) {
1234 /* A link partner was negogiated... */
1236 uint16_t remote
= mii_read_register(sc
, MII_ANLPAR
);
1238 if ((remote
& ANLPAR_TXFD
) != 0) {
1239 xprintf("100BaseT FDX\n");
1240 linkspeed
= ETHER_SPEED_100FDX
;
1242 else if ((remote
& ANLPAR_TXHD
) != 0) {
1243 xprintf("100BaseT HDX\n");
1244 linkspeed
= ETHER_SPEED_100HDX
;
1246 else if ((remote
& ANLPAR_10FD
) != 0) {
1247 xprintf("10BaseT FDX\n");
1248 linkspeed
= ETHER_SPEED_10FDX
;
1250 else if ((remote
& ANLPAR_10HD
) != 0) {
1251 xprintf("10BaseT HDX\n");
1252 linkspeed
= ETHER_SPEED_10HDX
;
1256 /* no link partner negotiation */
1257 control
&=~ (BMCR_ANENABLE
| BMCR_RESTARTAN
);
1258 mii_write_register(sc
, MII_BMCR
, control
);
1259 xprintf("10BaseT HDX (assumed)\n");
1260 linkspeed
= ETHER_SPEED_10HDX
;
1261 if ((status
& BMSR_LINKSTAT
) == 0)
1262 mii_write_register(sc
, MII_BMCR
, control
);
1263 mii_set_speed(sc
, linkspeed
);
1266 status
= mii_read_register(sc
, MII_BMSR
); /* clear latching bits */
1267 mii_dump(sc
, "final PHY");
1269 #endif /* MACPHYTER_TEST */
1273 dp83815_phyupdate(dp83815_softc
*sc
, uint32_t status
)
1275 xprintf("%s: Link speed: ", dp83815_devname(sc
));
1276 if ((status
& M_CFG_LNKSTS
) != 0) {
1277 switch (status
& (M_CFG_SPEED100
| M_CFG_FDUP
)) {
1278 case (M_CFG_SPEED100
| M_CFG_FDUP
):
1279 sc
->linkspeed
= ETHER_SPEED_100FDX
;
1280 xprintf("100BaseT FDX\n");
1282 case (M_CFG_SPEED100
):
1283 sc
->linkspeed
= ETHER_SPEED_100HDX
;
1284 xprintf("100BaseT HDX\n");
1287 sc
->linkspeed
= ETHER_SPEED_10FDX
;
1288 xprintf("10BaseT FDX\n");
1291 sc
->linkspeed
= ETHER_SPEED_10HDX
;
1292 xprintf("10BaseT HDX\n");
1295 if ((status
& M_CFG_SPEED100
) != 0) {
1298 /* This is a reputed fix that improves 100BT rx
1299 performance on short cables with "a small number"
1300 of DP83815 chips. It comes from Bruce at NatSemi
1301 via the Soekris support web page (see appended
1304 WRITECSR(sc
, R_PGSEL
, 0x0001);
1305 (void)READCSR(sc
, R_PGSEL
); /* push */
1306 t
= READCSR(sc
, R_DSPCFG
);
1307 WRITECSR(sc
, R_DSPCFG
, (t
& 0xFFF) | 0x1000);
1309 t
= READCSR(sc
, R_TSTDAT
) & 0xFF;
1310 if ((t
& 0x0080) == 0 || ((t
> 0x00D8) && (t
<= 0x00FF))) {
1311 WRITECSR(sc
, R_TSTDAT
, 0x00E8);
1312 t
= READCSR(sc
, R_DSPCFG
);
1313 WRITECSR(sc
, R_DSPCFG
, t
| 0x0020);
1315 WRITECSR(sc
, R_PGSEL
, 0);
1317 if ((status
& M_CFG_FDUP
) != (sc
->phy_status
& M_CFG_FDUP
)) {
1318 uint32_t txcfg
, rxcfg
;
1320 txcfg
= READCSR(sc
, R_TXCFG
);
1321 rxcfg
= READCSR(sc
, R_RXCFG
);
1322 if (status
& M_CFG_FDUP
) {
1323 txcfg
|= (M_TXCFG_CSI
| M_TXCFG_HBI
);
1324 rxcfg
|= M_RXCFG_ATX
;
1327 txcfg
&= ~(M_TXCFG_CSI
| M_TXCFG_HBI
);
1328 rxcfg
&= ~M_RXCFG_ATX
;
1330 WRITECSR(sc
, R_TXCFG
, txcfg
);
1331 WRITECSR(sc
, R_RXCFG
, rxcfg
);
1335 xprintf("Unknown\n");
1338 sc
->phy_status
= status
;
1342 dp83815_hwinit(dp83815_softc
*sc
)
1344 if (sc
->state
== eth_state_uninit
) {
1346 uint32_t txcfg
, rxcfg
;
1350 /* RESET_ADAPTER(sc); */
1351 sc
->state
= eth_state_off
;
1354 cfg
= READCSR(sc
, R_CFG
);
1355 cfg
|= M_CFG_BEM
; /* We will use match bits */
1356 WRITECSR(sc
, R_CFG
, cfg
);
1359 dp83815_phyupdate(sc
, cfg
& M_CFG_LNKSUMMARY
);
1361 /* Set a maximum tx DMA burst length of 512 (128*4) bytes, a
1362 fill threshold of 512 (16*32) and a drain threshold of 64
1364 txcfg
= READCSR(sc
, R_TXCFG
);
1365 txcfg
&= ~(M_TXCFG_MXDMA
| M_TXCFG_FLTH
| M_TXCFG_DRTH
);
1366 txcfg
|= (M_TXCFG_ATP
1367 | V_TXCFG_MXDMA(K_MXDMA_512
)
1368 | V_TXCFG_FLTH(16) | V_TXCFG_DRTH(2));
1369 WRITECSR(sc
, R_TXCFG
, txcfg
);
1371 /* Set a maximum rx DMA burst length of 512 (128*4) bytes, and
1372 an rx drain threshhold of 128 (16*8) bytes */
1373 rxcfg
= READCSR(sc
, R_RXCFG
);
1374 rxcfg
&= ~(M_RXCFG_MXDMA
| M_RXCFG_DRTH
);
1375 rxcfg
|= (V_RXCFG_MXDMA(K_MXDMA_512
) | V_RXCFG_DRTH(16));
1376 WRITECSR(sc
, R_RXCFG
, rxcfg
);
1380 uint8_t srom
[EEPROM_SIZE
];
1381 uint8_t addr
[ENET_ADDR_LEN
];
1383 eeprom_read_all(sc
, srom
);
1385 xprintf(" checksum %04x\n", eeprom_checksum(srom
));
1386 if (eeprom_read_addr(srom
, addr
) == 0)
1387 xprintf(" addr: %02x-%02x-%02x-%02x-%02x-%02x\n",
1388 addr
[0], addr
[1], addr
[2], addr
[3], addr
[4], addr
[5]);
1391 xprintf("MII address %02x\n", sc
->phy_addr
);
1392 mii_dump(sc
, "DP83815 PHY:");
1393 (void)mii_autonegotiate
;
1395 #endif /* MACPHYTER_TEST */
1401 ready
|= READCSR(sc
, R_ISR
);
1402 if ((ready
& (M_INT_TXRCMP
| M_INT_RXRCMP
))
1403 == (M_INT_TXRCMP
| M_INT_RXRCMP
) || timeout
<= 0)
1405 cfe_sleep(CFE_HZ
/10);
1406 timeout
-= CFE_HZ
/10;
1408 if ((ready
& M_INT_TXRCMP
) == 0)
1409 xprintf("%s: tx reset failed\n", dp83815_devname(sc
));
1410 if ((ready
& M_INT_RXRCMP
) == 0)
1411 xprintf("%s: rx reset failed\n", dp83815_devname(sc
));
1416 dp83815_setspeed(dp83815_softc
*sc
, int speed
)
1421 dp83815_setloopback(dp83815_softc
*sc
, int mode
)
1427 dp83815_isr(void *arg
)
1429 dp83815_softc
*sc
= (dp83815_softc
*)arg
;
1439 /* Read (and clear) the interrupt status. */
1440 isr
= READCSR(sc
, R_ISR
);
1441 status
= isr
& sc
->intmask
;
1443 /* if there are no more interrupts, leave now. */
1444 if (status
== 0) break;
1446 /* Now, test each unmasked bit in the interrupt register and
1447 handle each interrupt type appropriately. */
1449 if (status
& (M_INT_RTABT
| M_INT_RMABT
)) {
1450 WRITECSR(sc
, R_IER
, 0);
1452 xprintf("%s: bus error\n", dp83815_devname(sc
));
1455 if (sc
->bus_errors
>= 2) {
1458 sc
->state
= eth_state_off
;
1463 WRITECSR(sc
, R_IMR
, sc
->intmask
);
1467 if (status
& M_INT_RXDESC
) {
1469 sc
->rx_interrupts
++;
1471 dp83815_procrxring(sc
);
1474 if (status
& M_INT_TXDESC
) {
1476 sc
->tx_interrupts
++;
1478 dp83815_proctxring(sc
);
1481 if (status
& (M_INT_TXURN
| M_INT_RXORN
)) {
1482 if (status
& M_INT_TXURN
) {
1483 xprintf("%s: tx underrun, %08x\n", dp83815_devname(sc
), isr
);
1485 if (status
& M_INT_RXORN
) {
1486 xprintf("%s: tx overrun, %08x\n", dp83815_devname(sc
), isr
);
1490 if (status
& M_INT_PHY
) {
1491 sc
->intmask
&= ~ M_INT_PHY
;
1492 WRITECSR(sc
, R_IMR
, sc
->intmask
);
1493 (void)READCSR(sc
, R_MISR
); /* Clear at PHY */
1501 dp83815_checkphy(dp83815_softc
*sc
)
1506 (void)READCSR(sc
, R_MISR
); /* Clear at PHY */
1507 cfg
= READCSR(sc
, R_CFG
);
1508 status
= cfg
& M_CFG_LNKSUMMARY
;
1509 if (status
!= sc
->phy_status
) {
1510 dp83815_phyupdate(sc
, status
);
1513 sc
->intmask
|= M_INT_PHY
;
1514 WRITECSR(sc
, R_IMR
, sc
->intmask
);
1519 dp83815_start(dp83815_softc
*sc
)
1523 /* Set up loopback here */
1526 WRITECSR(sc
, R_IER
, 0); /* no interrupts */
1527 WRITECSR(sc
, R_IMR
, 0);
1528 (void)READCSR(sc
, R_ISR
); /* clear any pending */
1530 sc
->phy_status
= READCSR(sc
, R_CFG
) & M_CFG_LNKSUMMARY
;
1533 sc
->intmask
= M_INT_RXDESC
| M_INT_TXDESC
;
1534 sc
->intmask
|= M_INT_RTABT
| M_INT_RMABT
| M_INT_RXORN
| M_INT_TXURN
;
1535 sc
->intmask
|= M_INT_PHY
;
1538 cfe_request_irq(sc
->irq
, dp83815_isr
, sc
, CFE_IRQ_FLAGS_SHARED
, 0);
1539 WRITECSR(sc
, R_IMR
, sc
->intmask
);
1540 WRITECSR(sc
, R_IER
, M_IER_IE
);
1543 (void)READCSR(sc
, R_MISR
); /* clear any pending */
1544 WRITECSR(sc
, R_MISR
, MISR_MSKJAB
| MISR_MSKRF
| MISR_MSKFHF
| MISR_MSKRHF
);
1545 WRITECSR(sc
, R_MICR
, MICR_INTEN
);
1547 WRITECSR(sc
, R_TXDP
, PTR_TO_PCI(sc
->txdscr_start
));
1548 WRITECSR(sc
, R_RXDP
, PTR_TO_PCI(sc
->rxdscr_start
));
1550 WRITECSR(sc
, R_MIBC
, M_MIBC_ACLR
); /* zero hw MIB counters */
1552 WRITECSR(sc
, R_CR
, M_CR_TXE
| M_CR_RXE
);
1553 sc
->state
= eth_state_on
;
1557 dp83815_stop(dp83815_softc
*sc
)
1562 /* Make sure that no further interrutps will be processed. */
1564 WRITECSR(sc
, R_IER
, 0);
1565 WRITECSR(sc
, R_IMR
, 0);
1568 (void)READCSR(sc
, R_IER
); /* Push */
1569 cfe_free_irq(sc
->irq
, 0);
1572 WRITECSR(sc
, R_CR
, M_CR_TXD
| M_CR_RXD
);
1574 /* wait for any DMA activity to terminate */
1575 for (count
= 0; count
<= 13; count
++) {
1576 status
= READCSR(sc
, R_CR
);
1577 if ((status
& (M_CR_TXE
| M_CR_RXE
)) == 0)
1579 cfe_sleep(CFE_HZ
/10);
1582 xprintf("%s: idle state not achieved\n", dp83815_devname(sc
));
1585 sc
->state
= eth_state_uninit
;
1586 sc
->linkspeed
= ETHER_SPEED_AUTO
;
1589 (void)READCSR(sc
, R_ISR
); /* Clear any stragglers. */
1593 /* *********************************************************************
1594 * ETH_PARSE_XDIGIT(c)
1596 * Parse a hex digit, returning its value
1602 * hex value, or -1 if invalid
1603 ********************************************************************* */
1605 eth_parse_xdigit(char c
)
1609 if ((c
>= '0') && (c
<= '9')) digit
= c
- '0';
1610 else if ((c
>= 'a') && (c
<= 'f')) digit
= c
- 'a' + 10;
1611 else if ((c
>= 'A') && (c
<= 'F')) digit
= c
- 'A' + 10;
1617 /* *********************************************************************
1618 * ETH_PARSE_HWADDR(str,hwaddr)
1620 * Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
1625 * hwaddr - pointer to hardware address
1629 ********************************************************************* */
1631 eth_parse_hwaddr(char *str
, uint8_t *hwaddr
)
1634 int idx
= ENET_ADDR_LEN
;
1636 while (*str
&& (idx
> 0)) {
1637 digit1
= eth_parse_xdigit(*str
);
1638 if (digit1
< 0) return -1;
1640 if (!*str
) return -1;
1642 if ((*str
== ':') || (*str
== '-')) {
1647 digit2
= eth_parse_xdigit(*str
);
1648 if (digit2
< 0) return -1;
1652 *hwaddr
++ = (digit1
<< 4) | digit2
;
1655 if ((*str
== ':') || (*str
== '-'))
1661 /* *********************************************************************
1662 * ETH_INCR_HWADDR(hwaddr,incr)
1664 * Increment a 6-byte Ethernet hardware address, with carries
1667 * hwaddr - pointer to hardware address
1668 * incr - desired increment
1672 ********************************************************************* */
1674 eth_incr_hwaddr(uint8_t *hwaddr
, unsigned incr
)
1681 while (idx
>= 0 && carry
!= 0) {
1682 unsigned sum
= hwaddr
[idx
] + carry
;
1684 hwaddr
[idx
] = sum
& 0xFF;
1691 /* *********************************************************************
1692 * Declarations for CFE Device Driver Interface routines
1693 ********************************************************************* */
1695 static int dp83815_ether_open(cfe_devctx_t
*ctx
);
1696 static int dp83815_ether_read(cfe_devctx_t
*ctx
,iocb_buffer_t
*buffer
);
1697 static int dp83815_ether_inpstat(cfe_devctx_t
*ctx
,iocb_inpstat_t
*inpstat
);
1698 static int dp83815_ether_write(cfe_devctx_t
*ctx
,iocb_buffer_t
*buffer
);
1699 static int dp83815_ether_ioctl(cfe_devctx_t
*ctx
,iocb_buffer_t
*buffer
);
1700 static int dp83815_ether_close(cfe_devctx_t
*ctx
);
1701 static void dp83815_ether_poll(cfe_devctx_t
*ctx
, int64_t ticks
);
1702 static void dp83815_ether_reset(void *softc
);
1704 /* *********************************************************************
1705 * CFE Device Driver dispatch structure
1706 ********************************************************************* */
1708 const static cfe_devdisp_t dp83815_ether_dispatch
= {
1711 dp83815_ether_inpstat
,
1712 dp83815_ether_write
,
1713 dp83815_ether_ioctl
,
1714 dp83815_ether_close
,
1719 /* *********************************************************************
1720 * CFE Device Driver descriptor
1721 ********************************************************************* */
1723 const cfe_driver_t dp83815drv
= {
1727 &dp83815_ether_dispatch
,
1733 dp83815_ether_attach(cfe_driver_t
*drv
,
1734 pcitag_t tag
, int index
, uint8_t hwaddr
[])
1740 uint8_t promaddr
[ENET_ADDR_LEN
];
1744 device
= pci_conf_read(tag
, R_CFGID
);
1745 class = pci_conf_read(tag
, R_CFGRID
);
1747 /* Use memory space for the CSRs */
1748 pci_map_mem(tag
, R_CFGMA
, PCI_MATCH_BITS
, &pa
);
1750 sc
= (dp83815_softc
*) KMALLOC(sizeof(dp83815_softc
), 0);
1753 xprintf("DP83815: No memory to complete probe\n");
1756 memset(sc
, 0, sizeof(*sc
));
1758 sc
->membase
= (uint32_t)pa
;
1759 sc
->irq
= pci_conf_read(tag
, R_CFGINT
) & 0xFF;
1761 sc
->device
= PCI_PRODUCT(device
);
1762 sc
->revision
= PCI_REVISION(class);
1765 sc
->linkspeed
= ETHER_SPEED_AUTO
; /* select autonegotiation */
1766 sc
->loopback
= ETHER_LOOPBACK_OFF
;
1767 memcpy(sc
->hwaddr
, hwaddr
, ENET_ADDR_LEN
);
1769 srr
= READCSR(sc
, R_SRR
);
1773 /* Prefer the address in EEPROM. This will be read into the
1774 PMATCH register upon power up. Unfortunately, how to test for
1775 completion of the auto-load (but see PTSCR_EELOAD_EN). */
1776 if (dp83815_get_pm_addr(sc
, promaddr
) == 0) {
1777 memcpy(sc
->hwaddr
, promaddr
, ENET_ADDR_LEN
);
1780 sc
->state
= eth_state_uninit
;
1782 xsprintf(descr
, "%s at 0x%X (%02x-%02x-%02x-%02x-%02x-%02x)",
1783 drv
->drv_description
, sc
->membase
,
1784 sc
->hwaddr
[0], sc
->hwaddr
[1], sc
->hwaddr
[2],
1785 sc
->hwaddr
[3], sc
->hwaddr
[4], sc
->hwaddr
[5]);
1787 cfe_attach(drv
, sc
, NULL
, descr
);
1792 /* *********************************************************************
1793 * DP83815_ETHER_PROBE(drv,probe_a,probe_b,probe_ptr)
1795 * Probe and install drivers for all dp83815 Ethernet controllers.
1796 * For each, create a context structure and attach to the
1797 * specified network device.
1800 * drv - driver descriptor
1801 * probe_a - not used
1802 * probe_b - not used
1803 * probe_ptr - string pointer to hardware address for the first
1804 * MAC, in the form xx:xx:xx:xx:xx:xx
1808 ********************************************************************* */
1810 dp83815_ether_probe(cfe_driver_t
*drv
,
1811 unsigned long probe_a
, unsigned long probe_b
,
1815 uint8_t hwaddr
[ENET_ADDR_LEN
];
1818 eth_parse_hwaddr((char *) probe_ptr
, hwaddr
);
1820 /* use default address 02-00-00-10-0B-00 */
1821 hwaddr
[0] = 0x02; hwaddr
[1] = 0x00; hwaddr
[2] = 0x00;
1822 hwaddr
[3] = 0x10; hwaddr
[4] = 0x0B; hwaddr
[5] = 0x00;
1829 if (pci_find_device(K_PCI_VENDOR_NSC
, K_PCI_ID_DP83815
, n
, &tag
) != 0)
1831 dp83815_ether_attach(drv
, tag
, n
, hwaddr
);
1833 eth_incr_hwaddr(hwaddr
, 1);
1838 /* The functions below are called via the dispatch vector for the 83815. */
1840 /* *********************************************************************
1841 * DP83815_ETHER_OPEN(ctx)
1843 * Open the Ethernet device. The MAC is reset, initialized, and
1844 * prepared to receive and send packets.
1847 * ctx - device context (includes ptr to our softc)
1851 ********************************************************************* */
1853 dp83815_ether_open(cfe_devctx_t
*ctx
)
1855 dp83815_softc
*sc
= ctx
->dev_softc
;
1857 if (sc
->state
== eth_state_on
)
1862 sc
->inpkts
= sc
->outpkts
= 0;
1864 sc
->rx_interrupts
= sc
->tx_interrupts
= 0;
1875 /* *********************************************************************
1876 * DP83815_ETHER_READ(ctx,buffer)
1878 * Read a packet from the Ethernet device. If no packets are
1879 * available, the read will succeed but return 0 bytes.
1882 * ctx - device context (includes ptr to our softc)
1883 * buffer - pointer to buffer descriptor.
1887 ********************************************************************* */
1889 dp83815_ether_read(cfe_devctx_t
*ctx
, iocb_buffer_t
*buffer
)
1891 dp83815_softc
*sc
= ctx
->dev_softc
;
1899 if (sc
->state
!= eth_state_on
) return -1;
1902 pkt
= (eth_pkt_t
*) q_deqnext(&(sc
->rxqueue
));
1906 buffer
->buf_retlen
= 0;
1910 blen
= buffer
->buf_length
;
1911 if (blen
> pkt
->length
) blen
= pkt
->length
;
1913 blockcopy(buffer
->buf_ptr
, pkt
->buffer
, blen
);
1914 buffer
->buf_retlen
= blen
;
1916 eth_free_pkt(sc
, pkt
);
1917 dp83815_fillrxring(sc
);
1926 /* *********************************************************************
1927 * DP83815_ETHER_INPSTAT(ctx,inpstat)
1929 * Check for received packets on the Ethernet device
1932 * ctx - device context (includes ptr to our softc)
1933 * inpstat - pointer to input status structure
1937 ********************************************************************* */
1939 dp83815_ether_inpstat(cfe_devctx_t
*ctx
, iocb_inpstat_t
*inpstat
)
1941 dp83815_softc
*sc
= ctx
->dev_softc
;
1947 if (sc
->state
!= eth_state_on
) return -1;
1949 /* We avoid an interlock here because the result is a hint and an
1950 interrupt cannot turn a non-empty queue into an empty one. */
1951 inpstat
->inp_status
= (q_isempty(&(sc
->rxqueue
))) ? 0 : 1;
1956 /* *********************************************************************
1957 * DP83815_ETHER_WRITE(ctx,buffer)
1959 * Write a packet to the Ethernet device.
1962 * ctx - device context (includes ptr to our softc)
1963 * buffer - pointer to buffer descriptor.
1967 ********************************************************************* */
1969 dp83815_ether_write(cfe_devctx_t
*ctx
, iocb_buffer_t
*buffer
)
1971 dp83815_softc
*sc
= ctx
->dev_softc
;
1979 if (sc
->state
!= eth_state_on
) return -1;
1981 pkt
= eth_alloc_pkt(sc
);
1982 if (!pkt
) return CFE_ERR_NOMEM
;
1984 blen
= buffer
->buf_length
;
1985 if (blen
> pkt
->length
) blen
= pkt
->length
;
1987 blockcopy(pkt
->buffer
, buffer
->buf_ptr
, blen
);
1990 if (dp83815_transmit(sc
, pkt
) != 0) {
1991 eth_free_pkt(sc
,pkt
);
1992 return CFE_ERR_IOERR
;
2002 /* *********************************************************************
2003 * DP83815_ETHER_IOCTL(ctx,buffer)
2005 * Do device-specific I/O control operations for the device
2008 * ctx - device context (includes ptr to our softc)
2009 * buffer - pointer to buffer descriptor.
2013 ********************************************************************* */
2015 dp83815_ether_ioctl(cfe_devctx_t
*ctx
, iocb_buffer_t
*buffer
)
2017 dp83815_softc
*sc
= ctx
->dev_softc
;
2022 switch ((int)buffer
->buf_ioctlcmd
) {
2023 case IOCTL_ETHER_GETHWADDR
:
2024 memcpy(buffer
->buf_ptr
, sc
->hwaddr
, sizeof(sc
->hwaddr
));
2027 case IOCTL_ETHER_SETHWADDR
:
2028 return -1; /* not supported */
2030 case IOCTL_ETHER_GETSPEED
:
2031 argp
= (int *) buffer
->buf_ptr
;
2032 *argp
= sc
->linkspeed
;
2035 case IOCTL_ETHER_SETSPEED
:
2037 dp83815_resetrings(sc
);
2038 speed
= *((int *) buffer
->buf_ptr
);
2039 dp83815_setspeed(sc
, speed
);
2041 sc
->state
= eth_state_on
;
2044 case IOCTL_ETHER_GETLINK
:
2045 argp
= (int *) buffer
->buf_ptr
;
2046 *argp
= sc
->linkspeed
;
2049 case IOCTL_ETHER_GETLOOPBACK
:
2050 *((int *) buffer
) = sc
->loopback
;
2053 case IOCTL_ETHER_SETLOOPBACK
:
2055 dp83815_resetrings(sc
);
2056 mode
= *((int *) buffer
->buf_ptr
);
2057 sc
->loopback
= ETHER_LOOPBACK_OFF
; /* default */
2058 if (mode
== ETHER_LOOPBACK_INT
|| mode
== ETHER_LOOPBACK_EXT
) {
2059 dp83815_setloopback(sc
, mode
);
2062 sc
->state
= eth_state_on
;
2070 /* *********************************************************************
2071 * DP83815_ETHER_CLOSE(ctx)
2073 * Close the Ethernet device.
2076 * ctx - device context (includes ptr to our softc)
2080 ********************************************************************* */
2082 dp83815_ether_close(cfe_devctx_t
*ctx
)
2084 dp83815_softc
*sc
= ctx
->dev_softc
;
2086 sc
->state
= eth_state_off
;
2089 /* resynchronize descriptor rings */
2090 dp83815_resetrings(sc
);
2092 xprintf("%s: %d sent, %d received, %d interrupts\n",
2093 dp83815_devname(sc
), sc
->outpkts
, sc
->inpkts
, sc
->interrupts
);
2094 xprintf(" %d rx interrupts, %d tx interrupts\n",
2095 sc
->rx_interrupts
, sc
->tx_interrupts
);
2102 /* *********************************************************************
2103 * DP83815_ETHER_POLL(ctx,ticks)
2108 * ctx - device context (includes ptr to our softc)
2109 * ticks- current time in ticks
2113 ********************************************************************* */
2116 dp83815_ether_poll(cfe_devctx_t
*ctx
, int64_t ticks
)
2118 dp83815_softc
*sc
= ctx
->dev_softc
;
2120 if (sc
->phy_check
) {
2122 dp83815_checkphy(sc
);
2127 /* *********************************************************************
2128 * DP83815_ETHER_RESET(softc)
2130 * This routine is called when CFE is restarted after a
2131 * program exits. We can clean up pending I/Os here.
2134 * softc - pointer to dp83815_softc
2138 ********************************************************************* */
2141 dp83815_ether_reset(void *softc
)
2143 dp83815_softc
*sc
= (dp83815_softc
*)softc
;
2145 /* Turn off the Ethernet interface. */
2147 /* RESET_ADAPTER(sc); */
2149 sc
->state
= eth_state_uninit
;