release/src-rt/shared/sbpci.c

   1 /*
   2  * Low-Level PCI and SB support for BCM47xx
   3  *
   4  * Copyright 2004, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id$
  13  */
  14
  15 #include <typedefs.h>
  16 #include <pcicfg.h>
  17 #include <bcmdevs.h>
  18 #include <sbconfig.h>
  19 #include <sbpci.h>
  20 #include <osl.h>
  21 #include <bcmendian.h>
  22 #include <bcmutils.h>
  23 #include <sbutils.h>
  24 #include <bcmnvram.h>
  25 #include <hndmips.h>
  26
  27 /* Can free sbpci_init() memory after boot */
  28 #ifndef linux
  29 #define __init
  30 #endif
  31
  32 /* Emulated configuration space */
  33 static pci_config_regs sb_config_regs[SB_MAXCORES];
  34
  35 /* Banned cores */
  36 static uint16 pci_ban[32] = { 0 };
  37 static uint pci_banned = 0;
  38
  39 /* CardBus mode */
  40 static bool cardbus = FALSE;
  41
  42 /* Disable PCI host core */
  43 static bool pci_disabled = FALSE;
  44
  45 /*
  46  * Functions for accessing external PCI configuration space
  47  */
  48
  49 /* Assume one-hot slot wiring */
  50 #define PCI_SLOT_MAX 16
  51
  52 static uint32
  53 config_cmd(void *sbh, uint bus, uint dev, uint func, uint off)
  54 {
  55         uint coreidx;
  56         sbpciregs_t *regs;
  57         uint32 addr = 0;
  58
  59         /* CardBusMode supports only one device */
  60         if (cardbus && dev > 1)
  61                 return 0;
  62
  63         coreidx = sb_coreidx(sbh);
  64         regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
  65
  66         /* Type 0 transaction */
  67         if (bus == 1) {
  68                 /* Skip unwired slots */
  69                 if (dev < PCI_SLOT_MAX) {
  70                         /* Slide the PCI window to the appropriate slot */
  71                         W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
  72                         addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
  73                                 (func << 8) | (off & ~3);
  74                 }
  75         }
  76
  77         /* Type 1 transaction */
  78         else {
  79                 W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
  80                 addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
  81         }
  82
  83         sb_setcoreidx(sbh, coreidx);
  84
  85         return addr;
  86 }
  87
  88 static int
  89 extpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
  90 {
  91         uint32 addr, *reg = NULL, val;
  92         int ret = 0;
  93
  94         if (pci_disabled ||
  95             !(addr = config_cmd(sbh, bus, dev, func, off)) ||
  96             !(reg = (uint32 *) REG_MAP(addr, len)) ||
  97             BUSPROBE(val, reg))
  98                 val = 0xffffffff;
  99
 100         val >>= 8 * (off & 3);
 101         if (len == 4)
 102                 *((uint32 *) buf) = val;
 103         else if (len == 2)
 104                 *((uint16 *) buf) = (uint16) val;
 105         else if (len == 1)
 106                 *((uint8 *) buf) = (uint8) val;
 107         else
 108                 ret = -1;
 109
 110         if (reg)
 111                 REG_UNMAP(reg);
 112
 113         return ret;
 114 }
 115
 116 static int
 117 extpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
 118 {
 119         uint32 addr, *reg = NULL, val;
 120         int ret = 0;
 121
 122         if (pci_disabled ||
 123             !(addr = config_cmd(sbh, bus, dev, func, off)) ||
 124             !(reg = (uint32 *) REG_MAP(addr, len)) ||
 125             BUSPROBE(val, reg))
 126                 goto done;
 127
 128         if (len == 4)
 129                 val = *((uint32 *) buf);
 130         else if (len == 2) {
 131                 val &= ~(0xffff << (8 * (off & 3)));
 132                 val |= *((uint16 *) buf) << (8 * (off & 3));
 133         } else if (len == 1) {
 134                 val &= ~(0xff << (8 * (off & 3)));
 135                 val |= *((uint8 *) buf) << (8 * (off & 3));
 136         } else
 137                 ret = -1;
 138
 139         W_REG(reg, val);
 140
 141  done:
 142         if (reg)
 143                 REG_UNMAP(reg);
 144
 145         return ret;
 146 }
 147
 148 /*
 149  * Functions for accessing translated SB configuration space
 150  */
 151
 152 static int
 153 sb_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
 154 {
 155         pci_config_regs *cfg;
 156
 157         if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
 158                 return -1;
 159         cfg = &sb_config_regs[dev];
 160
 161         ASSERT(ISALIGNED(off, len));
 162         ASSERT(ISALIGNED((uintptr)buf, len));
 163
 164         if (len == 4)
 165                 *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
 166         else if (len == 2)
 167                 *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
 168         else if (len == 1)
 169                 *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
 170         else
 171                 return -1;
 172
 173         return 0;
 174 }
 175
 176 static int
 177 sb_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
 178 {
 179         uint coreidx, n;
 180         void *regs;
 181         sbconfig_t *sb;
 182         pci_config_regs *cfg;
 183
 184         if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
 185                 return -1;
 186         cfg = &sb_config_regs[dev];
 187
 188         ASSERT(ISALIGNED(off, len));
 189         ASSERT(ISALIGNED((uintptr)buf, len));
 190
 191         /* Emulate BAR sizing */
 192         if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
 193             len == 4 && *((uint32 *) buf) == ~0) {
 194                 coreidx = sb_coreidx(sbh);
 195                 if ((regs = sb_setcoreidx(sbh, dev))) {
 196                         sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 197                         /* Highest numbered address match register */
 198                         n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
 199                         if (off == OFFSETOF(pci_config_regs, base[0]))
 200                                 cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
 201                         else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
 202                                 cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
 203                         else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
 204                                 cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
 205                         else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
 206                                 cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
 207                 }
 208                 sb_setcoreidx(sbh, coreidx);
 209                 return 0;
 210         }
 211
 212         if (len == 4)
 213                 *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
 214         else if (len == 2)
 215                 *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
 216         else if (len == 1)
 217                 *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
 218         else
 219                 return -1;
 220
 221         return 0;
 222 }
 223
 224 int
 225 sbpci_read_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
 226 {
 227         if (bus == 0)
 228                 return sb_read_config(sbh, bus, dev, func, off, buf, len);
 229         else
 230                 return extpci_read_config(sbh, bus, dev, func, off, buf, len);
 231 }
 232
 233 int
 234 sbpci_write_config(void *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
 235 {
 236         if (bus == 0)
 237                 return sb_write_config(sbh, bus, dev, func, off, buf, len);
 238         else
 239                 return extpci_write_config(sbh, bus, dev, func, off, buf, len);
 240 }
 241
 242 void
 243 sbpci_ban(uint16 core)
 244 {
 245         if (pci_banned < ARRAYSIZE(pci_ban))
 246                 pci_ban[pci_banned++] = core;
 247 }
 248
 249 int __init
 250 sbpci_init(void *sbh)
 251 {
 252         uint chip, chiprev, chippkg, coreidx, host, i;
 253         uint32 boardflags;
 254         sbpciregs_t *pci;
 255         sbconfig_t *sb;
 256         pci_config_regs *cfg;
 257         void *regs;
 258         char varname[8];
 259         uint wlidx = 0;
 260         uint16 vendor, core;
 261         uint8 class, subclass, progif;
 262         uint32 val;
 263         uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
 264         uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
 265
 266         chip = sb_chip(sbh);
 267         chiprev = sb_chiprev(sbh);
 268         chippkg = sb_chippkg(sbh);
 269         coreidx = sb_coreidx(sbh);
 270
 271         if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0)))
 272                 return -1;
 273         sb_core_reset(sbh, 0);
 274
 275         boardflags = (uint32) getintvar(NULL, "boardflags");
 276
 277         if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
 278                 pci_disabled = TRUE;
 279
 280         /*
 281          * The 200-pin BCM4712 package does not bond out PCI. Even when
 282          * PCI is bonded out, some boards may leave the pins
 283          * floating.
 284          */
 285         if (((chip == BCM4712_DEVICE_ID) &&
 286              ((chippkg == BCM4712SMALL_PKG_ID) ||
 287               (chippkg == BCM4712MID_PKG_ID))) ||
 288             (boardflags & BFL_NOPCI))
 289                 pci_disabled = TRUE;
 290
 291         /*
 292          * If the PCI core should not be touched (disabled, not bonded
 293          * out, or pins floating), do not even attempt to access core
 294          * registers. Otherwise, try to determine if it is in host
 295          * mode.
 296          */
 297         if (pci_disabled)
 298                 host = 0;
 299         else
 300                 host = !BUSPROBE(val, &pci->control);
 301
 302         if (!host) {
 303                 /* Disable PCI interrupts in client mode */
 304                 sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
 305                 W_REG(&sb->sbintvec, 0);
 306
 307                 /* Disable the PCI bridge in client mode */
 308                 sbpci_ban(SB_PCI);
 309                 printf("PCI: Disabled\n");
 310         } else {
 311                 /* Reset the external PCI bus and enable the clock */
 312                 W_REG(&pci->control, 0x5);              /* enable the tristate drivers */
 313                 W_REG(&pci->control, 0xd);              /* enable the PCI clock */
 314                 OSL_DELAY(150);                         /* delay > 100 us */
 315                 W_REG(&pci->control, 0xf);              /* deassert PCI reset */
 316                 W_REG(&pci->arbcontrol, PCI_INT_ARB);   /* use internal arbiter */
 317                 OSL_DELAY(1);                           /* delay 1 us */
 318
 319                 /* Enable CardBusMode */
 320                 cardbus = nvram_match("cardbus", "1");
 321                 if (cardbus) {
 322                         printf("PCI: Enabling CardBus\n");
 323                         /* GPIO 1 resets the CardBus device on bcm94710ap */
 324                         sb_gpioout(sbh, 1, 1);
 325                         sb_gpioouten(sbh, 1, 1);
 326                         W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
 327                 }
 328
 329                 /* 64 MB I/O access window */
 330                 W_REG(&pci->sbtopci0, SBTOPCI_IO);
 331                 /* 64 MB configuration access window */
 332                 W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
 333                 /* 1 GB memory access window */
 334                 W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
 335
 336                 /* Enable PCI bridge BAR0 prefetch and burst */
 337                 val = 6;
 338                 sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
 339
 340                 /* Enable PCI interrupts */
 341                 W_REG(&pci->intmask, PCI_INTA);
 342         }
 343
 344         /* Scan the SB bus */
 345         bzero(sb_config_regs, sizeof(sb_config_regs));
 346         for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
 347                 cfg->vendor = 0xffff;
 348                 if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
 349                         continue;
 350                 sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 351
 352                 /* Read ID register and parse vendor and core */
 353                 val = R_REG(&sb->sbidhigh);
 354                 vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
 355                 core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
 356                 progif = 0;
 357
 358                 /* Check if this core is banned */
 359                 for (i = 0; i < pci_banned; i++)
 360                         if (core == pci_ban[i])
 361                                 break;
 362                 if (i < pci_banned)
 363                         continue;
 364
 365                 /* Known vendor translations */
 366                 switch (vendor) {
 367                 case SB_VEND_BCM:
 368                         vendor = VENDOR_BROADCOM;
 369                         break;
 370                 }
 371
 372                 /* Determine class based on known core codes */
 373                 switch (core) {
 374                 case SB_ILINE20:
 375                         class = PCI_CLASS_NET;
 376                         subclass = PCI_NET_ETHER;
 377                         core = BCM47XX_ILINE_ID;
 378                         break;
 379                 case SB_ILINE100:
 380                         class = PCI_CLASS_NET;
 381                         subclass = PCI_NET_ETHER;
 382                         core = BCM4610_ILINE_ID;
 383                         break;
 384                 case SB_ENET:
 385                         class = PCI_CLASS_NET;
 386                         subclass = PCI_NET_ETHER;
 387                         core = BCM47XX_ENET_ID;
 388                         break;
 389                 case SB_SDRAM:
 390                 case SB_MEMC:
 391                         class = PCI_CLASS_MEMORY;
 392                         subclass = PCI_MEMORY_RAM;
 393                         break;
 394                 case SB_PCI:
 395                         class = PCI_CLASS_BRIDGE;
 396                         subclass = PCI_BRIDGE_PCI;
 397                         break;
 398                 case SB_MIPS:
 399                 case SB_MIPS33:
 400                         class = PCI_CLASS_CPU;
 401                         subclass = PCI_CPU_MIPS;
 402                         break;
 403                 case SB_CODEC:
 404                         class = PCI_CLASS_COMM;
 405                         subclass = PCI_COMM_MODEM;
 406                         core = BCM47XX_V90_ID;
 407                         break;
 408                 case SB_USB:
 409                         class = PCI_CLASS_SERIAL;
 410                         subclass = PCI_SERIAL_USB;
 411                         progif = 0x10; /* OHCI */
 412                         core = BCM47XX_USB_ID;
 413                         break;
 414                 case SB_USB11H:
 415                         class = PCI_CLASS_SERIAL;
 416                         subclass = PCI_SERIAL_USB;
 417                         progif = 0x10; /* OHCI */
 418                         core = BCM47XX_USBH_ID;
 419                         break;
 420                 case SB_USB11D:
 421                         class = PCI_CLASS_SERIAL;
 422                         subclass = PCI_SERIAL_USB;
 423                         core = BCM47XX_USBD_ID;
 424                         break;
 425                 case SB_IPSEC:
 426                         class = PCI_CLASS_CRYPT;
 427                         subclass = PCI_CRYPT_NETWORK;
 428                         core = BCM47XX_IPSEC_ID;
 429                         break;
 430                 case SB_ROBO:
 431                         class = PCI_CLASS_NET;
 432                         subclass = PCI_NET_OTHER;
 433                         core = BCM47XX_ROBO_ID;
 434                         break;
 435                 case SB_EXTIF:
 436                 case SB_CC:
 437                         class = PCI_CLASS_MEMORY;
 438                         subclass = PCI_MEMORY_FLASH;
 439                         break;
 440                 case SB_D11:
 441                         class = PCI_CLASS_NET;
 442                         subclass = PCI_NET_OTHER;
 443                         /* Let an nvram variable override this */
 444                         sprintf(varname, "wl%did", wlidx);
 445                         wlidx++;
 446                         if ((core = getintvar(NULL, varname)) == 0) {
 447                                 if (chip == BCM4712_DEVICE_ID) {
 448                                         if (chippkg == BCM4712SMALL_PKG_ID)
 449                                                 core = BCM4306_D11G_ID;
 450                                         else
 451                                                 core = BCM4306_D11DUAL_ID;
 452                                 } else {
 453                                         /* 4310 */
 454                                         core = BCM4310_D11B_ID;
 455                                 }
 456                         }
 457                         break;
 458
 459                 default:
 460                         class = subclass = progif = 0xff;
 461                         break;
 462                 }
 463
 464                 /* Supported translations */
 465                 cfg->vendor = htol16(vendor);
 466                 cfg->device = htol16(core);
 467                 cfg->rev_id = chiprev;
 468                 cfg->prog_if = progif;
 469                 cfg->sub_class = subclass;
 470                 cfg->base_class = class;
 471                 cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
 472                 cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
 473                 cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
 474                 cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
 475                 cfg->base[4] = 0;
 476                 cfg->base[5] = 0;
 477                 if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
 478                         cfg->header_type = PCI_HEADER_BRIDGE;
 479                 else
 480                         cfg->header_type = PCI_HEADER_NORMAL;
 481                 /* Save core interrupt flag */
 482                 cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
 483                 /* Default to MIPS shared interrupt 0 */
 484                 cfg->int_line = 0;
 485                 /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
 486                 if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
 487                     (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
 488                         sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 489                         val = R_REG(&sb->sbipsflag);
 490                         for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
 491                                 if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
 492                                         break;
 493                         }
 494                         if (cfg->int_line > 4)
 495                                 cfg->int_line = 0;
 496                 }
 497                 /* Emulated core */
 498                 *((uint32 *) &cfg->sprom_control) = 0xffffffff;
 499         }
 500
 501         sb_setcoreidx(sbh, coreidx);
 502         return 0;
 503 }
 504
 505 void
 506 sbpci_check(void *sbh)
 507 {
 508         uint coreidx;
 509         sbpciregs_t *pci;
 510         uint32 sbtopci1;
 511         uint32 buf[64], *ptr, i;
 512         ulong pa;
 513         volatile uint j;
 514
 515         coreidx = sb_coreidx(sbh);
 516         pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
 517
 518         /* Clear the test array */
 519         pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
 520         ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
 521         memset(ptr, 0, sizeof(buf));
 522
 523         /* Point PCI window 1 to memory */
 524         sbtopci1 = R_REG(&pci->sbtopci1);
 525         W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
 526
 527         /* Fill the test array via PCI window 1 */
 528         ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
 529         for (i = 0; i < ARRAYSIZE(buf); i++) {
 530                 for (j = 0; j < 2; j++);
 531                 W_REG(&ptr[i], i);
 532         }
 533         REG_UNMAP(ptr);
 534
 535         /* Restore PCI window 1 */
 536         W_REG(&pci->sbtopci1, sbtopci1);
 537
 538         /* Check the test array */
 539         DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
 540         ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
 541         for (i = 0; i < ARRAYSIZE(buf); i++) {
 542                 if (ptr[i] != i)
 543                         break;
 544         }
 545
 546         /* Change the clock if the test fails */
 547         if (i < ARRAYSIZE(buf)) {
 548                 uint32 req, cur;
 549
 550                 cur = sb_clock(sbh);
 551                 printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
 552                 for (req = 104000000; req < 176000000; req += 4000000) {
 553                         printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
 554                         /* This will only reset if the clocks are valid and have changed */
 555                         sb_mips_setclock(sbh, req, 0, 0);
 556                 }
 557                 /* Should not reach here */
 558                 ASSERT(0);
 559         }
 560
 561         sb_setcoreidx(sbh, coreidx);
 562 }