release/src-rt/shared/sbmips.c

   1 /*
   2  * BCM47XX Sonics SiliconBackplane MIPS core routines
   3  *
   4  * Copyright 2004, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id$
  13  */
  14
  15 #include <typedefs.h>
  16 #include <osl.h>
  17 #include <sbutils.h>
  18 #include <bcmdevs.h>
  19 #include <bcmnvram.h>
  20 #include <bcmutils.h>
  21 #include <hndmips.h>
  22 #include <sbconfig.h>
  23 #include <sbextif.h>
  24 #include <sbchipc.h>
  25 #include <sbmemc.h>
  26 #include <mipsinc.h>
  27
  28 /*
  29  * Returns TRUE if an external UART exists at the given base
  30  * register.
  31  */
  32 static bool
  33 BCMINITFN(serial_exists)(uint8 *regs)
  34 {
  35         uint8 save_mcr, status1;
  36
  37         save_mcr = R_REG(&regs[UART_MCR]);
  38         W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
  39         status1 = R_REG(&regs[UART_MSR]) & 0xf0;
  40         W_REG(&regs[UART_MCR], save_mcr);
  41
  42         return (status1 == 0x90);
  43 }
  44
  45 /*
  46  * Initializes UART access. The callback function will be called once
  47  * per found UART.
  48  */
  49 void
  50 BCMINITFN(sb_serial_init)(void *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
  51 {
  52         void *regs;
  53         ulong base;
  54         uint irq;
  55         int i, n;
  56
  57         if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
  58                 extifregs_t *eir = (extifregs_t *) regs;
  59                 sbconfig_t *sb;
  60
  61                 /* Determine external UART register base */
  62                 sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
  63                 base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
  64
  65                 /* Determine IRQ */
  66                 irq = sb_irq(sbh);
  67
  68                 /* Disable GPIO interrupt initially */
  69                 W_REG(&eir->gpiointpolarity, 0);
  70                 W_REG(&eir->gpiointmask, 0);
  71
  72                 /* Search for external UARTs */
  73                 n = 2;
  74                 for (i = 0; i < 2; i++) {
  75                         regs = (void *) REG_MAP(base + (i * 8), 8);
  76                         if (BCMINIT(serial_exists)(regs)) {
  77                                 /* Set GPIO 1 to be the external UART IRQ */
  78                                 W_REG(&eir->gpiointmask, 2);
  79                                 if (add)
  80                                         add(regs, irq, 13500000, 0);
  81                         }
  82                 }
  83
  84                 /* Add internal UART if enabled */
  85                 if (R_REG(&eir->corecontrol) & CC_UE)
  86                         if (add)
  87                                 add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
  88         } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
  89                 chipcregs_t *cc = (chipcregs_t *) regs;
  90                 uint32 rev, cap, pll, baud_base, div;
  91
  92                 /* Determine core revision and capabilities */
  93                 rev = sb_corerev(sbh);
  94                 cap = R_REG(&cc->capabilities);
  95                 pll = cap & CAP_PLL_MASK;
  96
  97                 /* Determine IRQ */
  98                 irq = sb_irq(sbh);
  99
 100                 if (pll == PLL_TYPE1) {
 101                         /* PLL clock */
 102                         baud_base = sb_clock_rate(pll,
 103                                                   R_REG(&cc->clockcontrol_n),
 104                                                   R_REG(&cc->clockcontrol_m2));
 105                         div = 1;
 106                 } else if (rev >= 3) {
 107                         if (pll == PLL_TYPE6) {
 108                                 /* Fixed ALP clock on 4320 */
 109                                 baud_base = 20000000;
 110                                 /* Set the override bit so we don't divide it */
 111                                 W_REG(&cc->corecontrol, CC_UARTCLKO);
 112                         } else {
 113                                 /* Internal backplane clock */
 114                                 baud_base = sb_clock(sbh);
 115                         }
 116                         div = 2;        /* Minimum divisor */
 117                         W_REG(&cc->clkdiv, ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
 118                 } else {
 119                         /* Fixed internal backplane clock */
 120                         baud_base = 88000000;
 121                         div = 48;
 122                 }
 123
 124                 /* Clock source depends on strapping if UartClkOverride is unset */
 125                 if ((rev > 0) && ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
 126                         if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
 127                                 /* Internal divided backplane clock */
 128                                 baud_base /= div;
 129                         } else {
 130                                 /* Assume external clock of 1.8432 MHz */
 131                                 baud_base = 1843200;
 132                         }
 133                 }
 134
 135                 /* Add internal UARTs */
 136                 n = cap & CAP_UARTS_MASK;
 137                 for (i = 0; i < n; i++) {
 138                         /* Register offset changed after revision 0 */
 139                         if (rev)
 140                                 regs = (void *)((ulong) &cc->uart0data + (i * 256));
 141                         else
 142                                 regs = (void *)((ulong) &cc->uart0data + (i * 8));
 143
 144                         if (add)
 145                                 add(regs, irq, baud_base, 0);
 146                 }
 147         }
 148 }
 149
 150 /*
 151  * Initialize jtag master and return handle for
 152  * jtag_rwreg. Returns NULL on failure.
 153  */
 154 void *
 155 sb_jtagm_init(void *sbh, uint clkd, bool exttap)
 156 {
 157         void *regs;
 158
 159         if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
 160                 chipcregs_t *cc = (chipcregs_t *) regs;
 161                 uint32 tmp;
 162
 163                 /*
 164                  * Determine jtagm availability from
 165                  * core revision and capabilities.
 166                  */
 167                 tmp = sb_corerev(sbh);
 168                 /*
 169                  * Corerev 10 has jtagm, but the only chip
 170                  * with it does not have a mips, and
 171                  * the layout of the jtagcmd register is
 172                  * different. We'll only accept >= 11.
 173                  */
 174                 if (tmp < 11)
 175                         return (NULL);
 176
 177                 tmp = R_REG(&cc->capabilities);
 178                 if ((tmp & CAP_JTAGP) == 0)
 179                         return (NULL);
 180
 181                 /* Set clock divider if requested */
 182                 if (clkd != 0) {
 183                         tmp = R_REG(&cc->clkdiv);
 184                         tmp = (tmp & ~CLKD_JTAG) |
 185                                 ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
 186                         W_REG(&cc->clkdiv, tmp);
 187                 }
 188
 189                 /* Enable jtagm */
 190                 tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
 191                 W_REG(&cc->jtagctrl, tmp);
 192         }
 193
 194         return (regs);
 195 }
 196
 197 void
 198 sb_jtagm_disable(void *h)
 199 {
 200         chipcregs_t *cc = (chipcregs_t *)h;
 201
 202         W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
 203 }
 204
 205 /*
 206  * Read/write a jtag register. Assumes a target with
 207  * 8 bit IR and 32 bit DR.
 208  */
 209 #define IRWIDTH         8
 210 #define DRWIDTH         32
 211 uint32
 212 jtag_rwreg(void *h, uint32 ir, uint32 dr)
 213 {
 214         chipcregs_t *cc = (chipcregs_t *) h;
 215         uint32 tmp;
 216
 217         W_REG(&cc->jtagir, ir);
 218         W_REG(&cc->jtagdr, dr);
 219         tmp = JCMD_START | JCMD_ACC_IRDR |
 220                 ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
 221                 (DRWIDTH - 1);
 222         W_REG(&cc->jtagcmd, tmp);
 223         while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
 224                 /* OSL_DELAY(1); */
 225         }
 226
 227         tmp = R_REG(&cc->jtagdr);
 228         return (tmp);
 229 }
 230
 231 /* Returns the SB interrupt flag of the current core. */
 232 uint32
 233 sb_flag(void *sbh)
 234 {
 235         void *regs;
 236         sbconfig_t *sb;
 237
 238         regs = sb_coreregs(sbh);
 239         sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 240
 241         return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
 242 }
 243
 244 static const uint32 sbips_int_mask[] = {
 245         0,
 246         SBIPS_INT1_MASK,
 247         SBIPS_INT2_MASK,
 248         SBIPS_INT3_MASK,
 249         SBIPS_INT4_MASK
 250 };
 251
 252 static const uint32 sbips_int_shift[] = {
 253         0,
 254         0,
 255         SBIPS_INT2_SHIFT,
 256         SBIPS_INT3_SHIFT,
 257         SBIPS_INT4_SHIFT
 258 };
 259
 260 /*
 261  * Returns the MIPS IRQ assignment of the current core. If unassigned,
 262  * 0 is returned.
 263  */
 264 uint
 265 sb_irq(void *sbh)
 266 {
 267         uint idx;
 268         void *regs;
 269         sbconfig_t *sb;
 270         uint32 flag, sbipsflag;
 271         uint irq = 0;
 272
 273         flag = sb_flag(sbh);
 274
 275         idx = sb_coreidx(sbh);
 276
 277         if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
 278             (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
 279                 sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 280
 281                 /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
 282                 sbipsflag = R_REG(&sb->sbipsflag);
 283                 for (irq = 1; irq <= 4; irq++) {
 284                         if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
 285                                 break;
 286                 }
 287                 if (irq == 5)
 288                         irq = 0;
 289         }
 290
 291         sb_setcoreidx(sbh, idx);
 292
 293         return irq;
 294 }
 295
 296 /* Clears the specified MIPS IRQ. */
 297 static void
 298 BCMINITFN(sb_clearirq)(void *sbh, uint irq)
 299 {
 300         void *regs;
 301         sbconfig_t *sb;
 302
 303         if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
 304             !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
 305                 ASSERT(regs);
 306         sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 307
 308         if (irq == 0)
 309                 W_REG(&sb->sbintvec, 0);
 310         else
 311                 OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
 312 }
 313
 314 /*
 315  * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
 316  * IRQ 0 may be assigned more than once.
 317  */
 318 static void
 319 BCMINITFN(sb_setirq)(void *sbh, uint irq, uint coreid, uint coreunit)
 320 {
 321         void *regs;
 322         sbconfig_t *sb;
 323         uint32 flag;
 324
 325         regs = sb_setcore(sbh, coreid, coreunit);
 326         ASSERT(regs);
 327         flag = sb_flag(sbh);
 328
 329         if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
 330             !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
 331                 ASSERT(regs);
 332         sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
 333
 334         if (irq == 0)
 335                 OR_REG(&sb->sbintvec, 1 << flag);
 336         else {
 337                 flag <<= sbips_int_shift[irq];
 338                 ASSERT(!(flag & ~sbips_int_mask[irq]));
 339                 flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
 340                 W_REG(&sb->sbipsflag, flag);
 341         }
 342 }
 343
 344 /*
 345  * Initializes clocks and interrupts. SB and NVRAM access must be
 346  * initialized prior to calling.
 347  */
 348 void
 349 BCMINITFN(sb_mips_init)(void *sbh)
 350 {
 351         ulong hz, ns, tmp;
 352         extifregs_t *eir;
 353         chipcregs_t *cc;
 354         char *value;
 355         uint irq;
 356
 357         /* Figure out current SB clock speed */
 358         if ((hz = sb_clock(sbh)) == 0)
 359                 hz = 100000000;
 360         ns = 1000000000 / hz;
 361
 362         /* Setup external interface timing */
 363         if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
 364                 /* Initialize extif so we can get to the LEDs and external UART */
 365                 W_REG(&eir->prog_config, CF_EN);
 366
 367                 /* Set timing for the flash */
 368                 tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
 369                 tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
 370                 tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
 371                 W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
 372
 373                 /* Set programmable interface timing for external uart */
 374                 tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
 375                 tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
 376                 tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
 377                 tmp = tmp | CEIL(120, ns);              /* W0 = 120nS */
 378                 W_REG(&eir->prog_waitcount, tmp);       /* 0x01020a0c for a 100Mhz clock */
 379         } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
 380                 /* Set timing for the flash */
 381                 tmp = CEIL(10, ns) << FW_W3_SHIFT;      /* W3 = 10nS */
 382                 tmp |= CEIL(10, ns) << FW_W1_SHIFT;     /* W1 = 10nS */
 383                 tmp |= CEIL(120, ns);                   /* W0 = 120nS */
 384
 385                 // Added by Chen-I for 5365
 386                 if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
 387                 {
 388                         W_REG(&cc->flash_waitcount, tmp);
 389                         W_REG(&cc->pcmcia_memwait, tmp);
 390                 }
 391                 else
 392                 {
 393                         if (sb_corerev(sbh) < 9)
 394                                 W_REG(&cc->flash_waitcount, tmp);
 395
 396                         if ( (sb_corerev(sbh) < 9) ||
 397                              ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0) ) {
 398                                 W_REG(&cc->pcmcia_memwait, tmp);
 399                         }
 400                 }
 401         }
 402
 403         /* Chip specific initialization */
 404         switch (BCMINIT(sb_chip)(sbh)) {
 405         case BCM4710_DEVICE_ID:
 406                 /* Clear interrupt map */
 407                 for (irq = 0; irq <= 4; irq++)
 408                         BCMINIT(sb_clearirq)(sbh, irq);
 409                 BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
 410                 BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
 411                 BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
 412                 BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
 413                 BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
 414                 ASSERT(eir);
 415                 value = BCMINIT(nvram_get)("et0phyaddr");
 416                 if (value && !strcmp(value, "31")) {
 417                         /* Enable internal UART */
 418                         W_REG(&eir->corecontrol, CC_UE);
 419                         /* Give USB its own interrupt */
 420                         BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
 421                 } else {
 422                         /* Disable internal UART */
 423                         W_REG(&eir->corecontrol, 0);
 424                         /* Give Ethernet its own interrupt */
 425                         BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
 426                         BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
 427                 }
 428                 break;
 429         case BCM4310_DEVICE_ID:
 430                 MTC0(C0_BROADCOM, 0, MFC0(C0_BROADCOM, 0) & ~(1 << 22));
 431                 break;
 432         case BCM5350_DEVICE_ID:
 433                 /* Clear interrupt map */
 434                 for (irq = 0; irq <= 4; irq++)
 435                         BCMINIT(sb_clearirq)(sbh, irq);
 436                 BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
 437                 BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
 438                 BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
 439                 BCMINIT(sb_setirq)(sbh, 3, SB_IPSEC, 0);
 440                 BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
 441                 break;
 442         }
 443 }
 444
 445 uint32
 446 BCMINITFN(sb_mips_clock)(void *sbh)
 447 {
 448         extifregs_t *eir;
 449         chipcregs_t *cc;
 450         uint32 n, m;
 451         uint idx;
 452         uint32 pll_type, rate = 0;
 453
 454         /* get index of the current core */
 455         idx = sb_coreidx(sbh);
 456         pll_type = PLL_TYPE1;
 457
 458         /* switch to extif or chipc core */
 459         if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
 460                 n = R_REG(&eir->clockcontrol_n);
 461                 m = R_REG(&eir->clockcontrol_sb);
 462         } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
 463                 pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
 464                 n = R_REG(&cc->clockcontrol_n);
 465                 if ((pll_type == PLL_TYPE2) ||
 466                     (pll_type == PLL_TYPE4) ||
 467                     (pll_type == PLL_TYPE6))
 468                         m = R_REG(&cc->clockcontrol_mips);
 469                 else if (pll_type == PLL_TYPE5) {
 470                         rate = 200000000;
 471                         goto out;
 472                 }
 473                 else if (pll_type == PLL_TYPE3) {
 474                         if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
 475                                 rate = 200000000;
 476                                 goto out;
 477                         } else
 478                                 m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
 479                 } else
 480                         m = R_REG(&cc->clockcontrol_sb);
 481         } else
 482                 goto out;
 483
 484         // Added by Chen-I for 5365
 485         if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
 486                 rate = 100000000;
 487         else
 488                 /* calculate rate */
 489                 rate = sb_clock_rate(pll_type, n, m);
 490
 491         if (pll_type == PLL_TYPE6)
 492                 rate = SB2MIPS_T6(rate);
 493
 494 out:
 495         /* switch back to previous core */
 496         sb_setcoreidx(sbh, idx);
 497
 498         return rate;
 499 }
 500
 501 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
 502
 503 static void
 504 BCMINITFN(handler)(void)
 505 {
 506         /* Step 11 */
 507         __asm__ (
 508                 ".set\tmips32\n\t"
 509                 "ssnop\n\t"
 510                 "ssnop\n\t"
 511         /* Disable interrupts */
 512         /*      MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
 513                 "mfc0 $15, $12\n\t"
 514         /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
 515                 "li $14, -31746\n\t"
 516                 "and $15, $15, $14\n\t"
 517                 "mtc0 $15, $12\n\t"
 518                 "eret\n\t"
 519                 "nop\n\t"
 520                 "nop\n\t"
 521                 ".set\tmips0"
 522         );
 523 }
 524
 525 /* The following MUST come right after handler() */
 526 static void
 527 BCMINITFN(afterhandler)(void)
 528 {
 529 }
 530
 531 /*
 532  * Set the MIPS, backplane and PCI clocks as closely as possible.
 533  */
 534 bool
 535 BCMINITFN(sb_mips_setclock)(void *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
 536 {
 537         extifregs_t *eir = NULL;
 538         chipcregs_t *cc = NULL;
 539         mipsregs_t *mipsr = NULL;
 540         volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
 541         uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, new_ratio;
 542         uint32 pll_type, sync_mode;
 543         uint ic_size, ic_lsize;
 544         uint idx, i;
 545         typedef struct {
 546                 uint32 mipsclock;
 547                 uint16 n;
 548                 uint32 sb;
 549                 uint32 pci33;
 550                 uint32 pci25;
 551         } n3m_table_t;
 552         static n3m_table_t BCMINITDATA(type1_table)[] = {
 553                 {  96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /*  96.000 32.000 24.000 */
 554                 { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
 555                 { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
 556                 { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
 557                 { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
 558                 { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
 559                 { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
 560                 { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
 561                 { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
 562                 { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
 563                 { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
 564                 { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
 565                 { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
 566                 { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
 567                 { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
 568                 { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
 569                 { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
 570                 { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
 571                 { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
 572                 { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
 573         };
 574         typedef struct {
 575                 uint32 mipsclock;
 576                 uint16 n;
 577                 uint32 m2; /* that is the clockcontrol_m2 */
 578         } type3_table_t;
 579         static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
 580                 { 150000000, 0x311, 0x4020005 },
 581 //              { 180000000, 0x, 0x },  /* later we may want this frequency */
 582                 { 200000000, 0x311, 0x4020003 },
 583         };
 584         typedef struct {
 585                 uint32 mipsclock;
 586                 uint32 sbclock;
 587                 uint16 n;
 588                 uint32 sb;
 589                 uint32 pci33;
 590                 uint32 m2;
 591                 uint32 m3;
 592                 uint32 ratio;
 593                 uint32 ratio_parm;
 594         } n4m_table_t;
 595
 596         static n4m_table_t BCMINITDATA(type2_table)[] = {
 597                 { 180000000,  80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
 598                 { 180000000,  90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
 599                 { 200000000, 100000000, 0x0303, 0x01000000, 0x01000600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
 600                 { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
 601                 { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
 602                 { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
 603                 { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
 604                 { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
 605                 { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 },
 606                 { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 0x21, 0x0aaa0555 },
 607                 { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
 608                 { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
 609                 { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
 610                 { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
 611                 { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 0x21, 0x0aaa0555 },
 612                 { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 0x94, 0x012a00a9 },
 613                 { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 0x21, 0x0aaa0555 }
 614         };
 615
 616         static n4m_table_t BCMINITDATA(type4_table)[] = {
 617                 { 192000000,  96000000, 0x0702, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
 618                 { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 0x21, 0x0aaa0555 },
 619                 { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
 620                 { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x11030305, 0x04000005, 0x94, 0x012a00a9 },
 621                 { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 0x21, 0x0aaa0555 },
 622                 { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 0x21, 0x0aaa0555 },
 623                 { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
 624                 { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 0x21, 0x0aaa0555 },
 625                 { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
 626                 { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
 627                 { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 0x73, 0x254a14a9 },
 628                 { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 0x52, 0x02520129 }
 629         };
 630         ulong start, end, dst;
 631         bool ret = FALSE;
 632
 633         /* get index of the current core */
 634         idx = sb_coreidx(sbh);
 635         clockcontrol_m2 = NULL;
 636
 637         /* switch to extif or chipc core */
 638         if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
 639                 pll_type = PLL_TYPE1;
 640                 clockcontrol_n = &eir->clockcontrol_n;
 641                 clockcontrol_sb = &eir->clockcontrol_sb;
 642                 clockcontrol_pci = &eir->clockcontrol_pci;
 643                 clockcontrol_m2 = &cc->clockcontrol_m2;
 644         } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
 645                 pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
 646                 if (pll_type == PLL_TYPE6) {
 647                         clockcontrol_n = NULL;
 648                         clockcontrol_sb = NULL;
 649                         clockcontrol_pci = NULL;
 650                 } else {
 651                         clockcontrol_n = &cc->clockcontrol_n;
 652                         clockcontrol_sb = &cc->clockcontrol_sb;
 653                         clockcontrol_pci = &cc->clockcontrol_pci;
 654                 clockcontrol_m2 = &cc->clockcontrol_m2;
 655                 }
 656         } else
 657                 goto done;
 658
 659         if (pll_type == PLL_TYPE6) {
 660                 /* Silence compilers */
 661                 orig_n = orig_sb = orig_pci = 0;
 662         } else {
 663                 /* Store the current clock register values */
 664                 orig_n = R_REG(clockcontrol_n);
 665                 orig_sb = R_REG(clockcontrol_sb);
 666                 orig_pci = R_REG(clockcontrol_pci);
 667         }
 668
 669         if (pll_type == PLL_TYPE1) {
 670                 /* Keep the current PCI clock if not specified */
 671                 if (pciclock == 0) {
 672                         pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
 673                         pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
 674                 }
 675
 676                 /* Search for the closest MIPS clock less than or equal to a preferred value */
 677                 for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
 678                         ASSERT(BCMINIT(type1_table)[i].mipsclock ==
 679                                sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
 680                         if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
 681                                 break;
 682                 }
 683                 if (i == 0) {
 684                         ret = FALSE;
 685                         goto done;
 686                 } else {
 687                         ret = TRUE;
 688                         i--;
 689                 }
 690                 ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
 691
 692                 /* No PLL change */
 693                 if ((orig_n == BCMINIT(type1_table)[i].n) &&
 694                     (orig_sb == BCMINIT(type1_table)[i].sb) &&
 695                     (orig_pci == BCMINIT(type1_table)[i].pci33))
 696                         goto done;
 697
 698                 /* Set the PLL controls */
 699                 W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
 700                 W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
 701                 if (pciclock == 25000000)
 702                         W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
 703                 else
 704                         W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
 705
 706                 /* Reset */
 707                 sb_watchdog(sbh, 1);
 708
 709                 while (1);
 710         } else if ((pll_type == PLL_TYPE3) &&
 711                    (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
 712                 /* 5350 */
 713                 /* Search for the closest MIPS clock less than or equal to a preferred value */
 714
 715                 for (i = 0; i < ARRAYSIZE(type3_table); i++) {
 716                         if (type3_table[i].mipsclock > mipsclock)
 717                                 break;
 718                 }
 719                 if (i == 0) {
 720                         ret = FALSE;
 721                         goto done;
 722                 } else {
 723                         ret = TRUE;
 724                         i--;
 725                 }
 726                 ASSERT(type3_table[i].mipsclock <= mipsclock);
 727
 728                 /* No PLL change */
 729                 orig_m2 = R_REG(&cc->clockcontrol_m2);
 730                 if ((orig_n == type3_table[i].n) &&
 731                     (orig_m2 == type3_table[i].m2))  {
 732                         goto done;
 733                 }
 734
 735                 /* Set the PLL controls */
 736                 W_REG(clockcontrol_n, type3_table[i].n);
 737                 W_REG(clockcontrol_m2, type3_table[i].m2);
 738
 739                 /* Reset */
 740                 sb_watchdog(sbh, 1);
 741                 while (1);
 742         } else if ((pll_type == PLL_TYPE2) ||
 743                    (pll_type == PLL_TYPE4) ||
 744                    (pll_type == PLL_TYPE6)) {
 745                 n4m_table_t *table = NULL;
 746                 uint tabsz = 0;
 747
 748                 ASSERT(cc);
 749
 750                 orig_mips = R_REG(&cc->clockcontrol_mips);
 751
 752                 if (pll_type == PLL_TYPE6) {
 753                         uint32 new_mips = 0;
 754
 755                         ret = TRUE;
 756                         if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
 757                                 new_mips = CC_T6_MMASK;
 758
 759                         if (orig_mips == new_mips)
 760                                 goto done;
 761
 762                         W_REG(&cc->clockcontrol_mips, new_mips);
 763                         goto end_fill;
 764                 }
 765
 766                 table = (pll_type == PLL_TYPE2) ? BCMINIT(type2_table) : BCMINIT(type4_table);
 767                 tabsz = (pll_type == PLL_TYPE2) ? ARRAYSIZE(BCMINIT(type2_table)) :
 768                         ARRAYSIZE(BCMINIT(type4_table));
 769
 770                 /* Store the current clock register values */
 771                 orig_m2 = R_REG(&cc->clockcontrol_m2);
 772                 orig_ratio_parm = 0;
 773
 774                 /* Look up current ratio */
 775                 for (i = 0; i < tabsz; i++) {
 776                         if ((orig_n == table[i].n) &&
 777                             (orig_sb == table[i].sb) &&
 778                             (orig_pci == table[i].pci33) &&
 779                             (orig_m2 == table[i].m2) &&
 780                             (orig_mips == table[i].m3)) {
 781                                 orig_ratio_parm = table[i].ratio_parm;
 782                                 break;
 783                         }
 784                 }
 785
 786                 /* Search for the closest MIPS clock greater or equal to a preferred value */
 787                 for (i = 0; i < tabsz; i++) {
 788                         ASSERT(table[i].mipsclock ==
 789                                sb_clock_rate(pll_type, table[i].n, table[i].m3));
 790                         if ((mipsclock <= table[i].mipsclock) &&
 791                             ((sbclock == 0) || (sbclock <= table[i].sbclock)))
 792                                 break;
 793                 }
 794                 if (i == tabsz) {
 795                         ret = FALSE;
 796                         goto done;
 797                 } else {
 798                         ret = TRUE;
 799                 }
 800
 801                 /* No PLL change */
 802                 if ((orig_n == table[i].n) &&
 803                     (orig_sb == table[i].sb) &&
 804                     (orig_pci == table[i].pci33) &&
 805                     (orig_m2 == table[i].m2) &&
 806                     (orig_mips == table[i].m3))
 807                         goto done;
 808
 809                 /* Set the PLL controls */
 810                 W_REG(clockcontrol_n, table[i].n);
 811                 W_REG(clockcontrol_sb, table[i].sb);
 812                 W_REG(clockcontrol_pci, table[i].pci33);
 813                 W_REG(&cc->clockcontrol_m2, table[i].m2);
 814                 W_REG(&cc->clockcontrol_mips, table[i].m3);
 815
 816                 /* No ratio change */
 817                 if (orig_ratio_parm == table[i].ratio_parm)
 818                         goto end_fill;
 819
 820                 new_ratio = table[i].ratio_parm;
 821
 822                 icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
 823
 824                 /* Preload the code into the cache */
 825                 start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
 826                 end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
 827                 while (start < end) {
 828                         cache_unroll(start, Fill_I);
 829                         start += ic_lsize;
 830                 }
 831
 832                 /* Copy the handler */
 833                 start = (ulong) &BCMINIT(handler);
 834                 end = (ulong) &BCMINIT(afterhandler);
 835                 dst = KSEG1ADDR(0x180);
 836                 for (i = 0; i < (end - start); i += 4)
 837                         *((ulong *)(dst + i)) = *((ulong *)(start + i));
 838
 839                 /* Preload handler into the cache one line at a time */
 840                 for (i = 0; i < (end - start); i += 4)
 841                         cache_unroll(dst + i, Fill_I);
 842
 843                 /* Clear BEV bit */
 844                 MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
 845
 846                 /* Enable interrupts */
 847                 MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
 848
 849                 /* Enable MIPS timer interrupt */
 850                 if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
 851                     !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
 852                         ASSERT(mipsr);
 853                 W_REG(&mipsr->intmask, 1);
 854
 855         start_fill:
 856                 /* step 1, set clock ratios */
 857                 MTC0(C0_BROADCOM, 3, new_ratio);
 858                 MTC0(C0_BROADCOM, 1, 8);
 859
 860                 /* step 2: program timer intr */
 861                 W_REG(&mipsr->timer, 100);
 862                 (void) R_REG(&mipsr->timer);
 863
 864                 /* step 3, switch to async */
 865                 sync_mode = MFC0(C0_BROADCOM, 4);
 866                 MTC0(C0_BROADCOM, 4, 1 << 22);
 867
 868                 /* step 4, set cfg active */
 869                 MTC0(C0_BROADCOM, 2, 0x9);
 870
 871
 872                 /* steps 5 & 6 */
 873                 __asm__ __volatile__ (
 874                         ".set\tmips3\n\t"
 875                         "wait\n\t"
 876                         ".set\tmips0"
 877                 );
 878
 879                 /* step 7, clear cfg_active */
 880                 MTC0(C0_BROADCOM, 2, 0);
 881
 882                 /* Additional Step: set back to orig sync mode */
 883                 MTC0(C0_BROADCOM, 4, sync_mode);
 884
 885                 /* step 8, fake soft reset */
 886                 MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
 887
 888         end_fill:
 889                 /* step 9 set watchdog timer */
 890                 sb_watchdog(sbh, 20);
 891                 (void) R_REG(&cc->chipid);
 892
 893                 /* step 11 */
 894                 __asm__ __volatile__ (
 895                         ".set\tmips3\n\t"
 896                         "sync\n\t"
 897                         "wait\n\t"
 898                         ".set\tmips0"
 899                 );
 900                 while (1);
 901         }
 902
 903 done:
 904         /* switch back to previous core */
 905         sb_setcoreidx(sbh, idx);
 906
 907         return ret;
 908 }
 909
 910
 911 /* returns the ncdl value to be programmed into sdram_ncdl for calibration */
 912 uint32
 913 BCMINITFN(sb_memc_get_ncdl)(void *sbh)
 914 {
 915         sbmemcregs_t *memc;
 916         uint32 ret = 0;
 917         uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
 918         uint idx, rev;
 919
 920         idx = sb_coreidx(sbh);
 921
 922         memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
 923         if (memc == 0)
 924                 goto out;
 925
 926         rev = sb_corerev(sbh);
 927
 928         config = R_REG(&memc->config);
 929         wr = R_REG(&memc->wrncdlcor);
 930         rd = R_REG(&memc->rdncdlcor);
 931         misc = R_REG(&memc->miscdlyctl);
 932         dqsg = R_REG(&memc->dqsgatencdl);
 933
 934         rd &= MEMC_RDNCDLCOR_RD_MASK;
 935         wr &= MEMC_WRNCDLCOR_WR_MASK;
 936         dqsg &= MEMC_DQSGATENCDL_G_MASK;
 937
 938         if (config & MEMC_CONFIG_DDR) {
 939                 ret = (wr << 16) | (rd << 8) | dqsg;
 940         } else {
 941                 if ( (rev > 0)  || (sb_chip(sbh) == BCM5365_DEVICE_ID))
 942
 943                         cd = rd;
 944                 else
 945                         cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
 946                 sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
 947                 sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
 948                 ret = (sm << 16) | (sd << 8) | cd;
 949         }
 950
 951 out:
 952         /* switch back to previous core */
 953         sb_setcoreidx(sbh, idx);
 954
 955         return ret;
 956 }
 957
 958 /* returns the PFC values to be used based on the chip ID*/
 959
 960 uint32
 961 BCMINITFN(sb_mips_get_pfc)(void *sbh)
 962 {
 963         if (BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID)
 964                 return 0x11;
 965         else
 966                 return 0x15;
 967 }