release/src-rt/shared/siutils_priv.h

   1 /*
   2  * Include file private to the SOC Interconnect support files.
   3  *
   4  * Copyright (C) 2009, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: siutils_priv.h,v 1.3.2.6 2010/02/18 02:09:37 Exp $
  13  */
  14
  15 #ifndef _siutils_priv_h_
  16 #define _siutils_priv_h_
  17
  18 #define SI_ERROR(args)
  19
  20 #define SI_MSG(args)
  21
  22 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
  23 #define SI_VMSG(args)
  24
  25 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
  26
  27
  28 typedef uint32 (*si_intrsoff_t)(void *intr_arg);
  29 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
  30 typedef bool (*si_intrsenabled_t)(void *intr_arg);
  31
  32 typedef struct gpioh_item {
  33         void                    *arg;
  34         bool                    level;
  35         gpio_handler_t          handler;
  36         uint32                  event;
  37         struct gpioh_item       *next;
  38 } gpioh_item_t;
  39
  40 /* misc si info needed by some of the routines */
  41 typedef struct si_info {
  42         struct si_pub pub;              /* back plane public state (must be first field) */
  43
  44         void    *osh;                   /* osl os handle */
  45         void    *sdh;                   /* bcmsdh handle */
  46
  47         uint    dev_coreid;             /* the core provides driver functions */
  48         void    *intr_arg;              /* interrupt callback function arg */
  49         si_intrsoff_t intrsoff_fn;      /* turns chip interrupts off */
  50         si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
  51         si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
  52
  53         void *pch;                      /* PCI/E core handle */
  54
  55         gpioh_item_t *gpioh_head;       /* GPIO event handlers list */
  56
  57         bool    memseg;                 /* flag to toggle MEM_SEG register */
  58
  59         char *vars;
  60         uint varsz;
  61
  62         void    *curmap;                /* current regs va */
  63         void    *regs[SI_MAXCORES];     /* other regs va */
  64
  65         uint    curidx;                 /* current core index */
  66         uint    numcores;               /* # discovered cores */
  67         uint    coreid[SI_MAXCORES];    /* id of each core */
  68         uint32  coresba[SI_MAXCORES];   /* backplane address of each core */
  69         void    *regs2[SI_MAXCORES];    /* va of each core second register set (usbh20) */
  70         uint32  coresba2[SI_MAXCORES];  /* address of each core second register set (usbh20) */
  71         uint32  coresba_size[SI_MAXCORES]; /* backplane address space size */
  72         uint32  coresba2_size[SI_MAXCORES]; /* second address space size */
  73
  74         void    *curwrap;               /* current wrapper va */
  75         void    *wrappers[SI_MAXCORES]; /* other cores wrapper va */
  76         uint32  wrapba[SI_MAXCORES];    /* address of controlling wrapper */
  77
  78         uint32  cia[SI_MAXCORES];       /* erom cia entry for each core */
  79         uint32  cib[SI_MAXCORES];       /* erom cia entry for each core */
  80         uint32  oob_router;             /* oob router registers for axi */
  81 } si_info_t;
  82
  83 #define SI_INFO(sih)    (si_info_t *)(uintptr)sih
  84
  85 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
  86                 ISALIGNED((x), SI_CORE_SIZE))
  87 #define GOODREGS(regs)  ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
  88 #define BADCOREADDR     0
  89 #define GOODIDX(idx)    (((uint)idx) < SI_MAXCORES)
  90 #define BADIDX          (SI_MAXCORES + 1)
  91 #define NOREV           -1              /* Invalid rev */
  92
  93 #define PCI(si)         ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
  94                          ((si)->pub.buscoretype == PCI_CORE_ID))
  95 #define PCIE(si)        ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
  96                          ((si)->pub.buscoretype == PCIE_CORE_ID))
  97 #define PCMCIA(si)      ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
  98
  99 /* Newer chips can access PCI/PCIE and CC core without requiring to change
 100  * PCI BAR0 WIN
 101  */
 102 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
 103                      (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
 104
 105 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
 106 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
 107
 108 /*
 109  * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
 110  * after core switching to avoid invalid register accesss inside ISR.
 111  */
 112 #define INTR_OFF(si, intr_val) \
 113         if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {      \
 114                 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
 115 #define INTR_RESTORE(si, intr_val) \
 116         if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {  \
 117                 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
 118
 119 /* dynamic clock control defines */
 120 #define LPOMINFREQ              25000           /* low power oscillator min */
 121 #define LPOMAXFREQ              43000           /* low power oscillator max */
 122 #define XTALMINFREQ             19800000        /* 20 MHz - 1% */
 123 #define XTALMAXFREQ             20200000        /* 20 MHz + 1% */
 124 #define PCIMINFREQ              25000000        /* 25 MHz */
 125 #define PCIMAXFREQ              34000000        /* 33 MHz + fudge */
 126
 127 #define ILP_DIV_5MHZ            0               /* ILP = 5 MHz */
 128 #define ILP_DIV_1MHZ            4               /* ILP = 1 MHz */
 129
 130 #define PCI_FORCEHT(si) \
 131         (((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
 132         ((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \
 133         (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID)) || \
 134         (PCIE(si) && (si->pub.chip == BCM4748_CHIP_ID)))
 135
 136 /* GPIO Based LED powersave defines */
 137 #define DEFAULT_GPIO_ONTIME     10              /* Default: 10% on */
 138 #define DEFAULT_GPIO_OFFTIME    90              /* Default: 10% on */
 139
 140 #ifndef DEFAULT_GPIOTIMERVAL
 141 #define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
 142 #endif
 143
 144 /* Silicon Backplane externs */
 145 extern void sb_scan(si_t *sih, void *regs, uint devid);
 146 extern uint sb_coreid(si_t *sih);
 147 extern uint sb_flag(si_t *sih);
 148 extern void sb_setint(si_t *sih, int siflag);
 149 extern uint sb_corevendor(si_t *sih);
 150 extern uint sb_corerev(si_t *sih);
 151 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 152 extern bool sb_iscoreup(si_t *sih);
 153 extern void *sb_setcoreidx(si_t *sih, uint coreidx);
 154 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
 155 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 156 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
 157 extern void sb_commit(si_t *sih);
 158 extern uint32 sb_base(uint32 admatch);
 159 extern uint32 sb_size(uint32 admatch);
 160 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 161 extern void sb_core_tofixup(si_t *sih);
 162 extern void sb_core_disable(si_t *sih, uint32 bits);
 163 extern uint32 sb_addrspace(si_t *sih, uint asidx);
 164 extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
 165 extern int sb_numaddrspaces(si_t *sih);
 166
 167 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
 168
 169 extern bool sb_taclear(si_t *sih, bool details);
 170
 171 #if defined(BCMDBG_DUMP)
 172 extern void sb_dump(si_t *sih, struct bcmstrbuf *b);
 173 #endif
 174 #if defined(BCMDBG_DUMP)
 175 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
 176 #endif
 177
 178 /* Wake-on-wireless-LAN (WOWL) */
 179 extern bool sb_pci_pmecap(si_t *sih);
 180 struct osl_info;
 181 extern bool sb_pci_fastpmecap(struct osl_info *osh);
 182 extern bool sb_pci_pmeclr(si_t *sih);
 183 extern void sb_pci_pmeen(si_t *sih);
 184 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
 185
 186 /* AMBA Interconnect exported externs */
 187 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 188                        void *sdh, char **vars, uint *varsz);
 189 extern si_t *ai_kattach(osl_t *osh);
 190 extern void ai_scan(si_t *sih, void *regs, uint devid);
 191
 192 extern uint ai_flag(si_t *sih);
 193 extern void ai_setint(si_t *sih, int siflag);
 194 extern uint ai_coreidx(si_t *sih);
 195 extern uint ai_corevendor(si_t *sih);
 196 extern uint ai_corerev(si_t *sih);
 197 extern bool ai_iscoreup(si_t *sih);
 198 extern void *ai_setcoreidx(si_t *sih, uint coreidx);
 199 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
 200 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 201 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
 202 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 203 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 204 extern void ai_core_disable(si_t *sih, uint32 bits);
 205 extern int ai_numaddrspaces(si_t *sih);
 206 extern uint32 ai_addrspace(si_t *sih, uint asidx);
 207 extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
 208
 209 #if defined(BCMDBG_DUMP)
 210 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
 211 #endif
 212
 213 #endif  /* _siutils_priv_h_ */