release/src-rt/include/siutils.h

   1 /*
   2  * Misc utility routines for accessing the SOC Interconnects
   3  * of Broadcom HNBU chips.
   4  *
   5  * Copyright (C) 2009, Broadcom Corporation
   6  * All Rights Reserved.
   7  *
   8  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   9  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  10  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  11  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  12  *
  13  * $Id: siutils.h,v 13.211.2.14 2009/06/18 12:19:28 Exp $
  14  */
  15
  16 #ifndef _siutils_h_
  17 #define _siutils_h_
  18
  19 #if defined(WLC_HIGH) && !defined(WLC_LOW)
  20 #include "bcm_rpc.h"
  21 #endif
  22 /*
  23  * Data structure to export all chip specific common variables
  24  *   public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
  25  */
  26 struct si_pub {
  27         uint    socitype;               /* SOCI_SB, SOCI_AI */
  28
  29         uint    bustype;                /* SI_BUS, PCI_BUS */
  30         uint    buscoretype;            /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
  31         uint    buscorerev;             /* buscore rev */
  32         uint    buscoreidx;             /* buscore index */
  33         int     ccrev;                  /* chip common core rev */
  34         uint32  cccaps;                 /* chip common capabilities */
  35         int     pmurev;                 /* pmu core rev */
  36         uint32  pmucaps;                /* pmu capabilities */
  37         uint    boardtype;              /* board type */
  38         uint    boardvendor;            /* board vendor */
  39         uint    boardflags;             /* board flags */
  40         uint    chip;                   /* chip number */
  41         uint    chiprev;                /* chip revision */
  42         uint    chippkg;                /* chip package option */
  43         uint32  chipst;                 /* chip status */
  44         bool    issim;                  /* chip is in simulation or emulation */
  45         uint    socirev;                /* SOC interconnect rev */
  46         bool    pci_pr32414;
  47
  48 #if defined(WLC_HIGH) && !defined(WLC_LOW)
  49         rpc_info_t *rpc;
  50 #endif
  51 };
  52
  53 /* for HIGH_ONLY driver, the si_t must be writeable to allow states sync from BMAC to HIGH driver
  54  * for monolithic driver, it is readonly to prevent accident change
  55  */
  56 #if defined(WLC_HIGH) && !defined(WLC_LOW)
  57 typedef struct si_pub si_t;
  58 #else
  59 typedef const struct si_pub si_t;
  60 #endif
  61
  62 /*
  63  * Many of the routines below take an 'sih' handle as their first arg.
  64  * Allocate this by calling si_attach().  Free it by calling si_detach().
  65  * At any one time, the sih is logically focused on one particular si core
  66  * (the "current core").
  67  * Use si_setcore() or si_setcoreidx() to change the association to another core.
  68  */
  69 #define SI_OSH          NULL    /* Use for si_kattach when no osh is available */
  70
  71 /* clkctl xtal what flags */
  72 #define XTAL                    0x1     /* primary crystal oscillator (2050) */
  73 #define PLL                     0x2     /* main chip pll */
  74
  75 /* clkctl clk mode */
  76 #define CLK_FAST                0       /* force fast (pll) clock */
  77 #define CLK_DYNAMIC             2       /* enable dynamic clock control */
  78
  79 /* GPIO usage priorities */
  80 #define GPIO_DRV_PRIORITY       0       /* Driver */
  81 #define GPIO_APP_PRIORITY       1       /* Application */
  82 #define GPIO_HI_PRIORITY        2       /* Highest priority. Ignore GPIO reservation */
  83
  84 /* GPIO pull up/down */
  85 #define GPIO_PULLUP             0
  86 #define GPIO_PULLDN             1
  87
  88 /* GPIO event regtype */
  89 #define GPIO_REGEVT             0       /* GPIO register event */
  90 #define GPIO_REGEVT_INTMSK      1       /* GPIO register event int mask */
  91 #define GPIO_REGEVT_INTPOL      2       /* GPIO register event int polarity */
  92
  93 /* device path */
  94 #define SI_DEVPATH_BUFSZ        16      /* min buffer size in bytes */
  95
  96 /* SI routine enumeration: to be used by update function with multiple hooks */
  97 #define SI_DOATTACH     1
  98 #define SI_PCIDOWN      2
  99 #define SI_PCIUP        3
 100
 101 #if defined(BCMQT)
 102 #define ISSIM_ENAB(sih) ((sih)->issim)
 103 #else
 104 #define ISSIM_ENAB(sih) 0
 105 #endif
 106
 107 /* PMU clock/power control */
 108 #if defined(BCMPMUCTL)
 109 #define PMUCTL_ENAB(sih)        (BCMPMUCTL)
 110 #else
 111 #define PMUCTL_ENAB(sih)        ((sih)->cccaps & CC_CAP_PMU)
 112 #endif
 113
 114 /* chipcommon clock/power control (exclusive with PMU's) */
 115 #if defined(BCMPMUCTL) && BCMPMUCTL
 116 #define CCCTL_ENAB(sih)         (0)
 117 #define CCPLL_ENAB(sih)         (0)
 118 #else
 119 #define CCCTL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PWR_CTL)
 120 #define CCPLL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PLL_MASK)
 121 #endif
 122
 123 typedef void (*gpio_handler_t)(uint32 stat, void *arg);
 124
 125
 126 /* === exported functions === */
 127 extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 128                        void *sdh, char **vars, uint *varsz);
 129 extern si_t *si_kattach(osl_t *osh);
 130 extern void si_detach(si_t *sih);
 131 extern bool si_pci_war16165(si_t *sih);
 132
 133 extern uint si_corelist(si_t *sih, uint coreid[]);
 134 extern uint si_coreid(si_t *sih);
 135 extern uint si_flag(si_t *sih);
 136 extern uint si_intflag(si_t *sih);
 137 extern uint si_coreidx(si_t *sih);
 138 extern uint si_coreunit(si_t *sih);
 139 extern uint si_corevendor(si_t *sih);
 140 extern uint si_corerev(si_t *sih);
 141 extern void *si_osh(si_t *sih);
 142 extern void si_setosh(si_t *sih, osl_t *osh);
 143 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 144 extern void *si_coreregs(si_t *sih);
 145 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
 146 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 147 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
 148 extern bool si_iscoreup(si_t *sih);
 149 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
 150 extern void *si_setcoreidx(si_t *sih, uint coreidx);
 151 extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
 152 extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
 153 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
 154 extern int si_numaddrspaces(si_t *sih);
 155 extern uint32 si_addrspace(si_t *sih, uint asidx);
 156 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
 157 extern int si_corebist(si_t *sih);
 158 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 159 extern void si_core_tofixup(si_t *sih);
 160 extern void si_core_disable(si_t *sih, uint32 bits);
 161 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
 162 extern uint32 si_clock(si_t *sih);
 163 extern uint32 si_alp_clock(si_t *sih);
 164 extern uint32 si_ilp_clock(si_t *sih);
 165 extern void si_pci_setup(si_t *sih, uint coremask);
 166 extern void si_pcmcia_init(si_t *sih);
 167 extern void si_setint(si_t *sih, int siflag);
 168 extern bool si_backplane64(si_t *sih);
 169 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
 170         void *intrsenabled_fn, void *intr_arg);
 171 extern void si_deregister_intr_callback(si_t *sih);
 172 extern void si_clkctl_init(si_t *sih);
 173 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
 174 extern bool si_clkctl_cc(si_t *sih, uint mode);
 175 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
 176 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
 177 extern bool si_backplane64(si_t *sih);
 178 extern void si_btcgpiowar(si_t *sih);
 179 extern bool si_deviceremoved(si_t *sih);
 180 extern uint32 si_socram_size(si_t *sih);
 181
 182 extern void si_watchdog(si_t *sih, uint ticks);
 183 extern void si_watchdog_ms(si_t *sih, uint32 ms);
 184 extern void *si_gpiosetcore(si_t *sih);
 185 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 186 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 187 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 188 extern uint32 si_gpioin(si_t *sih);
 189 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 190 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 191 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
 192 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
 193 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
 194 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
 195 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
 196 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
 197
 198 /* GPIO event handlers */
 199 extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg);
 200 extern void si_gpio_handler_unregister(si_t *sih, void* gpioh);
 201 extern void si_gpio_handler_process(si_t *sih);
 202
 203 /* Wake-on-wireless-LAN (WOWL) */
 204 extern bool si_pci_pmecap(si_t *sih);
 205 struct osl_info;
 206 extern bool si_pci_fastpmecap(struct osl_info *osh);
 207 extern bool si_pci_pmestat(si_t *sih);
 208 extern void si_pci_pmeclr(si_t *sih);
 209 extern void si_pci_pmeen(si_t *sih);
 210 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
 211
 212
 213 extern uint16 si_d11_devid(si_t *sih);
 214 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
 215         uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
 216
 217 #ifdef BCMECICOEX
 218 extern void *si_eci_init(si_t *sih);
 219 extern void si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val);
 220 #else
 221 #define si_eci_init(sih) (0)
 222 #define si_eci_notify_bt(sih, type, val)  (0)
 223 #endif /* BCMECICOEX */
 224
 225 /* OTP status */
 226 extern bool si_is_otp_disabled(si_t *sih);
 227 extern bool si_is_otp_powered(si_t *sih);
 228 extern void si_otp_power(si_t *sih, bool on);
 229
 230 /* SPROM availability */
 231 extern bool si_is_sprom_available(si_t *sih);
 232
 233 /* OTP/SROM CIS stuff */
 234 extern int si_cis_source(si_t *sih);
 235 #define CIS_DEFAULT     0
 236 #define CIS_SROM        1
 237 #define CIS_OTP         2
 238
 239 /*
 240  * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
 241  * The returned path is NULL terminated and has trailing '/'.
 242  * Return 0 on success, nonzero otherwise.
 243  */
 244 extern int si_devpath(si_t *sih, char *path, int size);
 245 /* Read variable with prepending the devpath to the name */
 246 extern char *si_getdevpathvar(si_t *sih, const char *name);
 247 extern int si_getdevpathintvar(si_t *sih, const char *name);
 248
 249
 250 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
 251 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
 252 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
 253 extern void si_pci_sleep(si_t *sih);
 254 extern void si_pci_down(si_t *sih);
 255 extern void si_pci_up(si_t *sih);
 256 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
 257 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
 258 extern int si_pci_fixcfg(si_t *sih);
 259 extern bool si_ldo_war(si_t *sih, uint devid);
 260
 261 /* === debug routines === */
 262
 263 extern bool si_taclear(si_t *sih, bool details);
 264
 265
 266 #if defined(BCMDBG_DUMP)
 267 extern void si_dump(si_t *sih, struct bcmstrbuf *b);
 268 extern void si_ccreg_dump(si_t *sih, struct bcmstrbuf *b);
 269 extern void si_clkctl_dump(si_t *sih, struct bcmstrbuf *b);
 270 extern int si_gpiodump(si_t *sih, struct bcmstrbuf *b);
 271 #endif
 272 #if defined(BCMDBG_DUMP)
 273 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
 274 #endif
 275 extern void si_4329_vbatmeas_on(si_t *sih, uint32 *save_reg0, uint32 *save_reg5);
 276 extern void si_4329_vbatmeas_off(si_t *sih, uint32 save_reg0, uint32 save_reg5);
 277
 278 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
 279
 280 #endif  /* _siutils_h_ */