release/src-rt/include/sbsocram.h

   1 /*
   2  * BCM47XX Sonics SiliconBackplane embedded ram core
   3  *
   4  * Copyright (C) 2009, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: sbsocram.h,v 13.9.96.1 2009/06/18 12:19:28 Exp $
  13  */
  14
  15 #ifndef _SBSOCRAM_H
  16 #define _SBSOCRAM_H
  17
  18 #ifndef _LANGUAGE_ASSEMBLY
  19
  20 /* cpp contortions to concatenate w/arg prescan */
  21 #ifndef PAD
  22 #define _PADLINE(line)  pad ## line
  23 #define _XSTR(line)     _PADLINE(line)
  24 #define PAD             _XSTR(__LINE__)
  25 #endif  /* PAD */
  26
  27 /* Memcsocram core registers */
  28 typedef volatile struct sbsocramregs {
  29         uint32  coreinfo;
  30         uint32  bwalloc;
  31         uint32  PAD;
  32         uint32  biststat;
  33         uint32  bankidx;
  34         uint32  standbyctrl;
  35         uint32  PAD[116];
  36         uint32  pwrctl;         /* corerev >= 2 */
  37 } sbsocramregs_t;
  38
  39 #endif  /* _LANGUAGE_ASSEMBLY */
  40
  41 /* Register offsets */
  42 #define SR_COREINFO             0x00
  43 #define SR_BWALLOC              0x04
  44 #define SR_BISTSTAT             0x0c
  45 #define SR_BANKINDEX            0x10
  46 #define SR_BANKSTBYCTL          0x14
  47 #define SR_PWRCTL               0x1e8
  48
  49 /* Coreinfo register */
  50 #define SRCI_PT_MASK            0x00030000
  51 #define SRCI_PT_SHIFT           16
  52 /* port types : SRCI_PT_<processorPT>_<backplanePT> */
  53 #define SRCI_PT_CM3AHB_OCP      3
  54 /* corerev >= 3 */
  55 #define SRCI_LSS_MASK           0x00f00000
  56 #define SRCI_LSS_SHIFT          20
  57 #define SRCI_LRS_MASK           0x0f000000
  58 #define SRCI_LRS_SHIFT          24
  59
  60 /* In corerev 0, the memory size is 2 to the power of the
  61  * base plus 16 plus to the contents of the memsize field plus 1.
  62  */
  63 #define SRCI_MS0_MASK           0xf
  64 #define SR_MS0_BASE             16
  65
  66 /*
  67  * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
  68  * the memory size is number of banks times bank size.
  69  * The same applies to rom size.
  70  */
  71 #define SRCI_ROMNB_MASK         0xf000
  72 #define SRCI_ROMNB_SHIFT        12
  73 #define SRCI_ROMBSZ_MASK        0xf00
  74 #define SRCI_ROMBSZ_SHIFT       8
  75 #define SRCI_SRNB_MASK          0xf0
  76 #define SRCI_SRNB_SHIFT         4
  77 #define SRCI_SRBSZ_MASK         0xf
  78 #define SRCI_SRBSZ_SHIFT        0
  79
  80 #define SR_BSZ_BASE             14
  81
  82 /* Standby control register */
  83 #define SRSC_SBYOVR_MASK        0x80000000
  84 #define SRSC_SBYOVR_SHIFT       31
  85 #define SRSC_SBYOVRVAL_MASK     0x60000000
  86 #define SRSC_SBYOVRVAL_SHIFT    29
  87 #define SRSC_SBYEN_MASK         0x01000000      /* rev >= 3 */
  88 #define SRSC_SBYEN_SHIFT        24
  89
  90 /* Power control register */
  91 #define SRPC_PMU_STBYDIS_MASK   0x00000010      /* rev >= 3 */
  92 #define SRPC_PMU_STBYDIS_SHIFT  4
  93 #define SRPC_STBYOVRVAL_MASK    0x00000008
  94 #define SRPC_STBYOVRVAL_SHIFT   3
  95 #define SRPC_STBYOVR_MASK       0x00000007
  96 #define SRPC_STBYOVR_SHIFT      0
  97
  98 #endif  /* _SBSOCRAM_H */