release/src-rt/include/sbsdpcmdev.h

   1 /*
   2  * Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific
   3  * device core support
   4  *
   5  * Copyright (C) 2009, Broadcom Corporation
   6  * All Rights Reserved.
   7  *
   8  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   9  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  10  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  11  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  12  *
  13  * $Id: sbsdpcmdev.h,v 13.31.2.2 2008/07/22 21:45:46 Exp $
  14  */
  15
  16 #ifndef _sbsdpcmdev_h_
  17 #define _sbsdpcmdev_h_
  18
  19 /* cpp contortions to concatenate w/arg prescan */
  20 #ifndef PAD
  21 #define _PADLINE(line)  pad ## line
  22 #define _XSTR(line)     _PADLINE(line)
  23 #define PAD             _XSTR(__LINE__)
  24 #endif  /* PAD */
  25
  26
  27 /* core registers */
  28 typedef volatile struct {
  29         uint32 corecontrol;             /* CoreControl, 0x000, rev8 */
  30         uint32 corestatus;              /* CoreStatus, 0x004, rev8  */
  31         uint32 PAD[1];
  32         uint32 biststatus;              /* BistStatus, 0x00c, rev8  */
  33
  34         /* PCMCIA access */
  35         uint16 pcmciamesportaladdr;     /* PcmciaMesPortalAddr, 0x010, rev8   */
  36         uint16 PAD[1];
  37         uint16 pcmciamesportalmask;     /* PcmciaMesPortalMask, 0x014, rev8   */
  38         uint16 PAD[1];
  39         uint16 pcmciawrframebc;         /* PcmciaWrFrameBC, 0x018, rev8   */
  40         uint16 PAD[1];
  41         uint16 pcmciaunderflowtimer;    /* PcmciaUnderflowTimer, 0x01c, rev8   */
  42         uint16 PAD[1];
  43
  44         /* interrupt */
  45         uint32 intstatus;               /* IntStatus, 0x020, rev8   */
  46         uint32 hostintmask;             /* IntHostMask, 0x024, rev8   */
  47         uint32 intmask;                 /* IntSbMask, 0x028, rev8   */
  48         uint32 sbintstatus;             /* SBIntStatus, 0x02c, rev8   */
  49         uint32 sbintmask;               /* SBIntMask, 0x030, rev8   */
  50         uint32 PAD[3];
  51         uint32 tosbmailbox;             /* ToSBMailbox, 0x040, rev8   */
  52         uint32 tohostmailbox;           /* ToHostMailbox, 0x044, rev8   */
  53         uint32 tosbmailboxdata;         /* ToSbMailboxData, 0x048, rev8   */
  54         uint32 tohostmailboxdata;       /* ToHostMailboxData, 0x04c, rev8   */
  55
  56         /* synchronized access to registers in SDIO clock domain */
  57         uint32 sdioaccess;              /* SdioAccess, 0x050, rev8   */
  58         uint32 PAD[3];
  59
  60         /* PCMCIA frame control */
  61         uint8 pcmciaframectrl;          /* pcmciaFrameCtrl, 0x060, rev8   */
  62         uint8 PAD[3];
  63         uint8 pcmciawatermark;          /* pcmciaWaterMark, 0x064, rev8   */
  64         uint8 PAD[155];
  65
  66         /* interrupt batching control */
  67         uint32 intrcvlazy;              /* IntRcvLazy, 0x100, rev8 */
  68         uint32 PAD[3];
  69
  70         /* counters */
  71         uint32 cmd52rd;                 /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
  72         uint32 cmd52wr;                 /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
  73         uint32 cmd53rd;                 /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
  74         uint32 cmd53wr;                 /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
  75         uint32 abort;                   /* AbortCount, 0x120, rev8, SDIO: aborts */
  76         uint32 datacrcerror;            /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
  77         uint32 rdoutofsync;             /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
  78         uint32 wroutofsync;             /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
  79         uint32 writebusy;               /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
  80         uint32 readwait;                /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
  81         uint32 readterm;                /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
  82         uint32 writeterm;               /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
  83         uint32 PAD[40];
  84         uint32 clockctlstatus;          /* ClockCtlStatus, 0x1e0, rev8 */
  85         uint32 PAD[7];
  86
  87         /* DMA engines */
  88         dma32regp_t dmaregs;            /* DMA Regs, 0x200-0x21c, rev8 */
  89         dma32diag_t dmafifo;            /* DMA Diagnostic Regs, 0x220-0x22c */
  90         uint32 PAD[116];
  91
  92         /* SDIO/PCMCIA CIS region */
  93         char cis[512];                  /* 512 byte CIS, 0x400-0x5ff, rev6 */
  94
  95         /* PCMCIA function control registers */
  96         char pcmciafcr[256];            /* PCMCIA FCR, 0x600-6ff, rev6 */
  97         uint16 PAD[55];
  98
  99         /* PCMCIA backplane access */
 100         uint16 backplanecsr;            /* BackplaneCSR, 0x76E, rev6 */
 101         uint16 backplaneaddr0;          /* BackplaneAddr0, 0x770, rev6 */
 102         uint16 backplaneaddr1;          /* BackplaneAddr1, 0x772, rev6 */
 103         uint16 backplaneaddr2;          /* BackplaneAddr2, 0x774, rev6 */
 104         uint16 backplaneaddr3;          /* BackplaneAddr3, 0x776, rev6 */
 105         uint16 backplanedata0;          /* BackplaneData0, 0x778, rev6 */
 106         uint16 backplanedata1;          /* BackplaneData1, 0x77a, rev6 */
 107         uint16 backplanedata2;          /* BackplaneData2, 0x77c, rev6 */
 108         uint16 backplanedata3;          /* BackplaneData3, 0x77e, rev6 */
 109         uint16 PAD[31];
 110
 111         /* sprom "size" & "blank" info */
 112         uint16 spromstatus;             /* SPROMStatus, 0x7BE, rev2 */
 113         uint32 PAD[464];
 114
 115         /* Sonics SiliconBackplane registers */
 116         sbconfig_t sbconfig;            /* SbConfig Regs, 0xf00-0xfff, rev8 */
 117 } sdpcmd_regs_t;
 118
 119 /* corecontrol */
 120 #define CC_CISRDY       (1L << 0)       /* CIS Ready */
 121 #define CC_BPRESEN      (1L << 1)       /* CCCR RES signal causes backplane reset */
 122 #define CC_F2RDY        (1L << 2)       /* set CCCR IOR2 bit */
 123 #define CC_CLRPADSISO   (1L << 3)       /* clear SDIO pads isolation bit (rev 11) */
 124
 125 /* corestatus */
 126 #define CS_PCMCIAMODE   (1L << 0)       /* Device Mode; 0=SDIO, 1=PCMCIA */
 127 #define CS_SMARTDEV     (1L << 1)       /* 1=smartDev enabled */
 128 #define CS_F2ENABLED    (1L << 2)       /* 1=host has enabled the device */
 129
 130 #define PCMCIA_MES_PA_MASK      0x7fff  /* PCMCIA Message Portal Address Mask */
 131 #define PCMCIA_MES_PM_MASK      0x7fff  /* PCMCIA Message Portal Mask Mask */
 132 #define PCMCIA_WFBC_MASK        0xffff  /* PCMCIA Write Frame Byte Count Mask */
 133 #define PCMCIA_UT_MASK          0x07ff  /* PCMCIA Underflow Timer Mask */
 134
 135 /* intstatus - hw defs */
 136 #define I_SMB_SW0       (1L << 0)       /* To SB Mail S/W interrupt 0 */
 137 #define I_SMB_SW1       (1L << 1)       /* To SB Mail S/W interrupt 1 */
 138 #define I_SMB_SW2       (1L << 2)       /* To SB Mail S/W interrupt 2 */
 139 #define I_SMB_SW3       (1L << 3)       /* To SB Mail S/W interrupt 3 */
 140 #define I_SMB_SW_MASK   0x0000000f      /* To SB Mail S/W interrupts mask */
 141 #define I_SMB_SW_SHIFT  0               /* To SB Mail S/W interrupts shift */
 142 #define I_HMB_SW0       (1L << 4)       /* To Host Mail S/W interrupt 0 */
 143 #define I_HMB_SW1       (1L << 5)       /* To Host Mail S/W interrupt 1 */
 144 #define I_HMB_SW2       (1L << 6)       /* To Host Mail S/W interrupt 2 */
 145 #define I_HMB_SW3       (1L << 7)       /* To Host Mail S/W interrupt 3 */
 146 #define I_HMB_SW_MASK   0x000000f0      /* To Host Mail S/W interrupts mask */
 147 #define I_HMB_SW_SHIFT  4               /* To Host Mail S/W interrupts shift */
 148 #define I_WR_OOSYNC     (1L << 8)       /* Write Frame Out Of Sync */
 149 #define I_RD_OOSYNC     (1L << 9)       /* Read Frame Out Of Sync */
 150 #define I_PC            (1L << 10)      /* descriptor error */
 151 #define I_PD            (1L << 11)      /* data error */
 152 #define I_DE            (1L << 12)      /* Descriptor protocol Error */
 153 #define I_RU            (1L << 13)      /* Receive descriptor Underflow */
 154 #define I_RO            (1L << 14)      /* Receive fifo Overflow */
 155 #define I_XU            (1L << 15)      /* Transmit fifo Underflow */
 156 #define I_RI            (1L << 16)      /* Receive Interrupt */
 157 #define I_BUSPWR        (1L << 17)      /* SDIO Bus Power Change (rev 9) */
 158 #define I_XI            (1L << 24)      /* Transmit Interrupt */
 159 #define I_RF_TERM       (1L << 25)      /* Read Frame Terminate */
 160 #define I_WF_TERM       (1L << 26)      /* Write Frame Terminate */
 161 #define I_PCMCIA_XU     (1L << 27)      /* PCMCIA Transmit FIFO Underflow */
 162 #define I_SBINT         (1L << 28)      /* sbintstatus Interrupt */
 163 #define I_CHIPACTIVE    (1L << 29)      /* chip transitioned from doze to active state */
 164 #define I_SRESET        (1L << 30)      /* CCCR RES interrupt */
 165 #define I_IOE2          (1L << 31)      /* CCCR IOE2 Bit Changed */
 166 #define I_ERRORS        (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)       /* DMA Errors */
 167 #define I_DMA           (I_RI | I_XI | I_ERRORS)
 168
 169 /* sbintstatus */
 170 #define I_SB_SERR       (1 << 8)        /* Backplane SError (write) */
 171 #define I_SB_RESPERR    (1 << 9)        /* Backplane Response Error (read) */
 172 #define I_SB_SPROMERR   (1 << 10)       /* Error accessing the sprom */
 173
 174 /* sdioaccess */
 175 #define SDA_DATA_MASK   0x000000ff      /* Read/Write Data Mask */
 176 #define SDA_ADDR_MASK   0x000fff00      /* Read/Write Address Mask */
 177 #define SDA_ADDR_SHIFT  8               /* Read/Write Address Shift */
 178 #define SDA_WRITE       0x01000000      /* Write bit  */
 179 #define SDA_READ        0x00000000      /* Write bit cleared for Read */
 180 #define SDA_BUSY        0x80000000      /* Busy bit */
 181
 182 /* sdioaccess-accessible register address spaces */
 183 #define SDA_CCCR_SPACE          0x000   /* sdioAccess CCCR register space */
 184 #define SDA_F1_FBR_SPACE        0x100   /* sdioAccess F1 FBR register space */
 185 #define SDA_F2_FBR_SPACE        0x200   /* sdioAccess F2 FBR register space */
 186 #define SDA_F1_REG_SPACE        0x300   /* sdioAccess F1 core-specific register space */
 187
 188 /* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
 189 #define SDA_CHIPCONTROLDATA     0x006   /* ChipControlData */
 190 #define SDA_CHIPCONTROLENAB     0x007   /* ChipControlEnable */
 191 #define SDA_F2WATERMARK         0x008   /* Function 2 Watermark */
 192 #define SDA_DEVICECONTROL       0x009   /* DeviceControl */
 193 #define SDA_SBADDRLOW           0x00a   /* SbAddrLow */
 194 #define SDA_SBADDRMID           0x00b   /* SbAddrMid */
 195 #define SDA_SBADDRHIGH          0x00c   /* SbAddrHigh */
 196 #define SDA_FRAMECTRL           0x00d   /* FrameCtrl */
 197 #define SDA_CHIPCLOCKCSR        0x00e   /* ChipClockCSR */
 198 #define SDA_SDIOPULLUP          0x00f   /* SdioPullUp */
 199 #define SDA_SDIOWRFRAMEBCLOW    0x019   /* SdioWrFrameBCLow */
 200 #define SDA_SDIOWRFRAMEBCHIGH   0x01a   /* SdioWrFrameBCHigh */
 201 #define SDA_SDIORDFRAMEBCLOW    0x01b   /* SdioRdFrameBCLow */
 202 #define SDA_SDIORDFRAMEBCHIGH   0x01c   /* SdioRdFrameBCHigh */
 203
 204 /* SDA_F2WATERMARK */
 205 #define SDA_F2WATERMARK_MASK    0x7f    /* F2Watermark Mask */
 206
 207 /* SDA_SBADDRLOW */
 208 #define SDA_SBADDRLOW_MASK      0x80    /* SbAddrLow Mask */
 209
 210 /* SDA_SBADDRMID */
 211 #define SDA_SBADDRMID_MASK      0xff    /* SbAddrMid Mask */
 212
 213 /* SDA_SBADDRHIGH */
 214 #define SDA_SBADDRHIGH_MASK     0xff    /* SbAddrHigh Mask */
 215
 216 /* SDA_FRAMECTRL */
 217 #define SFC_RF_TERM     (1 << 0)        /* Read Frame Terminate */
 218 #define SFC_WF_TERM     (1 << 1)        /* Write Frame Terminate */
 219 #define SFC_CRC4WOOS    (1 << 2)        /* HW reports CRC error for write out of sync */
 220 #define SFC_ABORTALL    (1 << 3)        /* Abort cancels all in-progress frames */
 221
 222 /* pcmciaframectrl */
 223 #define PFC_RF_TERM     (1 << 0)        /* Read Frame Terminate */
 224 #define PFC_WF_TERM     (1 << 1)        /* Write Frame Terminate */
 225
 226 /* intrcvlazy */
 227 #define IRL_TO_MASK     0x00ffffff      /* timeout */
 228 #define IRL_FC_MASK     0xff000000      /* frame count */
 229 #define IRL_FC_SHIFT    24              /* frame count */
 230
 231 /* rx header */
 232 typedef volatile struct {
 233         uint16 len;
 234         uint16 flags;
 235 } sdpcmd_rxh_t;
 236
 237 /* rx header flags */
 238 #define RXF_CRC         0x0001          /* CRC error detected */
 239 #define RXF_WOOS        0x0002          /* write frame out of sync */
 240 #define RXF_WF_TERM     0x0004          /* write frame terminated */
 241 #define RXF_ABORT       0x0008          /* write frame aborted */
 242 #define RXF_DISCARD     (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT)  /* bad frame */
 243
 244 /* HW frame tag */
 245 #define SDPCM_FRAMETAG_LEN      4       /* HW frametag: 2 bytes len, 2 bytes check val */
 246
 247 /*
 248  * *******************************************************************
 249  *                     SOFTWARE DEFINITIONS
 250  * *******************************************************************
 251  */
 252
 253 /* intstatus register */
 254 #define I_SMB_NAK       I_SMB_SW0       /* 0x1 - To SB Mailbox Frame NAK */
 255 #define I_SMB_INT_ACK   I_SMB_SW1       /* 0x2 - To SB Mailbox Host Interrupt ACK */
 256 #define I_SMB_USE_OOB   I_SMB_SW2       /* 0x4 - To SB Mailbox Use OOB Wakeup */
 257 #define I_SMB_DEV_INT   I_SMB_SW3       /* 0x8 - To SB Mailbox Miscellaneous Interrupt */
 258
 259 #define I_HMB_FC_STATE  I_HMB_SW0       /* 0x10 - To Host Mailbox Flow Control State */
 260 #define I_HMB_FC_CHANGE I_HMB_SW1       /* 0x20 - To Host Mailbox Flow Control State Changed */
 261 #define I_HMB_FRAME_IND I_HMB_SW2       /* 0x40 - To Host Mailbox Frame Indication */
 262 #define I_HMB_HOST_INT  I_HMB_SW3       /* 0x80 - To Host Mailbox Miscellaneous Interrupt */
 263
 264 #define I_TOSBMAIL      (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT)
 265 #define I_TOHOSTMAIL    (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT)
 266
 267 /* tosbmailbox */
 268 #define SMB_NAK         (1L << 0)       /* To SB Mailbox Frame NAK */
 269 #define SMB_INT_ACK     (1L << 1)       /* To SB Mailbox Host Interrupt ACK */
 270 #define SMB_USE_OOB     (1L << 2)       /* To SB Mailbox Use OOB Wakeup */
 271 #define SMB_DEV_INT     (1L << 3)       /* To SB Mailbox Miscellaneous Interrupt */
 272 #define SMB_MASK        0x0000000f      /* To SB Mailbox Mask */
 273
 274 /* tohostmailbox */
 275 #define HMB_FC_ON       (1L << 0)       /* To Host Mailbox Flow Control State=ON */
 276 #define HMB_FC_CHANGE   (1L << 1)       /* To Host Mailbox Flow Control State Changed */
 277 #define HMB_FRAME_IND   (1L << 2)       /* To Host Mailbox Frame Indication */
 278 #define HMB_HOST_INT    (1L << 3)       /* To Host Mailbox Miscellaneous Interrupt */
 279 #define HMB_MASK        0x0000000f      /* To Host Mailbox Mask */
 280
 281 /* tohostmailboxdata */
 282 #define HMB_DATA_NAKHANDLED     1       /* we're ready to retransmit NAK'd frame to host */
 283 #define HMB_DATA_DEVREADY       2       /* we're ready to to talk to host after enable */
 284 #define HMB_DATA_FC             4       /* per prio flowcontrol update flag to host */
 285 #define HMB_DATA_FWREADY        8       /* firmware is ready for protocol activity */
 286
 287 #define HMB_DATA_FCDATA_MASK    0xff    /* per prio flowcontrol data */
 288 #define HMB_DATA_FCDATA_SHIFT   24      /* per prio flowcontrol data */
 289
 290 #define HMB_DATA_VERSION_MASK   0xff    /* device protocol version (with devready) */
 291 #define HMB_DATA_VERSION_SHIFT  16      /* device protocol version (with devready) */
 292
 293 /* tosbmailboxdata */
 294 #define SMB_DATA_VERSION_MASK   0xff    /* host protocol version (with F2 enable) */
 295 #define SMB_DATA_VERSION_SHIFT  16      /* host protocol version (with F2 enable) */
 296
 297 /* current protocol version */
 298 #define SDPCM_PROT_VERSION      4
 299
 300 /* SW frame header */
 301 #define SDPCM_SEQUENCE_MASK             0x000000ff      /* Sequence Number Mask */
 302 #define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
 303
 304 #define SDPCM_CHANNEL_MASK              0x00000f00      /* Channel Number Mask */
 305 #define SDPCM_CHANNEL_SHIFT             8               /* Channel Number Shift */
 306 #define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
 307
 308 #define SDPCM_FLAGS_MASK                0x0000f000      /* Mask of flag bits */
 309 #define SDPCM_FLAGS_SHIFT               12              /* Flag bits shift */
 310 #define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
 311
 312 /* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
 313 #define SDPCM_NEXTLEN_MASK              0x00ff0000      /* Next Read Len Mask */
 314 #define SDPCM_NEXTLEN_SHIFT             16              /* Next Read Len Shift */
 315 #define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
 316 #define SDPCM_NEXTLEN_OFFSET            2
 317
 318 /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
 319 #define SDPCM_DOFFSET_OFFSET            3               /* Data Offset */
 320 #define SDPCM_DOFFSET_VALUE(p)          (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
 321 #define SDPCM_DOFFSET_MASK              0xff000000
 322 #define SDPCM_DOFFSET_SHIFT             24
 323
 324 #define SDPCM_FCMASK_OFFSET             4               /* Flow control */
 325 #define SDPCM_FCMASK_VALUE(p)           (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
 326 #define SDPCM_WINDOW_OFFSET             5               /* Credit based fc */
 327 #define SDPCM_WINDOW_VALUE(p)           (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
 328 #define SDPCM_VERSION_OFFSET            6               /* Version # */
 329 #define SDPCM_VERSION_VALUE(p)          (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
 330 #define SDPCM_UNUSED_OFFSET             7               /* Spare */
 331 #define SDPCM_UNUSED_VALUE(p)           (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
 332
 333 #define SDPCM_SWHEADER_LEN      8       /* SW header is 64 bits */
 334
 335 /* logical channel numbers */
 336 #define SDPCM_CONTROL_CHANNEL   0       /* Control Request/Response Channel Id */
 337 #define SDPCM_EVENT_CHANNEL     1       /* Asyc Event Indication Channel Id */
 338 #define SDPCM_DATA_CHANNEL      2       /* Data Xmit/Recv Channel Id */
 339 #define SDPCM_GLOM_CHANNEL      3       /* For coalesced packets (superframes) */
 340 #define SDPCM_TEST_CHANNEL      15      /* Reserved for test/debug packets */
 341 #define SDPCM_MAX_CHANNEL       15
 342
 343 #define SDPCM_SEQUENCE_WRAP     256     /* wrap-around val for eight-bit frame seq number */
 344
 345 /* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
 346 #define SDPCM_GLOMDESC_FLAG     0x00008000      /* Superframe descriptor mask */
 347 #define SDPCM_GLOMDESC(p)       (((uint8 *)p)[1] & 0x80)
 348
 349 /* For TEST_CHANNEL packets, define another 4-byte header */
 350 #define SDPCM_TEST_HDRLEN       4       /* Generally: Cmd(1), Ext(1), Len(2);
 351                                          * Semantics of Ext byte depend on command.
 352                                          * Len is current or requested frame length, not
 353                                          * including test header; sent little-endian.
 354                                          */
 355 #define SDPCM_TEST_DISCARD      0x01    /* Receiver discards. Ext is a pattern id. */
 356 #define SDPCM_TEST_ECHOREQ      0x02    /* Echo request. Ext is a pattern id. */
 357 #define SDPCM_TEST_ECHORSP      0x03    /* Echo response. Ext is a pattern id. */
 358 #define SDPCM_TEST_BURST        0x04    /* Receiver to send a burst. Ext is a frame count */
 359 #define SDPCM_TEST_SEND         0x05    /* Receiver sets send mode. Ext is boolean on/off */
 360
 361 /* Handy macro for filling in datagen packets with a pattern */
 362 #define SDPCM_TEST_FILL(byteno, id)     ((uint8)(id + byteno))
 363
 364
 365 /* software counters (copy of hardware counters plus additional ones) */
 366 typedef volatile struct {
 367         uint32 cmd52rd;         /* Cmd52RdCount, SDIO: cmd52 reads */
 368         uint32 cmd52wr;         /* Cmd52WrCount, SDIO: cmd52 writes */
 369         uint32 cmd53rd;         /* Cmd53RdCount, SDIO: cmd53 reads */
 370         uint32 cmd53wr;         /* Cmd53WrCount, SDIO: cmd53 writes */
 371         uint32 abort;           /* AbortCount, SDIO: aborts */
 372         uint32 datacrcerror;    /* DataCrcErrorCount, SDIO: frames w/CRC error */
 373         uint32 rdoutofsync;     /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
 374         uint32 wroutofsync;     /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
 375         uint32 writebusy;       /* WriteBusyCount, SDIO: device asserted "busy" */
 376         uint32 readwait;        /* ReadWaitCount, SDIO: no data ready for a read cmd */
 377         uint32 readterm;        /* ReadTermCount, SDIO: read frame termination cmds */
 378         uint32 writeterm;       /* WriteTermCount, SDIO: write frames termination cmds */
 379         uint32 rxdescuflo;      /* receive descriptor underflows */
 380         uint32 rxfifooflo;      /* receive fifo overflows */
 381         uint32 txfifouflo;      /* transmit fifo underflows */
 382         uint32 runt;            /* runt (too short) frames recv'd from bus */
 383         uint32 badlen;          /* frame's rxh len does not match its hw tag len */
 384         uint32 badcksum;        /* frame's hw tag chksum doesn't agree with len value */
 385         uint32 seqbreak;        /* break in sequence # space from one rx frame to the next */
 386         uint32 rxfcrc;          /* frame rx header indicates crc error */
 387         uint32 rxfwoos;         /* frame rx header indicates write out of sync */
 388         uint32 rxfwft;          /* frame rx header indicates write frame termination */
 389         uint32 rxfabort;        /* frame rx header indicates frame aborted */
 390         uint32 woosint;         /* write out of sync interrupt */
 391         uint32 roosint;         /* read out of sync interrupt */
 392         uint32 rftermint;       /* read frame terminate interrupt */
 393         uint32 wftermint;       /* write frame terminate interrupt */
 394 } sdpcmd_cnt_t;
 395
 396 #endif  /* _sbsdpcmdev_h_ */