release/src-rt/include/sbsdio.h

   1 /*
   2  * SDIO device core hardware definitions.
   3  * sdio is a portion of the pcmcia core in core rev 3 - rev 8
   4  *
   5  * SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
   6  *
   7  * Copyright (C) 2009, Broadcom Corporation
   8  * All Rights Reserved.
   9  *
  10  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  11  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  12  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  13  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  14  *
  15  * $Id: sbsdio.h,v 13.32 2008/02/19 10:00:06 Exp $
  16  */
  17
  18 #ifndef _SBSDIO_H
  19 #define _SBSDIO_H
  20
  21 #define SBSDIO_NUM_FUNCTION             3       /* as of sdiod rev 0, supports 3 functions */
  22
  23 /* function 1 miscellaneous registers */
  24 #define SBSDIO_SPROM_CS                 0x10000         /* sprom command and status */
  25 #define SBSDIO_SPROM_INFO               0x10001         /* sprom info register */
  26 #define SBSDIO_SPROM_DATA_LOW           0x10002         /* sprom indirect access data byte 0 */
  27 #define SBSDIO_SPROM_DATA_HIGH          0x10003         /* sprom indirect access data byte 1 */
  28 #define SBSDIO_SPROM_ADDR_LOW           0x10004         /* sprom indirect access addr byte 0 */
  29 #define SBSDIO_SPROM_ADDR_HIGH          0x10005         /* sprom indirect access addr byte 0 */
  30 #define SBSDIO_CHIP_CTRL_DATA           0x10006         /* xtal_pu (gpio) output */
  31 #define SBSDIO_CHIP_CTRL_EN             0x10007         /* xtal_pu (gpio) enable */
  32 #define SBSDIO_WATERMARK                0x10008         /* rev < 7, watermark for sdio device */
  33 #define SBSDIO_DEVICE_CTL               0x10009         /* control busy signal generation */
  34
  35 /* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
  36 #define SBSDIO_FUNC1_SBADDRLOW          0x1000A         /* SB Address Window Low (b15) */
  37 #define SBSDIO_FUNC1_SBADDRMID          0x1000B         /* SB Address Window Mid (b23:b16) */
  38 #define SBSDIO_FUNC1_SBADDRHIGH         0x1000C         /* SB Address Window High (b31:b24)    */
  39 #define SBSDIO_FUNC1_FRAMECTRL          0x1000D         /* Frame Control (frame term/abort) */
  40 #define SBSDIO_FUNC1_CHIPCLKCSR         0x1000E         /* ChipClockCSR (ALP/HT ctl/status) */
  41 #define SBSDIO_FUNC1_SDIOPULLUP         0x1000F         /* SdioPullUp (on cmd, d0-d2) */
  42 #define SBSDIO_FUNC1_WFRAMEBCLO         0x10019         /* Write Frame Byte Count Low */
  43 #define SBSDIO_FUNC1_WFRAMEBCHI         0x1001A         /* Write Frame Byte Count High */
  44 #define SBSDIO_FUNC1_RFRAMEBCLO         0x1001B         /* Read Frame Byte Count Low */
  45 #define SBSDIO_FUNC1_RFRAMEBCHI         0x1001C         /* Read Frame Byte Count High */
  46
  47 #define SBSDIO_FUNC1_MISC_REG_START     0x10000         /* f1 misc register start */
  48 #define SBSDIO_FUNC1_MISC_REG_LIMIT     0x1001C         /* f1 misc register end */
  49
  50 /* SBSDIO_SPROM_CS */
  51 #define SBSDIO_SPROM_IDLE               0
  52 #define SBSDIO_SPROM_WRITE              1
  53 #define SBSDIO_SPROM_READ               2
  54 #define SBSDIO_SPROM_WEN                4
  55 #define SBSDIO_SPROM_WDS                7
  56 #define SBSDIO_SPROM_DONE               8
  57
  58 /* SBSDIO_SPROM_INFO */
  59 #define SROM_SZ_MASK                    0x03            /* SROM size, 1: 4k, 2: 16k */
  60 #define SROM_BLANK                      0x04            /* depreciated in corerev 6 */
  61 #define SROM_OTP                        0x80            /* OTP present */
  62
  63 /* SBSDIO_CHIP_CTRL */
  64 #define SBSDIO_CHIP_CTRL_XTAL           0x01            /* or'd with onchip xtal_pu,
  65                                                          * 1: power on oscillator
  66                                                          * (for 4318 only)
  67                                                          */
  68 /* SBSDIO_WATERMARK */
  69 #define SBSDIO_WATERMARK_MASK           0x7f            /* number of words - 1 for sd device
  70                                                          * to wait before sending data to host
  71                                                          */
  72
  73 /* SBSDIO_DEVICE_CTL */
  74 #define SBSDIO_DEVCTL_SETBUSY           0x01            /* 1: device will assert busy signal when
  75                                                          * receiving CMD53
  76                                                          */
  77 #define SBSDIO_DEVCTL_SPI_INTR_SYNC     0x02            /* 1: assertion of sdio interrupt is
  78                                                          * synchronous to the sdio clock
  79                                                          */
  80 #define SBSDIO_DEVCTL_CA_INT_ONLY       0x04            /* 1: mask all interrupts to host
  81                                                          * except the chipActive (rev 8)
  82                                                          */
  83 #define SBSDIO_DEVCTL_PADS_ISO          0x08            /* 1: isolate internal sdio signals, put
  84                                                          * external pads in tri-state; requires
  85                                                          * sdio bus power cycle to clear (rev 9)
  86                                                          */
  87 #define SBSDIO_DEVCTL_SB_RST_CTL        0x30            /* Force SD->SB reset mapping (rev 11) */
  88 #define SBSDIO_DEVCTL_RST_CORECTL       0x00            /*   Determined by CoreControl bit */
  89 #define SBSDIO_DEVCTL_RST_BPRESET       0x10            /*   Force backplane reset */
  90 #define SBSDIO_DEVCTL_RST_NOBPRESET     0x20            /*   Force no backplane reset */
  91
  92
  93 /* SBSDIO_FUNC1_CHIPCLKCSR */
  94 #define SBSDIO_FORCE_ALP                0x01            /* Force ALP request to backplane */
  95 #define SBSDIO_FORCE_HT                 0x02            /* Force HT request to backplane */
  96 #define SBSDIO_FORCE_ILP                0x04            /* Force ILP request to backplane */
  97 #define SBSDIO_ALP_AVAIL_REQ            0x08            /* Make ALP ready (power up xtal) */
  98 #define SBSDIO_HT_AVAIL_REQ             0x10            /* Make HT ready (power up PLL) */
  99 #define SBSDIO_FORCE_HW_CLKREQ_OFF      0x20            /* Squelch clock requests from HW */
 100 #define SBSDIO_ALP_AVAIL                0x40            /* Status: ALP is ready */
 101 #define SBSDIO_HT_AVAIL                 0x80            /* Status: HT is ready */
 102 /* In rev8, actual avail bits followed original docs */
 103 #define SBSDIO_Rev8_HT_AVAIL            0x40
 104 #define SBSDIO_Rev8_ALP_AVAIL           0x80
 105
 106 #define SBSDIO_AVBITS                   (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
 107 #define SBSDIO_ALPAV(regval)            ((regval) & SBSDIO_AVBITS)
 108 #define SBSDIO_HTAV(regval)             (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
 109 #define SBSDIO_ALPONLY(regval)          (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
 110 #define SBSDIO_CLKAV(regval, alponly)   (SBSDIO_ALPAV(regval) && \
 111                                         (alponly ? 1 : SBSDIO_HTAV(regval)))
 112
 113 /* SBSDIO_FUNC1_SDIOPULLUP */
 114 #define SBSDIO_PULLUP_D0                0x01            /* Enable D0/MISO pullup */
 115 #define SBSDIO_PULLUP_D1                0x02            /* Enable D1/INT# pullup */
 116 #define SBSDIO_PULLUP_D2                0x04            /* Enable D2 pullup */
 117 #define SBSDIO_PULLUP_CMD               0x08            /* Enable CMD/MOSI pullup */
 118 #define SBSDIO_PULLUP_ALL               0x0f            /* All valid bits */
 119
 120 /* function 1 OCP space */
 121 #define SBSDIO_SB_OFT_ADDR_MASK         0x07FFF         /* sb offset addr is <= 15 bits, 32k */
 122 #define SBSDIO_SB_OFT_ADDR_LIMIT        0x08000
 123 #define SBSDIO_SB_ACCESS_2_4B_FLAG      0x08000         /* with b15, maps to 32-bit SB access */
 124
 125 /* some duplication with sbsdpcmdev.h here */
 126 /* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
 127 #define SBSDIO_SBADDRLOW_MASK   0x80                    /* Valid bits in SBADDRLOW */
 128 #define SBSDIO_SBADDRMID_MASK   0xff                    /* Valid bits in SBADDRMID */
 129 #define SBSDIO_SBADDRHIGH_MASK  0xff                    /* Valid bits in SBADDRHIGH */
 130 #define SBSDIO_SBWINDOW_MASK    0xffff8000              /* Address bits from SBADDR regs */
 131
 132 /* direct(mapped) cis space */
 133 #define SBSDIO_CIS_BASE_COMMON          0x1000          /* MAPPED common CIS address */
 134 #ifdef BCMSPI
 135 #define SBSDIO_CIS_SIZE_LIMIT           0x100           /* maximum bytes in one spi CIS */
 136 #else
 137 #define SBSDIO_CIS_SIZE_LIMIT           0x200           /* maximum bytes in one CIS */
 138 #endif /* !BCMSPI */
 139
 140 #define SBSDIO_CIS_OFT_ADDR_MASK        0x1FFFF         /* cis offset addr is < 17 bits */
 141
 142 #define SBSDIO_CIS_MANFID_TUPLE_LEN     6               /* manfid tuple length, include tuple,
 143                                                          * link bytes
 144                                                          */
 145
 146 /* indirect cis access (in sprom) */
 147 #define SBSDIO_SPROM_CIS_OFFSET         0x8             /* 8 control bytes first, CIS starts from
 148                                                          * 8th byte
 149                                                          */
 150
 151 #define SBSDIO_BYTEMODE_DATALEN_MAX     64              /* sdio byte mode: maximum length of one
 152                                                          * data comamnd
 153                                                          */
 154
 155 #define SBSDIO_CORE_ADDR_MASK           0x1FFFF         /* sdio core function one address mask */
 156
 157 #endif  /* _SBSDIO_H */