release/src-rt/include/pcie_core.h

   1 /*
   2  * BCM43XX PCIE core hardware definitions.
   3  *
   4  * Copyright (C) 2009, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: pcie_core.h,v 13.3.2.3 2009/02/20 02:00:00 Exp $
  13  */
  14 #ifndef _PCIE_CORE_H
  15 #define _PCIE_CORE_H
  16
  17 /* cpp contortions to concatenate w/arg prescan */
  18 #ifndef PAD
  19 #define _PADLINE(line)  pad ## line
  20 #define _XSTR(line)     _PADLINE(line)
  21 #define PAD             _XSTR(__LINE__)
  22 #endif
  23
  24 /* PCIE Enumeration space offsets */
  25 #define  PCIE_CORE_CONFIG_OFFSET        0x0
  26 #define  PCIE_FUNC0_CONFIG_OFFSET       0x400
  27 #define  PCIE_FUNC1_CONFIG_OFFSET       0x500
  28 #define  PCIE_FUNC2_CONFIG_OFFSET       0x600
  29 #define  PCIE_FUNC3_CONFIG_OFFSET       0x700
  30 #define  PCIE_SPROM_SHADOW_OFFSET       0x800
  31 #define  PCIE_SBCONFIG_OFFSET           0xE00
  32
  33 /* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
  34 #define PCIE_DEV_BAR0_SIZE              0x4000
  35 #define PCIE_BAR0_WINMAPCORE_OFFSET     0x0
  36 #define PCIE_BAR0_EXTSPROM_OFFSET       0x1000
  37 #define PCIE_BAR0_PCIECORE_OFFSET       0x2000
  38 #define PCIE_BAR0_CCCOREREG_OFFSET      0x3000
  39
  40 /* different register spaces to access thr'u pcie indirect access */
  41 #define PCIE_CONFIGREGS         1               /* Access to config space */
  42 #define PCIE_PCIEREGS           2               /* Access to pcie registers */
  43
  44 /* SB side: PCIE core and host control registers */
  45 typedef struct sbpcieregs {
  46         uint32 control;         /* host mode only */
  47         uint32 PAD[2];
  48         uint32 biststatus;      /* bist Status: 0x00C */
  49         uint32 gpiosel;         /* PCIE gpio sel: 0x010 */
  50         uint32 gpioouten;       /* PCIE gpio outen: 0x14 */
  51         uint32 PAD[2];
  52         uint32 intstatus;       /* Interrupt status: 0x20 */
  53         uint32 intmask;         /* Interrupt mask: 0x24 */
  54         uint32 sbtopcimailbox;  /* sb to pcie mailbox: 0x028 */
  55         uint32 PAD[53];
  56         uint32 sbtopcie0;       /* sb to pcie translation 0: 0x100 */
  57         uint32 sbtopcie1;       /* sb to pcie translation 1: 0x104 */
  58         uint32 sbtopcie2;       /* sb to pcie translation 2: 0x108 */
  59         uint32 PAD[5];
  60
  61         /* pcie core supports in direct access to config space */
  62         uint32 configaddr;      /* pcie config space access: Address field: 0x120 */
  63         uint32 configdata;      /* pcie config space access: Data field: 0x124 */
  64
  65         /* mdio access to serdes */
  66         uint32 mdiocontrol;     /* controls the mdio access: 0x128 */
  67         uint32 mdiodata;        /* Data to the mdio access: 0x12c */
  68
  69         /* pcie protocol phy/dllp/tlp register indirect access mechanism */
  70         uint32 pcieindaddr;     /* indirect access to the internal register: 0x130 */
  71         uint32 pcieinddata;     /* Data to/from the internal regsiter: 0x134 */
  72
  73         uint32 clkreqenctrl;    /* >= rev 6, Clkreq rdma control : 0x138 */
  74         uint32 PAD[177];
  75         uint32 pciecfg[4][64];  /* 0x400 - 0x7FF, PCIE Cfg Space */
  76         uint16 sprom[36];       /* SPROM shadow Area */
  77 } sbpcieregs_t;
  78
  79 /* PCI control */
  80 #define PCIE_RST_OE     0x01    /* When set, drives PCI_RESET out to pin */
  81 #define PCIE_RST        0x02    /* Value driven out to pin */
  82
  83 #define PCIE_CFGADDR    0x120   /* offsetof(configaddr) */
  84 #define PCIE_CFGDATA    0x124   /* offsetof(configdata) */
  85
  86 /* Interrupt status/mask */
  87 #define PCIE_INTA       0x01    /* PCIE INTA message is received */
  88 #define PCIE_INTB       0x02    /* PCIE INTB message is received */
  89 #define PCIE_INTFATAL   0x04    /* PCIE INTFATAL message is received */
  90 #define PCIE_INTNFATAL  0x08    /* PCIE INTNONFATAL message is received */
  91 #define PCIE_INTCORR    0x10    /* PCIE INTCORR message is received */
  92 #define PCIE_INTPME     0x20    /* PCIE INTPME message is received */
  93
  94 /* SB to PCIE translation masks */
  95 #define SBTOPCIE0_MASK  0xfc000000
  96 #define SBTOPCIE1_MASK  0xfc000000
  97 #define SBTOPCIE2_MASK  0xc0000000
  98
  99 /* Access type bits (0:1) */
 100 #define SBTOPCIE_MEM    0
 101 #define SBTOPCIE_IO     1
 102 #define SBTOPCIE_CFG0   2
 103 #define SBTOPCIE_CFG1   3
 104
 105 /* Prefetch enable bit 2 */
 106 #define SBTOPCIE_PF             4
 107
 108 /* Write Burst enable for memory write bit 3 */
 109 #define SBTOPCIE_WR_BURST       8
 110
 111 /* config access */
 112 #define CONFIGADDR_FUNC_MASK    0x7000
 113 #define CONFIGADDR_FUNC_SHF     12
 114 #define CONFIGADDR_REG_MASK     0x0FFF
 115 #define CONFIGADDR_REG_SHF      0
 116
 117 #define PCIE_CONFIG_INDADDR(f, r)       ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \
 118                                          (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF))
 119
 120 /* PCIE protocol regs Indirect Address */
 121 #define PCIEADDR_PROT_MASK      0x300
 122 #define PCIEADDR_PROT_SHF       8
 123 #define PCIEADDR_PL_TLP         0
 124 #define PCIEADDR_PL_DLLP        1
 125 #define PCIEADDR_PL_PLP         2
 126
 127 /* PCIE protocol PHY diagnostic registers */
 128 #define PCIE_PLP_MODEREG                0x200 /* Mode */
 129 #define PCIE_PLP_STATUSREG              0x204 /* Status */
 130 #define PCIE_PLP_LTSSMCTRLREG           0x208 /* LTSSM control */
 131 #define PCIE_PLP_LTLINKNUMREG           0x20c /* Link Training Link number */
 132 #define PCIE_PLP_LTLANENUMREG           0x210 /* Link Training Lane number */
 133 #define PCIE_PLP_LTNFTSREG              0x214 /* Link Training N_FTS */
 134 #define PCIE_PLP_ATTNREG                0x218 /* Attention */
 135 #define PCIE_PLP_ATTNMASKREG            0x21C /* Attention Mask */
 136 #define PCIE_PLP_RXERRCTR               0x220 /* Rx Error */
 137 #define PCIE_PLP_RXFRMERRCTR            0x224 /* Rx Framing Error */
 138 #define PCIE_PLP_RXERRTHRESHREG         0x228 /* Rx Error threshold */
 139 #define PCIE_PLP_TESTCTRLREG            0x22C /* Test Control reg */
 140 #define PCIE_PLP_SERDESCTRLOVRDREG      0x230 /* SERDES Control Override */
 141 #define PCIE_PLP_TIMINGOVRDREG          0x234 /* Timing param override */
 142 #define PCIE_PLP_RXTXSMDIAGREG          0x238 /* RXTX State Machine Diag */
 143 #define PCIE_PLP_LTSSMDIAGREG           0x23C /* LTSSM State Machine Diag */
 144
 145 /* PCIE protocol DLLP diagnostic registers */
 146 #define PCIE_DLLP_LCREG                 0x100 /* Link Control */
 147 #define PCIE_DLLP_LSREG                 0x104 /* Link Status */
 148 #define PCIE_DLLP_LAREG                 0x108 /* Link Attention */
 149 #define PCIE_DLLP_LAMASKREG             0x10C /* Link Attention Mask */
 150 #define PCIE_DLLP_NEXTTXSEQNUMREG       0x110 /* Next Tx Seq Num */
 151 #define PCIE_DLLP_ACKEDTXSEQNUMREG      0x114 /* Acked Tx Seq Num */
 152 #define PCIE_DLLP_PURGEDTXSEQNUMREG     0x118 /* Purged Tx Seq Num */
 153 #define PCIE_DLLP_RXSEQNUMREG           0x11C /* Rx Sequence Number */
 154 #define PCIE_DLLP_LRREG                 0x120 /* Link Replay */
 155 #define PCIE_DLLP_LACKTOREG             0x124 /* Link Ack Timeout */
 156 #define PCIE_DLLP_PMTHRESHREG           0x128 /* Power Management Threshold */
 157 #define PCIE_DLLP_RTRYWPREG             0x12C /* Retry buffer write ptr */
 158 #define PCIE_DLLP_RTRYRPREG             0x130 /* Retry buffer Read ptr */
 159 #define PCIE_DLLP_RTRYPPREG             0x134 /* Retry buffer Purged ptr */
 160 #define PCIE_DLLP_RTRRWREG              0x138 /* Retry buffer Read/Write */
 161 #define PCIE_DLLP_ECTHRESHREG           0x13C /* Error Count Threshold */
 162 #define PCIE_DLLP_TLPERRCTRREG          0x140 /* TLP Error Counter */
 163 #define PCIE_DLLP_ERRCTRREG             0x144 /* Error Counter */
 164 #define PCIE_DLLP_NAKRXCTRREG           0x148 /* NAK Received Counter */
 165 #define PCIE_DLLP_TESTREG               0x14C /* Test */
 166 #define PCIE_DLLP_PKTBIST               0x150 /* Packet BIST */
 167 #define PCIE_DLLP_PCIE11                0x154 /* DLLP PCIE 1.1 reg */
 168
 169 #define PCIE_DLLP_LSREG_LINKUP          (1 << 16)
 170
 171 /* PCIE protocol TLP diagnostic registers */
 172 #define PCIE_TLP_CONFIGREG              0x000 /* Configuration */
 173 #define PCIE_TLP_WORKAROUNDSREG         0x004 /* TLP Workarounds */
 174 #define PCIE_TLP_WRDMAUPPER             0x010 /* Write DMA Upper Address */
 175 #define PCIE_TLP_WRDMALOWER             0x014 /* Write DMA Lower Address */
 176 #define PCIE_TLP_WRDMAREQ_LBEREG        0x018 /* Write DMA Len/ByteEn Req */
 177 #define PCIE_TLP_RDDMAUPPER             0x01C /* Read DMA Upper Address */
 178 #define PCIE_TLP_RDDMALOWER             0x020 /* Read DMA Lower Address */
 179 #define PCIE_TLP_RDDMALENREG            0x024 /* Read DMA Len Req */
 180 #define PCIE_TLP_MSIDMAUPPER            0x028 /* MSI DMA Upper Address */
 181 #define PCIE_TLP_MSIDMALOWER            0x02C /* MSI DMA Lower Address */
 182 #define PCIE_TLP_MSIDMALENREG           0x030 /* MSI DMA Len Req */
 183 #define PCIE_TLP_SLVREQLENREG           0x034 /* Slave Request Len */
 184 #define PCIE_TLP_FCINPUTSREQ            0x038 /* Flow Control Inputs */
 185 #define PCIE_TLP_TXSMGRSREQ             0x03C /* Tx StateMachine and Gated Req */
 186 #define PCIE_TLP_ADRACKCNTARBLEN        0x040 /* Address Ack XferCnt and ARB Len */
 187 #define PCIE_TLP_DMACPLHDR0             0x044 /* DMA Completion Hdr 0 */
 188 #define PCIE_TLP_DMACPLHDR1             0x048 /* DMA Completion Hdr 1 */
 189 #define PCIE_TLP_DMACPLHDR2             0x04C /* DMA Completion Hdr 2 */
 190 #define PCIE_TLP_DMACPLMISC0            0x050 /* DMA Completion Misc0 */
 191 #define PCIE_TLP_DMACPLMISC1            0x054 /* DMA Completion Misc1 */
 192 #define PCIE_TLP_DMACPLMISC2            0x058 /* DMA Completion Misc2 */
 193 #define PCIE_TLP_SPTCTRLLEN             0x05C /* Split Controller Req len */
 194 #define PCIE_TLP_SPTCTRLMSIC0           0x060 /* Split Controller Misc 0 */
 195 #define PCIE_TLP_SPTCTRLMSIC1           0x064 /* Split Controller Misc 1 */
 196 #define PCIE_TLP_BUSDEVFUNC             0x068 /* Bus/Device/Func */
 197 #define PCIE_TLP_RESETCTR               0x06C /* Reset Counter */
 198 #define PCIE_TLP_RTRYBUF                0x070 /* Retry Buffer value */
 199 #define PCIE_TLP_TGTDEBUG1              0x074 /* Target Debug Reg1 */
 200 #define PCIE_TLP_TGTDEBUG2              0x078 /* Target Debug Reg2 */
 201 #define PCIE_TLP_TGTDEBUG3              0x07C /* Target Debug Reg3 */
 202 #define PCIE_TLP_TGTDEBUG4              0x080 /* Target Debug Reg4 */
 203
 204 /* MDIO control */
 205 #define MDIOCTL_DIVISOR_MASK            0x7f    /* clock to be used on MDIO */
 206 #define MDIOCTL_DIVISOR_VAL             0x2
 207 #define MDIOCTL_PREAM_EN                0x80    /* Enable preamble sequnce */
 208 #define MDIOCTL_ACCESS_DONE             0x100   /* Tranaction complete */
 209
 210 /* MDIO Data */
 211 #define MDIODATA_MASK                   0x0000ffff      /* data 2 bytes */
 212 #define MDIODATA_TA                     0x00020000      /* Turnaround */
 213 #define MDIODATA_REGADDR_SHF_OLD        18              /* Regaddr shift (rev < 10) */
 214 #define MDIODATA_REGADDR_MASK_OLD       0x003c0000      /* Regaddr Mask (rev < 10) */
 215 #define MDIODATA_DEVADDR_SHF_OLD        22              /* Physmedia devaddr shift (rev < 10) */
 216 #define MDIODATA_DEVADDR_MASK_OLD       0x0fc00000      /* Physmedia devaddr Mask (rev < 10) */
 217 #define MDIODATA_REGADDR_SHF            18              /* Regaddr shift */
 218 #define MDIODATA_REGADDR_MASK           0x007c0000      /* Regaddr Mask */
 219 #define MDIODATA_DEVADDR_SHF            23              /* Physmedia devaddr shift */
 220 #define MDIODATA_DEVADDR_MASK           0x0f800000      /* Physmedia devaddr Mask */
 221 #define MDIODATA_WRITE                  0x10000000      /* write Transaction */
 222 #define MDIODATA_READ                   0x20000000      /* Read Transaction */
 223 #define MDIODATA_START                  0x40000000      /* start of Transaction */
 224
 225 #define MDIODATA_DEV_ADDR               0x0             /* dev address for serdes */
 226 #define MDIODATA_BLK_ADDR               0x1F            /* blk address for serdes */
 227
 228
 229 /* MDIO devices (SERDES modules)
 230  *  unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks.
 231  *  two layers mapping (blockidx, register offset) is required
 232  */
 233 #define MDIO_DEV_IEEE0          0x000
 234 #define MDIO_DEV_IEEE1          0x001
 235 #define MDIO_DEV_BLK0           0x800
 236 #define MDIO_DEV_BLK1           0x801
 237 #define MDIO_DEV_BLK2           0x802
 238 #define MDIO_DEV_BLK3           0x803
 239 #define MDIO_DEV_BLK4           0x804
 240 #define MDIO_DEV_TXPLL          0x808   /* TXPLL register block idx */
 241 #define MDIO_DEV_TXCTRL0        0x820
 242 #define MDIO_DEV_SERDESID       0x831
 243 #define MDIO_DEV_RXCTRL0        0x840
 244
 245 /* serdes regs (rev < 10) */
 246 #define MDIODATA_DEV_PLL                0x1d    /* SERDES PLL Dev */
 247 #define MDIODATA_DEV_TX                 0x1e    /* SERDES TX Dev */
 248 #define MDIODATA_DEV_RX                 0x1f    /* SERDES RX Dev */
 249         /* SERDES RX registers */
 250 #define SERDES_RX_CTRL                  1       /* Rx cntrl */
 251 #define SERDES_RX_TIMER1                2       /* Rx Timer1 */
 252 #define SERDES_RX_CDR                   6       /* CDR */
 253 #define SERDES_RX_CDRBW                 7       /* CDR BW */
 254
 255         /* SERDES RX control register */
 256 #define SERDES_RX_CTRL_FORCE            0x80    /* rxpolarity_force */
 257 #define SERDES_RX_CTRL_POLARITY         0x40    /* rxpolarity_value */
 258
 259         /* SERDES PLL registers */
 260 #define SERDES_PLL_CTRL                 1       /* PLL control reg */
 261 #define PLL_CTRL_FREQDET_EN             0x4000  /* bit 14 is FREQDET on */
 262
 263 /* Power management threshold */
 264 #define PCIE_L0THRESHOLDTIME_MASK       0xFF00  /* bits 0 - 7 */
 265 #define PCIE_L1THRESHOLDTIME_MASK       0xFF00  /* bits 8 - 15 */
 266 #define PCIE_L1THRESHOLDTIME_SHIFT      8       /* PCIE_L1THRESHOLDTIME_SHIFT */
 267 #define PCIE_L1THRESHOLD_WARVAL         0x72    /* WAR value */
 268 #define PCIE_ASPMTIMER_EXTEND           0x01000000      /* > rev7: enable extend ASPM timer */
 269
 270 /* SPROM offsets */
 271 #define SRSH_ASPM_OFFSET                4       /* word 4 */
 272 #define SRSH_ASPM_ENB                   0x18    /* bit 3, 4 */
 273 #define SRSH_ASPM_L1_ENB                0x10    /* bit 4 */
 274 #define SRSH_ASPM_L0s_ENB               0x8     /* bit 3 */
 275 #define SRSH_PCIE_MISC_CONFIG           5       /* word 5 */
 276 #define SRSH_L23READY_EXIT_NOPERST      0x8000  /* bit 15 */
 277 #define SRSH_CLKREQ_OFFSET_REV5         20      /* word 20 for srom rev <= 5 */
 278 #define SRSH_CLKREQ_OFFSET_REV8         52      /* word 52 for srom rev 8 */
 279 #define SRSH_CLKREQ_ENB                 0x0800  /* bit 11 */
 280 #define SRSH_BD_OFFSET                  6       /* word 6 */
 281 #define SRSH_AUTOINIT_OFFSET            18      /* auto initialization enable */
 282
 283 /* Linkcontrol reg offset in PCIE Cap */
 284 #define PCIE_CAP_LINKCTRL_OFFSET        16      /* linkctrl offset in pcie cap */
 285 #define PCIE_CAP_LCREG_ASPML0s          0x01    /* ASPM L0s in linkctrl */
 286 #define PCIE_CAP_LCREG_ASPML1           0x02    /* ASPM L1 in linkctrl */
 287 #define PCIE_CLKREQ_ENAB                0x100   /* CLKREQ Enab in linkctrl */
 288
 289 #define PCIE_ASPM_ENAB                  3       /* ASPM L0s & L1 in linkctrl */
 290 #define PCIE_ASPM_L1_ENAB               2       /* ASPM L0s & L1 in linkctrl */
 291 #define PCIE_ASPM_L0s_ENAB              1       /* ASPM L0s & L1 in linkctrl */
 292 #define PCIE_ASPM_DISAB                 0       /* ASPM L0s & L1 in linkctrl */
 293
 294 /* Status reg PCIE_PLP_STATUSREG */
 295 #define PCIE_PLP_POLARITYINV_STAT       0x10
 296 #endif  /* _PCIE_CORE_H */