2 * pcicfg.h: PCI configuration constants and structures.
4 * Copyright (C) 2009, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: pcicfg.h,v 1.43.2.6 2009/03/11 05:27:38 Exp $
18 #ifndef LINUX_POSTMOGRIFY_REMOVAL
19 /* The following inside ifndef's so we don't collide with NTDDK.H */
21 #define PCI_MAX_BUS 0x100
23 #ifndef PCI_MAX_DEVICES
24 #define PCI_MAX_DEVICES 0x20
26 #ifndef PCI_MAX_FUNCTION
27 #define PCI_MAX_FUNCTION 0x8
30 #ifndef PCI_INVALID_VENDORID
31 #define PCI_INVALID_VENDORID 0xffff
33 #ifndef PCI_INVALID_DEVICEID
34 #define PCI_INVALID_DEVICEID 0xffff
38 /* Convert between bus-slot-function-register and config addresses */
40 #define PCICFG_BUS_SHIFT 16 /* Bus shift */
41 #define PCICFG_SLOT_SHIFT 11 /* Slot shift */
42 #define PCICFG_FUN_SHIFT 8 /* Function shift */
43 #define PCICFG_OFF_SHIFT 0 /* Register shift */
45 #define PCICFG_BUS_MASK 0xff /* Bus mask */
46 #define PCICFG_SLOT_MASK 0x1f /* Slot mask */
47 #define PCICFG_FUN_MASK 7 /* Function mask */
48 #define PCICFG_OFF_MASK 0xff /* Bus mask */
50 #define PCI_CONFIG_ADDR(b, s, f, o) \
51 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
52 | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
53 | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
54 | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
56 #define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
57 #define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
58 #define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
59 #define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
61 /* PCIE Config space accessing MACROS */
63 #define PCIECFG_BUS_SHIFT 24 /* Bus shift */
64 #define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
65 #define PCIECFG_FUN_SHIFT 16 /* Function shift */
66 #define PCIECFG_OFF_SHIFT 0 /* Register shift */
68 #define PCIECFG_BUS_MASK 0xff /* Bus mask */
69 #define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
70 #define PCIECFG_FUN_MASK 7 /* Function mask */
71 #define PCIECFG_OFF_MASK 0xfff /* Register mask */
73 #define PCIE_CONFIG_ADDR(b, s, f, o) \
74 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
75 | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
76 | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
77 | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
79 #define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
80 #define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
81 #define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
82 #define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
84 /* The actual config space */
90 #define PCR_RSVDA_MAX 2
92 /* Bits in PCI bars' flags */
94 #define PCIBAR_FLAGS 0xf
96 #define PCIBAR_MEM1M 0x2
97 #define PCIBAR_MEM64 0x4
98 #define PCIBAR_PREFETCH 0x8
99 #define PCIBAR_MEM32_MASK 0xFFFFFF80
101 /* pci config status reg has a bit to indicate that capability ptr is present */
103 #define PCI_CAPPTR_PRESENT 0x0010
105 typedef struct _pci_config_regs
{
106 unsigned short vendor
;
107 unsigned short device
;
108 unsigned short command
;
109 unsigned short status
;
110 unsigned char rev_id
;
111 unsigned char prog_if
;
112 unsigned char sub_class
;
113 unsigned char base_class
;
114 unsigned char cache_line_size
;
115 unsigned char latency_timer
;
116 unsigned char header_type
;
118 unsigned long base
[PCI_BAR_MAX
];
119 unsigned long cardbus_cis
;
120 unsigned short subsys_vendor
;
121 unsigned short subsys_id
;
122 unsigned long baserom
;
123 unsigned long rsvd_a
[PCR_RSVDA_MAX
];
124 unsigned char int_line
;
125 unsigned char int_pin
;
126 unsigned char min_gnt
;
127 unsigned char max_lat
;
128 unsigned char dev_dep
[192];
131 #define SZPCR (sizeof (pci_config_regs))
132 #define MINSZPCR 64 /* offsetof (dev_dep[0] */
134 /* A structure for the config registers is nice, but in most
135 * systems the config space is not memory mapped, so we need
136 * field offsetts. :-(
138 #define PCI_CFG_VID 0
139 #define PCI_CFG_DID 2
140 #define PCI_CFG_CMD 4
141 #define PCI_CFG_STAT 6
142 #define PCI_CFG_REV 8
143 #define PCI_CFG_PROGIF 9
144 #define PCI_CFG_SUBCL 0xa
145 #define PCI_CFG_BASECL 0xb
146 #define PCI_CFG_CLSZ 0xc
147 #define PCI_CFG_LATTIM 0xd
148 #define PCI_CFG_HDR 0xe
149 #define PCI_CFG_BIST 0xf
150 #define PCI_CFG_BAR0 0x10
151 #define PCI_CFG_BAR1 0x14
152 #define PCI_CFG_BAR2 0x18
153 #define PCI_CFG_BAR3 0x1c
154 #define PCI_CFG_BAR4 0x20
155 #define PCI_CFG_BAR5 0x24
156 #define PCI_CFG_CIS 0x28
157 #define PCI_CFG_SVID 0x2c
158 #define PCI_CFG_SSID 0x2e
159 #define PCI_CFG_ROMBAR 0x30
160 #define PCI_CFG_CAPPTR 0x34
161 #define PCI_CFG_INT 0x3c
162 #define PCI_CFG_PIN 0x3d
163 #define PCI_CFG_MINGNT 0x3e
164 #define PCI_CFG_MAXLAT 0x3f
167 #undef PCI_CLASS_DISPLAY
168 #undef PCI_CLASS_MEMORY
169 #undef PCI_CLASS_BRIDGE
170 #undef PCI_CLASS_INPUT
171 #undef PCI_CLASS_DOCK
172 #endif /* __NetBSD__ */
175 #undef PCI_CLASS_BRIDGE
177 #undef PCI_CLASS_DISPLAY
178 #undef PCI_CLASS_SERIAL
179 #undef PCI_CLASS_SATELLITE
182 /* Classes and subclasses */
198 PCI_CLASS_INTELLIGENT
= 0xe,
211 PCI_DASDI_OTHER
= 0x80
212 } pci_dasdi_subclasses
;
220 } pci_net_subclasses
;
226 PCI_DISPLAY_OTHER
= 0x80
227 } pci_display_subclasses
;
233 PCI_MEDIA_OTHER
= 0x80
234 } pci_mmedia_subclasses
;
239 PCI_MEMORY_OTHER
= 0x80
240 } pci_memory_subclasses
;
252 PCI_BRIDGE_OTHER
= 0x80
253 } pci_bridge_subclasses
;
260 PCI_COMM_OTHER
= 0x80
261 } pci_comm_subclasses
;
268 PCI_BASE_PCI_HOTPLUG
,
269 PCI_BASE_OTHER
= 0x80
270 } pci_base_subclasses
;
278 PCI_INPUT_OTHER
= 0x80
279 } pci_input_subclasses
;
283 PCI_DOCK_OTHER
= 0x80
284 } pci_dock_subclasses
;
290 PCI_CPU_ALPHA
= 0x10,
291 PCI_CPU_POWERPC
= 0x20,
293 PCI_CPU_COPROC
= 0x40,
295 } pci_cpu_subclasses
;
304 PCI_SERIAL_OTHER
= 0x80
305 } pci_serial_subclasses
;
309 } pci_intelligent_subclasses
;
316 PCI_SATELLITE_OTHER
= 0x80
317 } pci_satellite_subclasses
;
321 PCI_CRYPT_ENTERTAINMENT
,
322 PCI_CRYPT_OTHER
= 0x80
323 } pci_crypt_subclasses
;
328 } pci_dsp_subclasses
;
333 } pci_xor_subclasses
;
336 #define PCI_HEADER_MULTI 0x80
337 #define PCI_HEADER_MASK 0x7f
345 /* Overlay for a PCI-to-PCI bridge */
347 #define PPB_RSVDA_MAX 2
348 #define PPB_RSVDD_MAX 8
350 typedef struct _ppb_config_regs
{
351 unsigned short vendor
;
352 unsigned short device
;
353 unsigned short command
;
354 unsigned short status
;
355 unsigned char rev_id
;
356 unsigned char prog_if
;
357 unsigned char sub_class
;
358 unsigned char base_class
;
359 unsigned char cache_line_size
;
360 unsigned char latency_timer
;
361 unsigned char header_type
;
363 unsigned long rsvd_a
[PPB_RSVDA_MAX
];
364 unsigned char prim_bus
;
365 unsigned char sec_bus
;
366 unsigned char sub_bus
;
367 unsigned char sec_lat
;
368 unsigned char io_base
;
369 unsigned char io_lim
;
370 unsigned short sec_status
;
371 unsigned short mem_base
;
372 unsigned short mem_lim
;
373 unsigned short pf_mem_base
;
374 unsigned short pf_mem_lim
;
375 unsigned long pf_mem_base_hi
;
376 unsigned long pf_mem_lim_hi
;
377 unsigned short io_base_hi
;
378 unsigned short io_lim_hi
;
379 unsigned short subsys_vendor
;
380 unsigned short subsys_id
;
381 unsigned long rsvd_b
;
382 unsigned char rsvd_c
;
383 unsigned char int_pin
;
384 unsigned short bridge_ctrl
;
385 unsigned char chip_ctrl
;
386 unsigned char diag_ctrl
;
387 unsigned short arb_ctrl
;
388 unsigned long rsvd_d
[PPB_RSVDD_MAX
];
389 unsigned char dev_dep
[192];
393 /* PCI CAPABILITY DEFINES */
394 #define PCI_CAP_POWERMGMTCAP_ID 0x01
395 #define PCI_CAP_MSICAP_ID 0x05
396 #define PCI_CAP_VENDSPEC_ID 0x09
397 #define PCI_CAP_PCIECAP_ID 0x10
399 /* Data structure to define the Message Signalled Interrupt facility
400 * Valid for PCI and PCIE configurations
402 typedef struct _pciconfig_cap_msi
{
404 unsigned char nextptr
;
405 unsigned short msgctrl
;
406 unsigned int msgaddr
;
409 /* Data structure to define the Power managment facility
410 * Valid for PCI and PCIE configurations
412 typedef struct _pciconfig_cap_pwrmgmt
{
414 unsigned char nextptr
;
415 unsigned short pme_cap
;
416 unsigned short pme_sts_ctrl
;
417 unsigned char pme_bridge_ext
;
419 } pciconfig_cap_pwrmgmt
;
421 #define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
422 #define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
423 #define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
424 #define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
426 /* Data structure to define the PCIE capability */
427 typedef struct _pciconfig_cap_pcie
{
429 unsigned char nextptr
;
430 unsigned short pcie_cap
;
431 unsigned int dev_cap
;
432 unsigned short dev_ctrl
;
433 unsigned short dev_status
;
434 unsigned int link_cap
;
435 unsigned short link_ctrl
;
436 unsigned short link_status
;
437 unsigned int slot_cap
;
438 unsigned short slot_ctrl
;
439 unsigned short slot_status
;
440 unsigned short root_ctrl
;
441 unsigned short root_cap
;
442 unsigned int root_status
;
443 } pciconfig_cap_pcie
;
445 /* PCIE Enhanced CAPABILITY DEFINES */
446 #define PCIE_EXTCFG_OFFSET 0x100
447 #define PCIE_ADVERRREP_CAPID 0x0001
448 #define PCIE_VC_CAPID 0x0002
449 #define PCIE_DEVSNUM_CAPID 0x0003
450 #define PCIE_PWRBUDGET_CAPID 0x0004
452 /* PCIE Root Control Register bits (Host mode only) */
453 #define PCIE_RC_CORR_SERR_EN 0x0001
454 #define PCIE_RC_NONFATAL_SERR_EN 0x0002
455 #define PCIE_RC_FATAL_SERR_EN 0x0004
456 #define PCIE_RC_PME_INT_EN 0x0008
457 #define PCIE_RC_CRS_EN 0x0010
459 /* PCIE Root Capability Register bits (Host mode only) */
460 #define PCIE_RC_CRS_VISIBILITY 0x0001
462 /* Header to define the PCIE specific capabilities in the extended config space */
463 typedef struct _pcie_enhanced_caphdr
{
464 unsigned short capID
;
465 unsigned short cap_ver
: 4;
466 unsigned short next_ptr
: 12;
467 } pcie_enhanced_caphdr
;
470 /* Everything below is BRCM HND proprietary */
473 /* Brcm PCI configuration registers */
474 #define cap_list rsvd_a[0]
475 #define bar0_window dev_dep[0x80 - 0x40]
476 #define bar1_window dev_dep[0x84 - 0x40]
477 #define sprom_control dev_dep[0x88 - 0x40]
478 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
479 #define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
480 #ifndef LINUX_POSTMOGRIFY_REMOVAL
481 #define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
482 #define PCI_SPROM_CONTROL 0x88 /* sprom property control */
483 #define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
484 #define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
485 #define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
486 #define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
487 #define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
488 #define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
489 #define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
490 #define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
491 #define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
492 #define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
493 #define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
495 #define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
496 #define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
497 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
498 #define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
499 * 8KB window, so their address is the "regular"
502 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
503 #define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
504 #ifndef LINUX_POSTMOGRIFY_REMOVAL
505 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
506 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
507 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
508 #define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
511 #define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
514 #define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
515 #define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
516 #define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
518 /* PCI_SPROM_CONTROL */
519 #define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
520 #define SPROM_LOCKED 0x08 /* SPROM Locked */
521 #define SPROM_BLANK 0x04 /* indicating a blank SPROM */
522 #define SPROM_WRITEEN 0x10 /* SPROM write enable */
523 #define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
524 #define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
525 #define SPROM_OTPIN_USE 0x80 /* device OTP In use */
527 /* Bits in PCI command and status regs */
528 #define PCI_CMD_IO 0x00000001 /* I/O enable */
529 #define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
530 #define PCI_CMD_MASTER 0x00000004 /* Master enable */
531 #define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
532 #define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
533 #define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
534 #define PCI_STAT_TA 0x08000000 /* target abort status */
535 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
536 #endif /* _h_pcicfg_ */