2 * Broadcom SiliconBackplane MIPS definitions
4 * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
5 * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
6 * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
7 * interface. The core revision is stored in the SB ID register in SB
10 * Copyright (C) 2009, Broadcom Corporation
11 * All Rights Reserved.
13 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18 * $Id: mips33_core.h,v 13.3 2008/03/25 22:43:52 Exp $
21 #ifndef _mips33_core_h_
22 #define _mips33_core_h_
26 #ifndef _LANGUAGE_ASSEMBLY
28 /* cpp contortions to concatenate w/arg prescan */
30 #define _PADLINE(line) pad ## line
31 #define _XSTR(line) _PADLINE(line)
32 #define PAD _XSTR(__LINE__)
35 typedef volatile struct {
45 #endif /* _LANGUAGE_ASSEMBLY */
47 #endif /* _mips33_core_h_ */