2 * Broadcom HND chip & on-chip-interconnect-related definitions.
4 * Copyright (C) 2009, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: hndsoc.h,v 13.3.2.5 2009/06/18 12:19:28 Exp $
18 /* Include the soci specific files */
23 * SOC Interconnect Address Map.
24 * All regions may not exist on all chips.
26 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
27 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
28 #define SI_PCI_MEM_SZ (64 * 1024 * 1024)
29 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
30 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
31 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
33 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
34 #define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
35 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
36 #define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software
37 * convenience and could be changed if we
38 * make any larger chips
41 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
42 #define SI_FASTRAM_SWAPPED 0x19800000
44 #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
45 #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
46 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
47 #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
48 #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
49 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
50 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
51 #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
52 #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
53 #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
55 #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
56 #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
57 #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
58 #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
59 * (2 ZettaBytes), low 32 bits
61 #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
62 * (2 ZettaBytes), high 32 bits
66 #define NODEV_CORE_ID 0x700 /* Invalid coreid */
67 #define CC_CORE_ID 0x800 /* chipcommon core */
68 #define ILINE20_CORE_ID 0x801 /* iline20 core */
69 #define SRAM_CORE_ID 0x802 /* sram core */
70 #define SDRAM_CORE_ID 0x803 /* sdram core */
71 #define PCI_CORE_ID 0x804 /* pci core */
72 #define MIPS_CORE_ID 0x805 /* mips core */
73 #define ENET_CORE_ID 0x806 /* enet mac core */
74 #define CODEC_CORE_ID 0x807 /* v90 codec core */
75 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
76 #define ADSL_CORE_ID 0x809 /* ADSL core */
77 #define ILINE100_CORE_ID 0x80a /* iline100 core */
78 #define IPSEC_CORE_ID 0x80b /* ipsec core */
79 #define UTOPIA_CORE_ID 0x80c /* utopia core */
80 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */
81 #define SOCRAM_CORE_ID 0x80e /* internal memory core */
82 #define MEMC_CORE_ID 0x80f /* memc sdram core */
83 #define OFDM_CORE_ID 0x810 /* OFDM phy core */
84 #define EXTIF_CORE_ID 0x811 /* external interface core */
85 #define D11_CORE_ID 0x812 /* 802.11 MAC core */
86 #define APHY_CORE_ID 0x813 /* 802.11a phy core */
87 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */
88 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */
89 #define MIPS33_CORE_ID 0x816 /* mips3302 core */
90 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
91 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
92 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
93 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
94 #define SDIOH_CORE_ID 0x81b /* sdio host core */
95 #define ROBO_CORE_ID 0x81c /* roboswitch core */
96 #define ATA100_CORE_ID 0x81d /* parallel ATA core */
97 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
98 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
99 #define PCIE_CORE_ID 0x820 /* pci express core */
100 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
101 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */
102 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
103 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */
104 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
105 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
106 #define PMU_CORE_ID 0x827 /* PMU core */
107 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
108 #define SDIOD_CORE_ID 0x829 /* SDIO device core */
109 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
110 #define QNPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
111 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */
112 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
113 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
114 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
115 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
116 #define SC_CORE_ID 0x831 /* shared common core */
117 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
118 #define SPIH_CORE_ID 0x833 /* SPI host core */
119 #define I2S_CORE_ID 0x834 /* I2S core */
120 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
121 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
122 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
123 * unused address ranges
126 /* There are TWO constants on all HND chips: SI_ENUM_BASE above,
127 * and chipcommon being the first core:
131 /* SOC Interconnect types (aka chip types) */
135 /* Common core control flags */
136 #define SICF_BIST_EN 0x8000
137 #define SICF_PME_EN 0x4000
138 #define SICF_CORE_BITS 0x3ffc
139 #define SICF_FGC 0x0002
140 #define SICF_CLOCK_EN 0x0001
142 /* Common core status flags */
143 #define SISF_BIST_DONE 0x8000
144 #define SISF_BIST_ERROR 0x4000
145 #define SISF_GATED_CLK 0x2000
146 #define SISF_DMA64 0x1000
147 #define SISF_CORE_BITS 0x0fff
149 /* A register that is common to all cores to
150 * communicate w/PMU regarding clock control.
152 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
154 /* clk_ctl_st register */
155 #define CCS_FORCEALP 0x00000001 /* force ALP request */
156 #define CCS_FORCEHT 0x00000002 /* force HT request */
157 #define CCS_FORCEILP 0x00000004 /* force ILP request */
158 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
159 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */
160 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
161 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
162 #define CCS_ERSRC_REQ_SHIFT 8
163 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */
164 #define CCS_HTAVAIL 0x00020000 /* HT is available */
165 #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */
166 #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */
167 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
168 #define CCS_ERSRC_STS_SHIFT 24
170 #define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
171 #define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
173 /* Not really related to SOC Interconnect, but a couple of software
174 * conventions for the use the flash space:
177 /* Minumum amount of flash we support */
178 #define FLASH_MIN 0x00020000 /* Minimum flash size */
180 /* A boot/binary may have an embedded block that describes its size */
181 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
182 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
183 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */
184 #define BISZ_TXTST_IDX 1 /* 1: text start */
185 #define BISZ_TXTEND_IDX 2 /* 2: text end */
186 #define BISZ_DATAST_IDX 3 /* 3: data start */
187 #define BISZ_DATAEND_IDX 4 /* 4: data end */
188 #define BISZ_BSSST_IDX 5 /* 5: bss start */
189 #define BISZ_BSSEND_IDX 6 /* 6: bss end */
190 #define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
192 #endif /* _HNDSOC_H */
