release/src-rt/include/hndjtagdefs.h

   1 /*
   2  * Definitiosn for Jtag taps in HND chips.
   3  *
   4  * $Id: hndjtagdefs.h,v 13.1 2008/11/13 22:33:43 Exp $
   5  *
   6  * Copyright (C) 2009, Broadcom Corporation
   7  * All Rights Reserved.
   8  *
   9  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  10  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  11  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  12  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  13  */
  14
  15 #ifndef _HNDJTAGDEFS_H
  16 #define _HNDJTAGDEFS_H
  17
  18 /* Jtag access regs are all 32 bits */
  19 #define JRBITS                  32
  20
  21 /* MIPS mode defines: */
  22
  23 #define MIPS_IR_SIZE            5
  24 #define MIPS_DR_SIZE            32
  25
  26 #define MIPS_IDCODE             1
  27 #define MIPS_BYPASS             0x1f
  28
  29 /* Register addresses */
  30 #define MIPS_ADDR               0x08
  31 #define MIPS_DATA               0x09
  32 #define MIPS_CTRL               0x0a
  33
  34 /* DMA related bits in the Control register */
  35 #define DMA_SZ1                 0x00000000
  36 #define DMA_SZ2                 0x00000080
  37 #define DMA_SZ4                 0x00000100
  38 #define DMA_SZ3                 0x00000180
  39 #define DMA_READ                0x00000200
  40 #define DMA_ERROR               0x00000400
  41 #define DMA_START               0x00000800
  42 #define DMA_BREAK               0x00001000
  43 #define DMA_ACC                 0x00020000
  44
  45 /* CC mode defines: */
  46
  47 #define CCJT_IR_SIZE            8
  48 #define CCJT_DR_SIZE            32
  49
  50 #define CCJT_USER_BASE          0x20
  51
  52 #define CCJT_IDCODE             1
  53 #define CCJT_BYPASS             0xff
  54
  55 /* Register addresses */
  56 #define CHIPC_ADDR              0x30
  57 #define CHIPC_DATA              0x32
  58 #define CHIPC_CTRL              0x34
  59
  60 #define CHIPC_RO                1               /* Or in this to get the read-only address */
  61
  62 /* Control register bits */
  63 #define CCC_BE0                 0x00000001
  64 #define CCC_BE1                 0x00000002
  65 #define CCC_BE2                 0x00000004
  66 #define CCC_BE3                 0x00000008
  67 #define CCC_SZ1                 (CCC_BE0)
  68 #define CCC_SZ2                 (CCC_BE1 | CCC_BE0)
  69 #define CCC_SZ4                 (CCC_BE3 | CCC_BE2 | CCC_BE1 | CCC_BE0)
  70 #define CCC_READ                0x00000010
  71 #define CCC_START               0x00000020
  72 #define CCC_ERROR               0x00000040
  73
  74 /* Bits written into the control register need to be shifted */
  75 #define CCC_WR_SHIFT            25
  76
  77 /* LV mode defines: */
  78
  79 #define LV_IR_SIZE              32
  80 #define LV_DR_SIZE              32
  81
  82 #define LV_BASE                 0x0003ff3a
  83 #define LV_REG_MASK             0x01f00000
  84 #define LV_REG_SHIFT            20
  85 #define LV_RO                   0x00080000
  86 #define LV_USER_BASE            0x10
  87
  88 /* Register addresses */
  89 #define LV_CAP                  0
  90 #define LV_CHAIN_CTL            1
  91 #define LV_ADDR                 2
  92 #define LV_ADDRH                3
  93 #define LV_DATA                 4
  94 #define LV_CTRL                 5
  95 #define LV_OTP_CTL              6
  96 #define LV_OTP_STAT             7
  97
  98 #define LV_REG_IR(reg)          (LV_BASE | (((reg) << LV_REG_SHIFT) & LV_REG_MASK))
  99 #define LV_REG_ROIR(reg)        (LV_BASE | LV_RO | (((reg) << LV_REG_SHIFT) & LV_REG_MASK))
 100 #define LV_UREG_IR(reg)         (LV_BASE | ((((reg) + LV_USER_BASE) << LV_REG_SHIFT) & LV_REG_MASK))
 101 #define LV_UREG_ROIR(reg)       \
 102         (LV_BASE | LV_RO | ((((reg) + LV_USER_BASE) << LV_REG_SHIFT) & LV_REG_MASK))
 103
 104 #define LV_IDCODE               0xfffffffe
 105 #define LV_BYPASS               0xffffffff
 106
 107 #define IDC_MFG_MASK            0x00000fff
 108 #define IDC_PART_MASK           0x0ffff000
 109 #define IDC_PART_SHIFT          12
 110 #define IDC_REV_MASK            0xf0000000
 111 #define IDC_REV_SHIFT           28
 112
 113 #define JEDEC_BRCM              0x17f
 114
 115 #endif  /* _HNDJTAGDEFS_H */