release/src-rt/include/dmemc_core.h

   1 /*
   2  * BCM47XX Denali DDR1/DDR2 and SDR/DDR1 memory controlers.
   3  *
   4  * Copyright (C) 2009, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: dmemc_core.h,v 13.1.4.3 2008/10/31 21:26:25 Exp $
  13  */
  14
  15 #ifndef _DMEMC_H
  16 #define _DMEMC_H
  17
  18 #ifndef PAD
  19 #define _PADLINE(line)  pad ## line
  20 #define _XSTR(line)     _PADLINE(line)
  21 #define PAD             _XSTR(__LINE__)
  22 #endif  /* PAD */
  23
  24 #ifdef _LANGUAGE_ASSEMBLY
  25
  26 #define DMEMC_CONTROL00         0x000
  27 #define DMEMC_CONTROL01         0x004
  28 #define DMEMC_CONTROL02         0x008
  29 #define DMEMC_CONTROL03         0x00c
  30 #define DMEMC_CONTROL04         0x010
  31 #define DMEMC_CONTROL05         0x014
  32 #define DMEMC_CONTROL06         0x018
  33 #define DMEMC_CONTROL07         0x01c
  34 #define DMEMC_CONTROL08         0x020
  35 #define DMEMC_CONTROL09         0x024
  36 #define DMEMC_CONTROL10         0x028
  37 #define DMEMC_CONTROL11         0x02c
  38 #define DMEMC_CONTROL12         0x030
  39 #define DMEMC_CONTROL13         0x034
  40 #define DMEMC_CONTROL14         0x038
  41 #define DMEMC_CONTROL15         0x03c
  42 #define DMEMC_CONTROL16         0x040
  43 #define DMEMC_CONTROL17         0x044
  44 #define DMEMC_CONTROL18         0x048
  45 #define DMEMC_CONTROL19         0x04c
  46 #define DMEMC_CONTROL20         0x050
  47 #define DMEMC_CONTROL21         0x054
  48 #define DMEMC_CONTROL22         0x058
  49 #define DMEMC_CONTROL23         0x05c
  50 #define DMEMC_CONTROL24         0x060
  51 #define DMEMC_CONTROL25         0x064
  52 #define DMEMC_CONTROL26         0x068
  53 #define DMEMC_CONTROL27         0x06c
  54 #define DMEMC_CONTROL28         0x070
  55 #define DMEMC_CONTROL29         0x074
  56 #define DMEMC_CONTROL30         0x078
  57 #define DMEMC_CONTROL31         0x07c
  58 #define DMEMC_CONTROL32         0x080
  59 #define DMEMC_CONTROL33         0x084
  60 #define DMEMC_CONTROL34         0x088
  61 #define DMEMC_CONTROL35         0x08c
  62 #define DMEMC_CONTROL36         0x090
  63 #define DMEMC_CONTROL37         0x094
  64 #define DMEMC_CONTROL38         0x098
  65 #define DMEMC_CONTROL39         0x09c
  66 #define DMEMC_CONTROL40         0x0a0
  67 #define DMEMC_CONTROL41         0x0a4
  68 #define DMEMC_CONTROL42         0x0a8
  69 #define DMEMC_CONTROL43         0x0ac
  70 #define DMEMC_CONTROL44         0x0b0
  71 #define DMEMC_CONTROL45         0x0b4
  72 #define DMEMC_CONTROL46         0x0b8
  73 #define DMEMC_CONTROL47         0x0bc
  74 #define DMEMC_CONTROL48         0x0c0
  75 #define DMEMC_CONTROL49         0x0c4
  76 #define DMEMC_CONTROL50         0x0c8
  77 #define DMEMC_CONTROL51         0x0cc
  78 #define DMEMC_CONTROL52         0x0d0
  79 #define DMEMC_CONTROL53         0x0d4
  80
  81 #define DMEMC_CLK_CTL_ST        0x1e0
  82 #define DMEMC_DDR_CTRL          0x1e4
  83 #define DMEMC_STAT              0x1f0
  84
  85 #define DMEMC_PVTGROUPA         0x400
  86 #define DMEMC_PVTGROUPB         0x404
  87 #define DMEMC_PVTGROUPC         0x408
  88 #define DMEMC_PVTGROUPE         0x40c
  89 #define DMEMC_PVTGROUPF         0x410
  90 #define DMEMC_PVTGROUPG         0x414
  91 #define DMEMC_PVTGROUPH         0x418
  92 #define DMEMC_PVTGROUPI         0x41c
  93 #define DMEMC_PVTGROUPJ         0x420
  94
  95 #define DMEMC_GPIOSEL           0x800
  96 #define DMEMC_GPIOOUTEN 0x804
  97
  98 #else   /* !_LANGUAGE_ASSEMBLY */
  99
 100 #define DMEMC_MAXREG            50
 101 #define DMEMC_PVTREGS           9
 102
 103 /* DMEMC core registers */
 104 typedef volatile struct dmemcregs {
 105         uint32  control[DMEMC_MAXREG];
 106         uint32  PAD[205];
 107         uint32  pvtgroup[DMEMC_PVTREGS];        /* 0x400 */
 108         uint32  PAD[247];
 109         uint32  gpiosel;                        /* 0x800 */
 110         uint32  gpioouten;                      /* 0x804 */
 111 } dmemcregs_t;
 112
 113
 114 #define DMEMS_MAXREG            53
 115
 116 /* DMEMC core registers */
 117 typedef volatile struct dmemsregs {
 118         uint32  control[DMEMS_MAXREG];
 119         uint32  PAD[66];
 120         uint32  clk_ctl_st;                     /* 0x1e0 */
 121         uint32  ddr_ctrl;                       /* 0x1e4 */
 122         uint32  PAD[2];
 123         uint32  stat;                           /* 0x1f0 */
 124         uint32  PAD[386];
 125         uint32  gpiosel;                        /* 0x800 */
 126         uint32  gpioouten;                      /* 0x804 */
 127 } dmemsregs_t;
 128
 129 #endif  /* _LANGUAGE_ASSEMBLY */
 130
 131 #define DMEMC_TABLE_END         0xffffffff
 132
 133 /* Bits in control3 */
 134 #define DMC03_BIST_DATA         0x01000000
 135 #define DMC03_BIST_ADDR         0x00010000
 136
 137 /* Bits in control4 */
 138 #define DMC04_DLLLOCK           0x01000000
 139 #define DMC04_DDR2              0x00010000
 140 #define DMC04_BIST_GO           0x00000001
 141
 142 /* Bits in control09 */
 143 #define DMC09_START             0x01000000
 144
 145 /* Bits in control11 */
 146 #define DMC11_BIST_DATA_OK      0x01000000
 147 #define DMC11_BIST_ADDR_OK      0x02000000
 148
 149 /* Bits in control19 */
 150 #define DMC19_ADDRSP_MASK       0x1f000000
 151 #define DMC19_ADDRSP_SHIFT      24
 152
 153 /* Bits in control23 */
 154 #define DMC23_INTMASK_MASK      0xff000000
 155 #define DMC23_INTMASK_SHIFT     24
 156 #define DMC23_INTACK_MASK       0x0000007f
 157
 158 /* Bits in control24 */
 159 #define DMC24_INTSTAT_MASK      0x000000ff
 160
 161 /* Interrupt bits (in control24.status, control23.int_ack and
 162  * control23.int_mask)
 163  */
 164 #define DM_INT_SINGLE_BAD       0x01
 165 #define DM_INT_MULTI_BAD        0x02
 166 #define DM_INT_CMD_ERR          0x04
 167 #define DM_INT_DATA_ERR         0x08
 168 #define DM_INT_INIT_DONE        0x10
 169 #define DM_INT_BIST_DONE        0x20
 170 #define DM_INT_DLL_UNLOCK       0x40
 171 #define DM_INT_ANY              0x80
 172
 173 /* Stat bits */
 174 #define DM_STAT_DDR2_CAP        0x0400
 175 #define DM_STAT_DDR1_CAP        0x0200
 176 #define DM_STAT_SDR_CAP         0x0100
 177 #define DM_STAT_DDR2            0x0004
 178 #define DM_STAT_DDR1            0x0002
 179 #define DM_STAT_SDR             0x0001
 180 #define DM_STAT_MASK            0x0007
 181
 182 #endif  /* _SBMEMC_H */