release/src-rt/include/bcmdevs.h

   1 /*
   2  * Broadcom device-specific manifest constants.
   3  *
   4  * Copyright (C) 2009, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  * $Id: bcmdevs.h,v 13.182.2.40 2010/01/28 03:48:46 Exp $
  13  */
  14
  15 #ifndef _BCMDEVS_H
  16 #define _BCMDEVS_H
  17
  18 /* PCI vendor ID's */
  19 #define VENDOR_EPIGRAM          0xfeda
  20 #define VENDOR_BROADCOM         0x14e4
  21 #define VENDOR_3COM             0x10b7
  22 #define VENDOR_NETGEAR          0x1385
  23 #define VENDOR_DIAMOND          0x1092
  24 #define VENDOR_INTEL            0x8086
  25 #define VENDOR_DELL             0x1028
  26 #define VENDOR_HP               0x103c
  27 #define VENDOR_HP_COMPAQ        0x0e11
  28 #define VENDOR_APPLE            0x106b
  29 #define VENDOR_SI_IMAGE         0x1095          /* Silicon Image, used by Arasan SDIO Host */
  30 #define VENDOR_BUFFALO          0x1154          /* Buffalo vendor id */
  31 #define VENDOR_TI               0x104c          /* Texas Instruments */
  32 #define VENDOR_RICOH            0x1180          /* Ricoh */
  33
  34 /* PCMCIA vendor ID's */
  35 #define VENDOR_BROADCOM_PCMCIA  0x02d0
  36
  37 /* SDIO vendor ID's */
  38 #define VENDOR_BROADCOM_SDIO    0x00BF
  39
  40 /* DONGLE VID/PIDs */
  41 #define BCM_DNGL_VID            0xa5c
  42 #define BCM_DNGL_BL_PID_4328    0xbd12
  43 #define BCM_DNGL_BL_PID_4322    0xbd13
  44 #define BCM_DNGL_BDC_PID        0xbdc
  45 #define BCM_DNGL_BL_PID_4319    0xbd16
  46
  47 /* PCI Device ID's */
  48 #define BCM4210_DEVICE_ID       0x1072          /* never used */
  49 #define BCM4230_DEVICE_ID       0x1086          /* never used */
  50 #define BCM4401_ENET_ID         0x170c          /* 4401b0 production enet cards */
  51 #define BCM3352_DEVICE_ID       0x3352          /* bcm3352 device id */
  52 #define BCM3360_DEVICE_ID       0x3360          /* bcm3360 device id */
  53 #define BCM4211_DEVICE_ID       0x4211
  54 #define BCM4231_DEVICE_ID       0x4231
  55 #define BCM4303_D11B_ID         0x4303          /* 4303 802.11b */
  56 #define BCM4311_D11G_ID         0x4311          /* 4311 802.11b/g id */
  57 #define BCM4311_D11DUAL_ID      0x4312          /* 4311 802.11a/b/g id */
  58 #define BCM4311_D11A_ID         0x4313          /* 4311 802.11a id */
  59 #define BCM4328_D11DUAL_ID      0x4314          /* 4328/4312 802.11a/g id */
  60 #define BCM4328_D11G_ID         0x4315          /* 4328/4312 802.11g id */
  61 #define BCM4328_D11A_ID         0x4316          /* 4328/4312 802.11a id */
  62 #define BCM4318_D11G_ID         0x4318          /* 4318 802.11b/g id */
  63 #define BCM4318_D11DUAL_ID      0x4319          /* 4318 802.11a/b/g id */
  64 #define BCM4318_D11A_ID         0x431a          /* 4318 802.11a id */
  65 #define BCM4325_D11DUAL_ID      0x431b          /* 4325 802.11a/g id */
  66 #define BCM4325_D11G_ID         0x431c          /* 4325 802.11g id */
  67 #define BCM4325_D11A_ID         0x431d          /* 4325 802.11a id */
  68 #define BCM4306_D11G_ID         0x4320          /* 4306 802.11g */
  69 #define BCM4306_D11A_ID         0x4321          /* 4306 802.11a */
  70 #define BCM4306_UART_ID         0x4322          /* 4306 uart */
  71 #define BCM4306_V90_ID          0x4323          /* 4306 v90 codec */
  72 #define BCM4306_D11DUAL_ID      0x4324          /* 4306 dual A+B */
  73 #define BCM4306_D11G_ID2        0x4325          /* BCM4306_D11G_ID; INF w/loose binding war */
  74 #define BCM4321_D11N_ID         0x4328          /* 4321 802.11n dualband id */
  75 #define BCM4321_D11N2G_ID       0x4329          /* 4321 802.11n 2.4Ghz band id */
  76 #define BCM4321_D11N5G_ID       0x432a          /* 4321 802.11n 5Ghz band id */
  77 #define BCM4322_D11N_ID         0x432b          /* 4322 802.11n dualband device */
  78 #define BCM4322_D11N2G_ID       0x432c          /* 4322 802.11n 2.4GHz device */
  79 #define BCM4322_D11N5G_ID       0x432d          /* 4322 802.11n 5GHz device */
  80 #define BCM43221_D11N2G_ID      0x4341          /* 43221 802.11n 2.4GHz device */
  81 #define BCM43231_D11N2G_ID      0x4340          /* 43231 802.11n 2.4GHz device */
  82 #define BCM43222_D11N_ID        0x4350          /* 43222 802.11n dualband device */
  83 #define BCM43222_D11N2G_ID      0x4351          /* 43222 802.11n 2.4GHz device */
  84 #define BCM43222_D11N5G_ID      0x4352          /* 43222 802.11n 5GHz device */
  85 #define BCM43224_D11N_ID        0x4353          /* 43224 802.11n dualband device */
  86 #define BCM43224_D11N2G_ID      0x4354          /* 43224 802.11n 2.4GHz device */
  87 #define BCM43224_D11N5G_ID      0x4355          /* 43224 802.11n 5GHz device */
  88 #define BCM4319_D11N_ID         0x4337          /* 4319 802.11n dualband device */
  89 #define BCM4319_D11N2G_ID       0x4338          /* 4319 802.11n 2.4G device */
  90 #define BCM4319_D11N5G_ID       0x4339          /* 4319 802.11n 5G device */
  91 #define BCM43225_D11N2G_ID      0x4357          /* 43225 802.11n 2.4GHz device */
  92 #define BCM43421_D11N_ID        0xA99D          /* 43421 802.11n dualband device */
  93 #define BCM4315_D11DUAL_ID      0x4334          /* 4315 802.11a/g id */
  94 #define BCM4315_D11G_ID         0x4335          /* 4315 802.11g id */
  95 #define BCM4315_D11A_ID         0x4336          /* 4315 802.11a id */
  96
  97
  98 #define BCMGPRS_UART_ID         0x4333          /* Uart id used by 4306/gprs card */
  99 #define BCMGPRS2_UART_ID        0x4344          /* Uart id used by 4306/gprs card */
 100 #define FPGA_JTAGM_ID           0x43f0          /* FPGA jtagm device id */
 101 #define BCM_JTAGM_ID            0x43f1          /* BCM jtagm device id */
 102 #define SDIOH_FPGA_ID           0x43f2          /* sdio host fpga */
 103 #define BCM_SDIOH_ID            0x43f3          /* BCM sdio host id */
 104 #define SDIOD_FPGA_ID           0x43f4          /* sdio device fpga */
 105 #define SPIH_FPGA_ID            0x43f5          /* PCI SPI Host Controller FPGA */
 106 #define BCM_SPIH_ID             0x43f6          /* Synopsis SPI Host Controller */
 107 #define MIMO_FPGA_ID            0x43f8          /* FPGA mimo minimacphy device id */
 108 #define BCM_JTAGM2_ID           0x43f9          /* BCM alternate jtagm device id */
 109 #define SDHCI_FPGA_ID           0x43fa          /* Standard SDIO Host Controller FPGA */
 110 #define BCM4402_ENET_ID         0x4402          /* 4402 enet */
 111 #define BCM4402_V90_ID          0x4403          /* 4402 v90 codec */
 112 #define BCM4410_DEVICE_ID       0x4410          /* bcm44xx family pci iline */
 113 #define BCM4412_DEVICE_ID       0x4412          /* bcm44xx family pci enet */
 114 #define BCM4430_DEVICE_ID       0x4430          /* bcm44xx family cardbus iline */
 115 #define BCM4432_DEVICE_ID       0x4432          /* bcm44xx family cardbus enet */
 116 #define BCM4704_ENET_ID         0x4706          /* 4704 enet (Use 47XX_ENET_ID instead!) */
 117 #define BCM4710_DEVICE_ID       0x4710          /* 4710 primary function 0 */
 118 #define BCM47XX_AUDIO_ID        0x4711          /* 47xx audio codec */
 119 #define BCM47XX_V90_ID          0x4712          /* 47xx v90 codec */
 120 #define BCM47XX_ENET_ID         0x4713          /* 47xx enet */
 121 #define BCM47XX_EXT_ID          0x4714          /* 47xx external i/f */
 122 #define BCM47XX_GMAC_ID         0x4715          /* 47xx Unimac based GbE */
 123 #define BCM47XX_USBH_ID         0x4716          /* 47xx usb host */
 124 #define BCM47XX_USBD_ID         0x4717          /* 47xx usb device */
 125 #define BCM47XX_IPSEC_ID        0x4718          /* 47xx ipsec */
 126 #define BCM47XX_ROBO_ID         0x4719          /* 47xx/53xx roboswitch core */
 127 #define BCM47XX_USB20H_ID       0x471a          /* 47xx usb 2.0 host */
 128 #define BCM47XX_USB20D_ID       0x471b          /* 47xx usb 2.0 device */
 129 #define BCM47XX_ATA100_ID       0x471d          /* 47xx parallel ATA */
 130 #define BCM47XX_SATAXOR_ID      0x471e          /* 47xx serial ATA & XOR DMA */
 131 #define BCM47XX_GIGETH_ID       0x471f          /* 47xx GbE (5700) */
 132 #define BCM4712_MIPS_ID         0x4720          /* 4712 base devid */
 133 #define BCM4716_DEVICE_ID       0x4722          /* 4716 base devid */
 134 #define BCM47XX_SMBUS_EMU_ID    0x47fe          /* 47xx emulated SMBus device */
 135 #define BCM47XX_XOR_EMU_ID      0x47ff          /* 47xx emulated XOR engine */
 136 #define EPI41210_DEVICE_ID      0xa0fa          /* bcm4210 */
 137 #define EPI41230_DEVICE_ID      0xa10e          /* bcm4230 */
 138 #define JINVANI_SDIOH_ID        0x4743          /* Jinvani SDIO Gold Host */
 139 #define BCM27XX_SDIOH_ID        0x2702          /* BCM27xx Standard SDIO Host */
 140 #define PCIXX21_FLASHMEDIA_ID   0x803b          /* TI PCI xx21 Standard Host Controller */
 141 #define PCIXX21_SDIOH_ID        0x803c          /* TI PCI xx21 Standard Host Controller */
 142 #define R5C822_SDIOH_ID         0x0822          /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
 143
 144 /* Chip ID's */
 145 #define BCM4306_CHIP_ID         0x4306          /* 4306 chipcommon chipid */
 146 #define BCM4311_CHIP_ID         0x4311          /* 4311 PCIe 802.11a/b/g */
 147 #define BCM4312_CHIP_ID         0x4312          /* 4312 chipcommon chipid */
 148 #define BCM4313_CHIP_ID         0x4313          /* 4313 chipcommon chipid */
 149 #define BCM4318_CHIP_ID         0x4318          /* 4318 chipcommon chipid */
 150 #define BCM4320_CHIP_ID         0x4320          /* 4320 chipcommon chipid */
 151 #define BCM4321_CHIP_ID         0x4321          /* 4321 chipcommon chipid */
 152 #define BCM4322_CHIP_ID         0x4322          /* 4322 chipcommon chipid */
 153 #define BCM43221_CHIP_ID        43221           /* 43221 chipcommon chipid (OTP chipid) */
 154 #define BCM43231_CHIP_ID        43231           /* 43231 chipcommon chipid (OTP chipid) */
 155 #define BCM43111_CHIP_ID        43111           /* 43111 chipcommon chipid (OTP chipid) */
 156 #define BCM43112_CHIP_ID        43112           /* 43112 chipcommon chipid (OTP chipid) */
 157 #define BCM43222_CHIP_ID        43222           /* 43222 chipcommon chipid */
 158 #define BCM43224_CHIP_ID        43224           /* 43224 chipcommon chipid */
 159 #define BCM43225_CHIP_ID        43225           /* 43225 chipcommon chipid (OTP chipid) */
 160 #define BCM43421_CHIP_ID        43421           /* 43421 chipcommon chipid */
 161 #define BCM4342_CHIP_ID         4342            /* 4342 chipcommon chipid (OTP, RBBU) */
 162 #define BCM4325_CHIP_ID         0x4325          /* 4325 chip id */
 163 #define BCM4328_CHIP_ID         0x4328          /* 4328 chip id */
 164 #define BCM4402_CHIP_ID         0x4402          /* 4402 chipid */
 165 #define BCM4704_CHIP_ID         0x4704          /* 4704 chipcommon chipid */
 166 #define BCM4710_CHIP_ID         0x4710          /* 4710 chipid */
 167 #define BCM4712_CHIP_ID         0x4712          /* 4712 chipcommon chipid */
 168 #define BCM4716_CHIP_ID         0x4716          /* 4716 chipcommon chipid */
 169 #define BCM47162_CHIP_ID        47162           /* 47162 chipcommon chipid */
 170 #define BCM4748_CHIP_ID         0x4748          /* 4716 chipcommon chipid (OTP, RBBU) */
 171 #define BCM4785_CHIP_ID         0x4785          /* 4785 chipcommon chipid */
 172 #define BCM5350_CHIP_ID         0x5350          /* 5350 chipcommon chipid */
 173 #define BCM5352_CHIP_ID         0x5352          /* 5352 chipcommon chipid */
 174 #define BCM5354_CHIP_ID         0x5354          /* 5354 chipcommon chipid */
 175 #define BCM5365_CHIP_ID         0x5365          /* 5365 chipcommon chipid */
 176 #define BCM4319_CHIP_ID         0x4319          /* 4319 chip id */
 177 #define BCM4329_CHIP_ID         0x4329          /* 4329 chipcommon chipid */
 178
 179
 180 /* Package ID's */
 181 #define BCM4303_PKG_ID          2               /* 4303 package id */
 182 #define BCM4309_PKG_ID          1               /* 4309 package id */
 183 #define BCM4712LARGE_PKG_ID     0               /* 340pin 4712 package id */
 184 #define BCM4712SMALL_PKG_ID     1               /* 200pin 4712 package id */
 185 #define BCM4712MID_PKG_ID       2               /* 225pin 4712 package id */
 186 #define BCM4328USBD11G_PKG_ID   2               /* 4328 802.11g USB package id */
 187 #define BCM4328USBDUAL_PKG_ID   3               /* 4328 802.11a/g USB package id */
 188 #define BCM4328SDIOD11G_PKG_ID  4               /* 4328 802.11g SDIO package id */
 189 #define BCM4328SDIODUAL_PKG_ID  5               /* 4328 802.11a/g SDIO package id */
 190 #define BCM4329_289PIN_PKG_ID   0               /* 4329 289-pin package id */
 191 #define BCM4329_182PIN_PKG_ID   1               /* 4329N 182-pin package id */
 192 #define BCM5354E_PKG_ID         1               /* 5354E package id */
 193 #define BCM4716_PKG_ID          8               /* 4716 package id */
 194 #define BCM4717_PKG_ID          9               /* 4717 package id */
 195 #define BCM4718_PKG_ID          10              /* 4718 package id */
 196 #define HDLSIM5350_PKG_ID       1               /* HDL simulator package id for a 5350 */
 197 #define HDLSIM_PKG_ID           14              /* HDL simulator package id */
 198 #define HWSIM_PKG_ID            15              /* Hardware simulator package id */
 199 #define BCM43224_FAB_CSM        0x8             /* the chip is manufactured by CSM */
 200 #define BCM43224_FAB_SMIC       0xa             /* the chip is manufactured by SMIC */
 201
 202 #define PCIXX21_FLASHMEDIA0_ID  0x8033          /* TI PCI xx21 Standard Host Controller */
 203 #define PCIXX21_SDIOH0_ID       0x8034          /* TI PCI xx21 Standard Host Controller */
 204
 205 /* boardflags */
 206 #define BFL_BTC2WIRE            0x00000001  /* Board implements old 2wire Bluetooth coexistence */
 207 #define BFL_PACTRL              0x00000002  /* Board has gpio 9 controlling the PA */
 208 #define BFL_AIRLINEMODE         0x00000004  /* Board implements gpio 13 radio disable indication */
 209 #define BFL_ENETROBO            0x00000010  /* Board has robo switch or core */
 210 #define BFL_CCKHIPWR            0x00000040  /* Can do high-power CCK transmission */
 211 #define BFL_ENETADM             0x00000080  /* Board has ADMtek switch */
 212 #define BFL_ENETVLAN            0x00000100  /* Board has VLAN capability */
 213 #ifdef WLAFTERBURNER
 214 #define BFL_AFTERBURNER         0x00000200  /* Board supports Afterburner mode */
 215 #endif /* WLAFTERBURNER */
 216 #define BFL_NOPCI               0x00000400  /* Board leaves PCI floating */
 217 #define BFL_FEM                 0x00000800  /* Board supports the Front End Module */
 218 #define BFL_EXTLNA              0x00001000  /* Board has an external LNA in 2.4GHz band */
 219 #define BFL_HGPA                0x00002000  /* Board has a high gain PA */
 220 #define BFL_BTC2WIRE_ALTGPIO    0x00004000  /* Board's BTC 2wire is in the alternate gpios */
 221 #define BFL_ALTIQ               0x00008000  /* Alternate I/Q settings */
 222 #define BFL_NOPA                0x00010000  /* Board has no PA */
 223 #define BFL_RSSIINV             0x00020000  /* Board's RSSI uses positive slope(not TSSI) */
 224 #define BFL_PAREF               0x00040000  /* Board uses the PARef LDO */
 225 #define BFL_3TSWITCH            0x00080000  /* Board uses a triple throw switch shared with BT */
 226 #define BFL_PHASESHIFT          0x00100000  /* Board can support phase shifter */
 227 #define BFL_BUCKBOOST           0x00200000  /* Power topology uses BUCKBOOST */
 228 #define BFL_FEM_BT              0x00400000  /* Board has FEM and switch to share antenna w/ BT */
 229 #define BFL_NOCBUCK             0x00800000  /* Power topology doesn't use CBUCK */
 230 #define BFL_CCKFAVOREVM         0x01000000  /* Favor CCK EVM over spectral mask */
 231 #define BFL_PALDO               0x02000000  /* Power topology uses PALDO */
 232 #define BFL_EXTLNA_5GHz         0x10000000  /* Board has an external LNA in 5GHz band */
 233 #define BFL_TRSW_1by2           0x20000000  /* Board has 2 TRSW's in 1by2 designs */
 234 #define BFL_LO_TRSW_R_5GHz      0x40000000  /* In 5G do not throw TRSW to T for clipLO gain */
 235 #define BFL_ELNA_GAINDEF        0x80000000  /* Backoff InitGain based on elna_2g/5g field
 236                                              * when this flag is set
 237                                              */
 238
 239 /* boardflags2 */
 240 #define BFL2_RXBB_INT_REG_DIS   0x00000001  /* Board has an external rxbb regulator */
 241 #define BFL2_APLL_WAR           0x00000002  /* Flag to implement alternative A-band PLL settings */
 242 #define BFL2_TXPWRCTRL_EN       0x00000004  /* Board permits enabling TX Power Control */
 243 #define BFL2_2X4_DIV            0x00000008  /* Board supports the 2X4 diversity switch */
 244 #define BFL2_5G_PWRGAIN         0x00000010  /* Board supports 5G band power gain */
 245 #define BFL2_PCIEWAR_OVR        0x00000020  /* Board overrides ASPM and Clkreq settings */
 246 #define BFL2_CAESERS_BRD        0x00000040  /* Board is Caesers brd (unused by sw) */
 247 #define BFL2_BTC3WIRE           0x00000080  /* Board used 3-wire BTC */
 248 #define BFL2_SKWRKFEM_BRD       0x00000100  /* 4321mcm93 board uses Skyworks FEM */
 249 #define BFL2_SPUR_WAR           0x00000200  /* Board has a WAR for clock-harmonic spurs */
 250 #define BFL2_GPLL_WAR           0x00000400  /* Flag to implement alternative G-band PLL settings */
 251 #define BFL2_TRISTATE_LED       0x00000800  /* Tri-state the LED */
 252 #define BFL2_SINGLEANT_CCK      0x00001000  /* Tx CCK pkts on Ant 0 only */
 253 #define BFL2_2G_SPUR_WAR        0x00002000  /* Board has a WAR to reduce and avoid clock-harmonic
 254                                              * spurs in 2G band
 255                                              */
 256 #define BFL2_BPHY_ALL_TXCORES   0x00004000  /* Transmit bphy frames using all tx cores */
 257 #define BFL2_FCC_BANDEDGE_WAR   0x00008000  /* using 40Mhz LPF for 20Mhz bandedge channels */
 258 #define BFL2_GPLL_WAR2          0x00010000  /* Flag to widen G-band PLL loop b/w */
 259 #define BFL2_INTERNDET_TXIQCAL  0x00040000  /* Use internal envelope detector for TX IQCAL */
 260
 261 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
 262 #define BOARD_GPIO_BTC3W_IN     0x850   /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
 263 #define BOARD_GPIO_BTC3W_OUT    0x020   /* bit 5 is TX_CONF */
 264 #define BOARD_GPIO_BTCMOD_IN    0x010   /* bit 4 is the alternate BT Coexistance Input */
 265 #define BOARD_GPIO_BTCMOD_OUT   0x020   /* bit 5 is the alternate BT Coexistance Out */
 266 #define BOARD_GPIO_BTC_IN       0x080   /* bit 7 is BT Coexistance Input */
 267 #define BOARD_GPIO_BTC_OUT      0x100   /* bit 8 is BT Coexistance Out */
 268 #define BOARD_GPIO_PACTRL       0x200   /* bit 9 controls the PA on new 4306 boards */
 269 #define BOARD_GPIO_12           0x1000  /* gpio 12 */
 270 #define BOARD_GPIO_13           0x2000  /* gpio 13 */
 271
 272 #define GPIO_BTC4W_OUT_4312  0x010  /* bit 4 is BT_IODISABLE */
 273 #define GPIO_BTC4W_OUT_43224  0x020  /* bit 5 is BT_IODISABLE */
 274 #define GPIO_BTC4W_OUT_43225  0x0e0  /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
 275 #define GPIO_BTC4W_OUT_43421  0x020  /* bit 5 is BT_IODISABLE */
 276
 277 #define PCI_CFG_GPIO_SCS        0x10    /* PCI config space bit 4 for 4306c0 slow clock source */
 278 #define PCI_CFG_GPIO_HWRAD      0x20    /* PCI config space GPIO 13 for hw radio disable */
 279 #define PCI_CFG_GPIO_XTAL       0x40    /* PCI config space GPIO 14 for Xtal powerup */
 280 #define PCI_CFG_GPIO_PLL        0x80    /* PCI config space GPIO 15 for PLL powerdown */
 281
 282 /* power control defines */
 283 #define PLL_DELAY               150             /* us pll on delay */
 284 #define FREF_DELAY              200             /* us fref change delay */
 285 #define MIN_SLOW_CLK            32              /* us Slow clock period */
 286 #define XTAL_ON_DELAY           1000            /* us crystal power-on delay */
 287
 288 /* Reference Board Types */
 289 #define BU4710_BOARD            0x0400
 290 #define VSIM4710_BOARD          0x0401
 291 #define QT4710_BOARD            0x0402
 292
 293 #define BU4309_BOARD            0x040a
 294 #define BCM94309CB_BOARD        0x040b
 295 #define BCM94309MP_BOARD        0x040c
 296 #define BCM4309AP_BOARD         0x040d
 297
 298 #define BCM94302MP_BOARD        0x040e
 299
 300 #define BU4306_BOARD            0x0416
 301 #define BCM94306CB_BOARD        0x0417
 302 #define BCM94306MP_BOARD        0x0418
 303
 304 #define BCM94710D_BOARD         0x041a
 305 #define BCM94710R1_BOARD        0x041b
 306 #define BCM94710R4_BOARD        0x041c
 307 #define BCM94710AP_BOARD        0x041d
 308
 309 #define BU2050_BOARD            0x041f
 310
 311
 312 #define BCM94309G_BOARD         0x0421
 313
 314 #define BU4704_BOARD            0x0423
 315 #define BU4702_BOARD            0x0424
 316
 317 #define BCM94306PC_BOARD        0x0425          /* pcmcia 3.3v 4306 card */
 318
 319
 320 #define BCM94702MN_BOARD        0x0428
 321
 322 /* BCM4702 1U CompactPCI Board */
 323 #define BCM94702CPCI_BOARD      0x0429
 324
 325 /* BCM4702 with BCM95380 VLAN Router */
 326 #define BCM95380RR_BOARD        0x042a
 327
 328 /* cb4306 with SiGe PA */
 329 #define BCM94306CBSG_BOARD      0x042b
 330
 331 /* cb4306 with SiGe PA */
 332 #define PCSG94306_BOARD         0x042d
 333
 334 /* bu4704 with sdram */
 335 #define BU4704SD_BOARD          0x042e
 336
 337 /* Dual 11a/11g Router */
 338 #define BCM94704AGR_BOARD       0x042f
 339
 340 /* 11a-only minipci */
 341 #define BCM94308MP_BOARD        0x0430
 342
 343
 344
 345 #define BU4712_BOARD            0x0444
 346 #define BU4712SD_BOARD          0x045d
 347 #define BU4712L_BOARD           0x045f
 348
 349 /* BCM4712 boards */
 350 #define BCM94712AP_BOARD        0x0445
 351 #define BCM94712P_BOARD         0x0446
 352
 353 /* BCM4318 boards */
 354 #define BU4318_BOARD            0x0447
 355 #define CB4318_BOARD            0x0448
 356 #define MPG4318_BOARD           0x0449
 357 #define MP4318_BOARD            0x044a
 358 #define SD4318_BOARD            0x044b
 359
 360 /* BCM63XX boards */
 361 #define BCM96338_BOARD          0x6338
 362 #define BCM96348_BOARD          0x6348
 363 #define BCM96358_BOARD          0x6358
 364 #define BCM96368_BOARD          0x6368
 365
 366 /* Another mp4306 with SiGe */
 367 #define BCM94306P_BOARD         0x044c
 368
 369 /* mp4303 */
 370 #define BCM94303MP_BOARD        0x044e
 371
 372 /* mpsgh4306 */
 373 #define BCM94306MPSGH_BOARD     0x044f
 374
 375 /* BRCM 4306 w/ Front End Modules */
 376 #define BCM94306MPM             0x0450
 377 #define BCM94306MPL             0x0453
 378
 379 /* 4712agr */
 380 #define BCM94712AGR_BOARD       0x0451
 381
 382 /* pcmcia 4303 */
 383 #define PC4303_BOARD            0x0454
 384
 385 /* 5350K */
 386 #define BCM95350K_BOARD         0x0455
 387
 388 /* 5350R */
 389 #define BCM95350R_BOARD         0x0456
 390
 391 /* 4306mplna */
 392 #define BCM94306MPLNA_BOARD     0x0457
 393
 394 /* 4320 boards */
 395 #define BU4320_BOARD            0x0458
 396 #define BU4320S_BOARD           0x0459
 397 #define BCM94320PH_BOARD        0x045a
 398
 399 /* 4306mph */
 400 #define BCM94306MPH_BOARD       0x045b
 401
 402 /* 4306pciv */
 403 #define BCM94306PCIV_BOARD      0x045c
 404
 405 #define BU4712SD_BOARD          0x045d
 406
 407 #define BCM94320PFLSH_BOARD     0x045e
 408
 409 #define BU4712L_BOARD           0x045f
 410 #define BCM94712LGR_BOARD       0x0460
 411 #define BCM94320R_BOARD         0x0461
 412
 413 #define BU5352_BOARD            0x0462
 414
 415 #define BCM94318MPGH_BOARD      0x0463
 416
 417 #define BU4311_BOARD            0x0464
 418 #define BCM94311MC_BOARD        0x0465
 419 #define BCM94311MCAG_BOARD      0x0466
 420
 421 #define BCM95352GR_BOARD        0x0467
 422
 423 /* bcm95351agr */
 424 #define BCM95351AGR_BOARD       0x0470
 425
 426 /* bcm94704mpcb */
 427 #define BCM94704MPCB_BOARD      0x0472
 428
 429 /* 4785 boards */
 430 #define BU4785_BOARD            0x0478
 431
 432 /* 4321 boards */
 433 #define BU4321_BOARD            0x046b
 434 #define BU4321E_BOARD           0x047c
 435 #define MP4321_BOARD            0x046c
 436 #define CB2_4321_BOARD          0x046d
 437 #define CB2_4321_AG_BOARD       0x0066
 438 #define MC4321_BOARD            0x046e
 439
 440 /* 4328 boards */
 441 #define BU4328_BOARD            0x0481
 442 #define BCM4328SDG_BOARD        0x0482
 443 #define BCM4328SDAG_BOARD       0x0483
 444 #define BCM4328UG_BOARD         0x0484
 445 #define BCM4328UAG_BOARD        0x0485
 446 #define BCM4328PC_BOARD         0x0486
 447 #define BCM4328CF_BOARD         0x0487
 448
 449 /* 4325 boards */
 450 #define BCM94325DEVBU_BOARD     0x0490
 451 #define BCM94325BGABU_BOARD     0x0491
 452
 453 /* 4322 boards */
 454 #define BCM94322MC_SSID         0x04a4
 455 #define BCM94322U_SSID          0x04a8
 456 #define BCM94322HM_SSID         0x04b0
 457 #define BCM94322USB_SSID        0x04a8
 458 #define BCM94322USB2D_SSID      0x04bf
 459
 460 #define BCM94325SDGMDL_BOARD    0x04aa
 461 #define BCM94325SDGMDL2_BOARD   0x04c6
 462
 463 /* 4716 boards */
 464 #define BCM94716NR2_SSID        0x04cd
 465
 466 /* 4319 boards */
 467 #define BCM94319DEVBU_SSID      0X04e5
 468 #define BCM94319USBNP4L_SSID    0X04e6
 469 #define BCM94319WLUSBN4L_SSID   0X04e7
 470 #define BCM94319SDG_SSID        0X04ea
 471 #define BCM94319LCUSBSDN4L_SSID 0X04eb
 472 #define BCM94319LCSDN4L_SSID    0X0507
 473 #define BCM94319LSUSBN4L_SSID   0X0508
 474
 475 /* # of GPIO pins */
 476 #define GPIO_NUMPINS            16
 477
 478 /* radio ID codes */
 479 #define NORADIO_ID              0xe4f5
 480 #define NORADIO_IDCODE          0x4e4f5246
 481
 482 #define BCM2050_ID              0x2050
 483 #define BCM2050_IDCODE          0x02050000
 484 #define BCM2050A0_IDCODE        0x1205017f
 485 #define BCM2050A1_IDCODE        0x2205017f
 486 #define BCM2050R8_IDCODE        0x8205017f
 487
 488 #define BCM2055_ID              0x2055
 489 #define BCM2055_IDCODE          0x02055000
 490 #define BCM2055A0_IDCODE        0x1205517f
 491
 492 #define BCM2056_ID              0x2056
 493 #define BCM2056_IDCODE          0x02056000
 494 #define BCM2056A0_IDCODE        0x1205517f
 495
 496 #define BCM2060_ID              0x2060
 497 #define BCM2060_IDCODE          0x02060000
 498 #define BCM2060WW_IDCODE        0x1206017f
 499
 500 #define BCM2062_ID              0x2062
 501 #define BCM2062_IDCODE          0x02062000
 502 #define BCM2062A0_IDCODE        0x0206217f
 503
 504 #define BCM2063_ID              0x2063
 505 #define BCM2063_IDCODE          0x02063000
 506 #define BCM2063A0_IDCODE        0x0206317f
 507
 508 /* parts of an idcode: */
 509 #define IDCODE_MFG_MASK         0x00000fff
 510 #define IDCODE_MFG_SHIFT        0
 511 #define IDCODE_ID_MASK          0x0ffff000
 512 #define IDCODE_ID_SHIFT         12
 513 #define IDCODE_REV_MASK         0xf0000000
 514 #define IDCODE_REV_SHIFT        28
 515
 516 #endif /* _BCMDEVS_H */