Broadcom SDK and wireless driver: another attempt to update to ver. 5.10.147.0
[tomato.git] / release / src-rt / include / aidmp.h
blobf436ccdca6483c1bd4c26a6e92307632f7cf254b
1 /*
2 * Broadcom AMBA Interconnect definitions.
4 * Copyright (C) 2009, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: aidmp.h,v 13.2 2008/03/28 19:02:00 Exp $
15 #ifndef _AIDMP_H
16 #define _AIDMP_H
18 /* Manufacturer Ids */
19 #define MFGID_ARM 0x43b
20 #define MFGID_BRCM 0x4bf
21 #define MFGID_MIPS 0x4a7
23 /* Componnent Classes */
24 #define CC_SIM 0
25 #define CC_EROM 1
26 #define CC_CORESIGHT 9
27 #define CC_VERIF 0xb
28 #define CC_OPTIMO 0xd
29 #define CC_GEN 0xe
30 #define CC_PRIMECELL 0xf
32 /* Enumeration ROM registers */
33 #define ER_EROMENTRY 0x000
34 #define ER_REMAPCONTROL 0xe00
35 #define ER_REMAPSELECT 0xe04
36 #define ER_MASTERSELECT 0xe10
37 #define ER_ITCR 0xf00
38 #define ER_ITIP 0xf04
40 /* Erom entries */
41 #define ER_TAG 0xe
42 #define ER_TAG1 0x6
43 #define ER_VALID 1
44 #define ER_CI 0
45 #define ER_MP 2
46 #define ER_ADD 4
47 #define ER_END 0xe
48 #define ER_BAD 0xffffffff
50 /* EROM CompIdentA */
51 #define CIA_MFG_MASK 0xfff00000
52 #define CIA_MFG_SHIFT 20
53 #define CIA_CID_MASK 0x000fff00
54 #define CIA_CID_SHIFT 8
55 #define CIA_CCL_MASK 0x000000f0
56 #define CIA_CCL_SHIFT 4
58 /* EROM CompIdentB */
59 #define CIB_REV_MASK 0xff000000
60 #define CIB_REV_SHIFT 24
61 #define CIB_NSW_MASK 0x00f80000
62 #define CIB_NSW_SHIFT 19
63 #define CIB_NMW_MASK 0x0007c000
64 #define CIB_NMW_SHIFT 14
65 #define CIB_NSP_MASK 0x00003e00
66 #define CIB_NSP_SHIFT 9
67 #define CIB_NMP_MASK 0x000001f0
68 #define CIB_NMP_SHIFT 4
70 /* EROM MasterPortDesc */
71 #define MPD_MUI_MASK 0x0000ff00
72 #define MPD_MUI_SHIFT 8
73 #define MPD_MP_MASK 0x000000f0
74 #define MPD_MP_SHIFT 4
76 /* EROM AddrDesc */
77 #define AD_ADDR_MASK 0xfffff000
78 #define AD_SP_MASK 0x00000f00
79 #define AD_SP_SHIFT 8
80 #define AD_ST_MASK 0x000000c0
81 #define AD_ST_SHIFT 6
82 #define AD_ST_SLAVE 0x00000000
83 #define AD_ST_BRIDGE 0x00000040
84 #define AD_ST_SWRAP 0x00000080
85 #define AD_ST_MWRAP 0x000000c0
86 #define AD_SZ_MASK 0x00000030
87 #define AD_SZ_SHIFT 4
88 #define AD_SZ_4K 0x00000000
89 #define AD_SZ_8K 0x00000010
90 #define AD_SZ_16K 0x00000020
91 #define AD_SZ_SZD 0x00000030
92 #define AD_AG32 0x00000008
93 #define AD_ADDR_ALIGN 0x00000fff
94 #define AD_SZ_BASE 0x00001000 /* 4KB */
96 /* EROM SizeDesc */
97 #define SD_SZ_MASK 0xfffff000
98 #define SD_SG32 0x00000008
99 #define SD_SZ_ALIGN 0x00000fff
102 #ifndef _LANGUAGE_ASSEMBLY
104 typedef volatile struct _aidmp {
105 uint32 oobselina30; /* 0x000 */
106 uint32 oobselina74; /* 0x004 */
107 uint32 PAD[6];
108 uint32 oobselinb30; /* 0x020 */
109 uint32 oobselinb74; /* 0x024 */
110 uint32 PAD[6];
111 uint32 oobselinc30; /* 0x040 */
112 uint32 oobselinc74; /* 0x044 */
113 uint32 PAD[6];
114 uint32 oobselind30; /* 0x060 */
115 uint32 oobselind74; /* 0x064 */
116 uint32 PAD[38];
117 uint32 oobselouta30; /* 0x100 */
118 uint32 oobselouta74; /* 0x104 */
119 uint32 PAD[6];
120 uint32 oobseloutb30; /* 0x120 */
121 uint32 oobseloutb74; /* 0x124 */
122 uint32 PAD[6];
123 uint32 oobseloutc30; /* 0x140 */
124 uint32 oobseloutc74; /* 0x144 */
125 uint32 PAD[6];
126 uint32 oobseloutd30; /* 0x160 */
127 uint32 oobseloutd74; /* 0x164 */
128 uint32 PAD[38];
129 uint32 oobsynca; /* 0x200 */
130 uint32 oobseloutaen; /* 0x204 */
131 uint32 PAD[6];
132 uint32 oobsyncb; /* 0x220 */
133 uint32 oobseloutben; /* 0x224 */
134 uint32 PAD[6];
135 uint32 oobsyncc; /* 0x240 */
136 uint32 oobseloutcen; /* 0x244 */
137 uint32 PAD[6];
138 uint32 oobsyncd; /* 0x260 */
139 uint32 oobseloutden; /* 0x264 */
140 uint32 PAD[38];
141 uint32 oobaextwidth; /* 0x300 */
142 uint32 oobainwidth; /* 0x304 */
143 uint32 oobaoutwidth; /* 0x308 */
144 uint32 PAD[5];
145 uint32 oobbextwidth; /* 0x320 */
146 uint32 oobbinwidth; /* 0x324 */
147 uint32 oobboutwidth; /* 0x328 */
148 uint32 PAD[5];
149 uint32 oobcextwidth; /* 0x340 */
150 uint32 oobcinwidth; /* 0x344 */
151 uint32 oobcoutwidth; /* 0x348 */
152 uint32 PAD[5];
153 uint32 oobdextwidth; /* 0x360 */
154 uint32 oobdinwidth; /* 0x364 */
155 uint32 oobdoutwidth; /* 0x368 */
156 uint32 PAD[37];
157 uint32 ioctrlset; /* 0x400 */
158 uint32 ioctrlclear; /* 0x404 */
159 uint32 ioctrl; /* 0x408 */
160 uint32 PAD[61];
161 uint32 iostatus; /* 0x500 */
162 uint32 PAD[127];
163 uint32 ioctrlwidth; /* 0x700 */
164 uint32 iostatuswidth; /* 0x704 */
165 uint32 PAD[62];
166 uint32 resetctrl; /* 0x800 */
167 uint32 resetstatus; /* 0x804 */
168 uint32 resetreadid; /* 0x808 */
169 uint32 resetwriteid; /* 0x80c */
170 uint32 PAD[60];
171 uint32 errlogctrl; /* 0x900 */
172 uint32 errlogdone; /* 0x904 */
173 uint32 errlogstatus; /* 0x908 */
174 uint32 errlogaddrlo; /* 0x90c */
175 uint32 errlogaddrhi; /* 0x910 */
176 uint32 errlogid; /* 0x914 */
177 uint32 errloguser; /* 0x918 */
178 uint32 errlogflags; /* 0x91c */
179 uint32 PAD[56];
180 uint32 intstatus; /* 0xa00 */
181 uint32 PAD[127];
182 uint32 config; /* 0xe00 */
183 uint32 PAD[63];
184 uint32 itcr; /* 0xf00 */
185 uint32 PAD[3];
186 uint32 itipooba; /* 0xf10 */
187 uint32 itipoobb; /* 0xf14 */
188 uint32 itipoobc; /* 0xf18 */
189 uint32 itipoobd; /* 0xf1c */
190 uint32 PAD[4];
191 uint32 itipoobaout; /* 0xf30 */
192 uint32 itipoobbout; /* 0xf34 */
193 uint32 itipoobcout; /* 0xf38 */
194 uint32 itipoobdout; /* 0xf3c */
195 uint32 PAD[4];
196 uint32 itopooba; /* 0xf50 */
197 uint32 itopoobb; /* 0xf54 */
198 uint32 itopoobc; /* 0xf58 */
199 uint32 itopoobd; /* 0xf5c */
200 uint32 PAD[4];
201 uint32 itopoobain; /* 0xf70 */
202 uint32 itopoobbin; /* 0xf74 */
203 uint32 itopoobcin; /* 0xf78 */
204 uint32 itopoobdin; /* 0xf7c */
205 uint32 PAD[4];
206 uint32 itopreset; /* 0xf90 */
207 uint32 PAD[15];
208 uint32 peripherialid4; /* 0xfd0 */
209 uint32 peripherialid5; /* 0xfd4 */
210 uint32 peripherialid6; /* 0xfd8 */
211 uint32 peripherialid7; /* 0xfdc */
212 uint32 peripherialid0; /* 0xfe0 */
213 uint32 peripherialid1; /* 0xfe4 */
214 uint32 peripherialid2; /* 0xfe8 */
215 uint32 peripherialid3; /* 0xfec */
216 uint32 componentid0; /* 0xff0 */
217 uint32 componentid1; /* 0xff4 */
218 uint32 componentid2; /* 0xff8 */
219 uint32 componentid3; /* 0xffc */
220 } aidmp_t;
222 #endif /* _LANGUAGE_ASSEMBLY */
224 /* Out-of-band Router registers */
225 #define OOB_BUSCONFIG 0x020
226 #define OOB_STATUSA 0x100
227 #define OOB_STATUSB 0x104
228 #define OOB_STATUSC 0x108
229 #define OOB_STATUSD 0x10c
230 #define OOB_ENABLEA0 0x200
231 #define OOB_ENABLEA1 0x204
232 #define OOB_ENABLEA2 0x208
233 #define OOB_ENABLEA3 0x20c
234 #define OOB_ENABLEB0 0x280
235 #define OOB_ENABLEB1 0x284
236 #define OOB_ENABLEB2 0x288
237 #define OOB_ENABLEB3 0x28c
238 #define OOB_ENABLEC0 0x300
239 #define OOB_ENABLEC1 0x304
240 #define OOB_ENABLEC2 0x308
241 #define OOB_ENABLEC3 0x30c
242 #define OOB_ENABLED0 0x380
243 #define OOB_ENABLED1 0x384
244 #define OOB_ENABLED2 0x388
245 #define OOB_ENABLED3 0x38c
246 #define OOB_ITCR 0xf00
247 #define OOB_ITIPOOBA 0xf10
248 #define OOB_ITIPOOBB 0xf14
249 #define OOB_ITIPOOBC 0xf18
250 #define OOB_ITIPOOBD 0xf1c
251 #define OOB_ITOPOOBA 0xf30
252 #define OOB_ITOPOOBB 0xf34
253 #define OOB_ITOPOOBC 0xf38
254 #define OOB_ITOPOOBD 0xf3c
256 /* DMP wrapper registers */
257 #define AI_OOBSELINA30 0x000
258 #define AI_OOBSELINA74 0x004
259 #define AI_OOBSELINB30 0x020
260 #define AI_OOBSELINB74 0x024
261 #define AI_OOBSELINC30 0x040
262 #define AI_OOBSELINC74 0x044
263 #define AI_OOBSELIND30 0x060
264 #define AI_OOBSELIND74 0x064
265 #define AI_OOBSELOUTA30 0x100
266 #define AI_OOBSELOUTA74 0x104
267 #define AI_OOBSELOUTB30 0x120
268 #define AI_OOBSELOUTB74 0x124
269 #define AI_OOBSELOUTC30 0x140
270 #define AI_OOBSELOUTC74 0x144
271 #define AI_OOBSELOUTD30 0x160
272 #define AI_OOBSELOUTD74 0x164
273 #define AI_OOBSYNCA 0x200
274 #define AI_OOBSELOUTAEN 0x204
275 #define AI_OOBSYNCB 0x220
276 #define AI_OOBSELOUTBEN 0x224
277 #define AI_OOBSYNCC 0x240
278 #define AI_OOBSELOUTCEN 0x244
279 #define AI_OOBSYNCD 0x260
280 #define AI_OOBSELOUTDEN 0x264
281 #define AI_OOBAEXTWIDTH 0x300
282 #define AI_OOBAINWIDTH 0x304
283 #define AI_OOBAOUTWIDTH 0x308
284 #define AI_OOBBEXTWIDTH 0x320
285 #define AI_OOBBINWIDTH 0x324
286 #define AI_OOBBOUTWIDTH 0x328
287 #define AI_OOBCEXTWIDTH 0x340
288 #define AI_OOBCINWIDTH 0x344
289 #define AI_OOBCOUTWIDTH 0x348
290 #define AI_OOBDEXTWIDTH 0x360
291 #define AI_OOBDINWIDTH 0x364
292 #define AI_OOBDOUTWIDTH 0x368
293 #define AI_IOCTRLSET 0x400
294 #define AI_IOCTRLCLEAR 0x404
295 #define AI_IOCTRL 0x408
296 #define AI_IOSTATUS 0x500
297 #define AI_IOCTRLWIDTH 0x700
298 #define AI_IOSTATUSWIDTH 0x704
299 #define AI_RESETCTRL 0x800
300 #define AI_RESETSTATUS 0x804
301 #define AI_RESETREADID 0x808
302 #define AI_RESETWRITEID 0x80c
303 #define AI_ERRLOGCTRL 0xa00
304 #define AI_ERRLOGDONE 0xa04
305 #define AI_ERRLOGSTATUS 0xa08
306 #define AI_ERRLOGADDRLO 0xa0c
307 #define AI_ERRLOGADDRHI 0xa10
308 #define AI_ERRLOGID 0xa14
309 #define AI_ERRLOGUSER 0xa18
310 #define AI_ERRLOGFLAGS 0xa1c
311 #define AI_INTSTATUS 0xa00
312 #define AI_CONFIG 0xe00
313 #define AI_ITCR 0xf00
314 #define AI_ITIPOOBA 0xf10
315 #define AI_ITIPOOBB 0xf14
316 #define AI_ITIPOOBC 0xf18
317 #define AI_ITIPOOBD 0xf1c
318 #define AI_ITIPOOBAOUT 0xf30
319 #define AI_ITIPOOBBOUT 0xf34
320 #define AI_ITIPOOBCOUT 0xf38
321 #define AI_ITIPOOBDOUT 0xf3c
322 #define AI_ITOPOOBA 0xf50
323 #define AI_ITOPOOBB 0xf54
324 #define AI_ITOPOOBC 0xf58
325 #define AI_ITOPOOBD 0xf5c
326 #define AI_ITOPOOBAIN 0xf70
327 #define AI_ITOPOOBBIN 0xf74
328 #define AI_ITOPOOBCIN 0xf78
329 #define AI_ITOPOOBDIN 0xf7c
330 #define AI_ITOPRESET 0xf90
331 #define AI_PERIPHERIALID4 0xfd0
332 #define AI_PERIPHERIALID5 0xfd4
333 #define AI_PERIPHERIALID6 0xfd8
334 #define AI_PERIPHERIALID7 0xfdc
335 #define AI_PERIPHERIALID0 0xfe0
336 #define AI_PERIPHERIALID1 0xfe4
337 #define AI_PERIPHERIALID2 0xfe8
338 #define AI_PERIPHERIALID3 0xfec
339 #define AI_COMPONENTID0 0xff0
340 #define AI_COMPONENTID1 0xff4
341 #define AI_COMPONENTID2 0xff8
342 #define AI_COMPONENTID3 0xffc
344 /* resetctrl */
345 #define AIRC_RESET 1
347 /* config */
348 #define AICFG_OOB 0x00000020
349 #define AICFG_IOS 0x00000010
350 #define AICFG_IOC 0x00000008
351 #define AICFG_TO 0x00000004
352 #define AICFG_ERRL 0x00000002
353 #define AICFG_RST 0x00000001
355 #endif /* _AIDMP_H */