release/src-rt/cfe/cfe/arch/mips/cpu/rm5200/include/r5kc0.h

   1 /*
   2  * r5kc0.h : base R5000 coprocessor 0 definitions
   3  * Copyright (c) 1997 Algorithmics Ltd.
   4  */
   5
   6 #ifndef _R5KC0_H_
   7 #ifdef __cplusplus
   8 extern "C" {
   9 #endif
  10 #define _R5KC0_H_
  11
  12 /*
  13  * R5000 Exception Codes
  14  */
  15 #define EXC_INTR        0       /* interrupt */
  16 #define EXC_MOD         1       /* tlb modification */
  17 #define EXC_TLBL        2       /* tlb miss (load/i-fetch) */
  18 #define EXC_TLBS        3       /* tlb miss (store) */
  19 #define EXC_ADEL        4       /* address error (load/i-fetch) */
  20 #define EXC_ADES        5       /* address error (store) */
  21 #define EXC_IBE         6       /* bus error (i-fetch) */
  22 #define EXC_DBE         7       /* data bus error (load/store) */
  23 #define EXC_SYS         8       /* system call */
  24 #define EXC_BP          9       /* breakpoint */
  25 #define EXC_RI          10      /* reserved instruction */
  26 #define EXC_CPU         11      /* coprocessor unusable */
  27 #define EXC_OVF         12      /* integer overflow */
  28 #define EXC_TRAP        13      /* trap exception */
  29 #define EXC_FPE         15      /* floating point exception */
  30 #if #cpu(rm52xx)
  31 #define EXC_WATCH       23      /* watchpoint - not on all variants */
  32 #endif
  33
  34 /*
  35  * R5000 Cause Register
  36  */
  37 #define CR_BD           0x80000000      /* branch delay */
  38 #define CR_CEMASK       0x30000000      /* coprocessor used */
  39 #define CR_CESHIFT      28
  40 #define CR_IV           0x00800000      /* interrupt vector enable */
  41
  42 /* interrupt pending bits */
  43 #define CR_SINT0        0x00000100      /* s/w interrupt 0 */
  44 #define CR_SINT1        0x00000200      /* s/w interrupt 1 */
  45 #define CR_HINT0        0x00000400      /* h/w interrupt 0 */
  46 #define CR_HINT1        0x00000800      /* h/w interrupt 1 */
  47 #define CR_HINT2        0x00001000      /* h/w interrupt 2 */
  48 #define CR_HINT3        0x00002000      /* h/w interrupt 3 */
  49 #define CR_HINT4        0x00004000      /* h/w interrupt 4 */
  50 #define CR_HINT5        0x00008000      /* h/w interrupt 5 */
  51
  52 /* alternative interrupt pending bit naming */
  53 #define CR_IP0          0x00000100
  54 #define CR_IP1          0x00000200
  55 #define CR_IP2          0x00000400
  56 #define CR_IP3          0x00000800
  57 #define CR_IP4          0x00001000
  58 #define CR_IP5          0x00002000
  59 #define CR_IP6          0x00004000
  60 #define CR_IP7          0x00008000
  61
  62 #define CR_IMASK        0x0000ff00      /* interrupt pending mask */
  63 #define CR_XMASK        0x0000007c      /* exception code mask */
  64 #define CR_XCPT(x)      ((x)<<2)
  65
  66
  67 /*
  68  * R5000 Status Register
  69  */
  70 #define SR_IE           0x00000001      /* interrupt enable */
  71 #define SR_EXL          0x00000002      /* exception level */
  72 #define SR_ERL          0x00000004      /* error level */
  73
  74 #define SR_KSU_MASK     0x00000018      /* ksu mode mask */
  75 #define SR_KSU_USER     0x00000010      /* user mode */
  76 #define SR_KSU_SPVS     0x00000008      /* supervisor mode */
  77 #define SR_KSU_KERN     0x00000000      /* kernel mode */
  78
  79 #define SR_UX           0x00000020      /* mips3 & xtlb in user mode */
  80 #define SR_SX           0x00000040      /* mips3 & xtlb in supervisor mode */
  81 #define SR_KX           0x00000080      /* xtlb in kernel mode */
  82
  83 /* interrupt mask bits */
  84 #define SR_SINT0        0x00000100      /* enable s/w interrupt 0 */
  85 #define SR_SINT1        0x00000200      /* enable s/w interrupt 1 */
  86 #define SR_HINT0        0x00000400      /* enable h/w interrupt 1 */
  87 #define SR_HINT1        0x00000800      /* enable h/w interrupt 2 */
  88 #define SR_HINT2        0x00001000      /* enable h/w interrupt 3 */
  89 #define SR_HINT3        0x00002000      /* enable h/w interrupt 4 */
  90 #define SR_HINT4        0x00004000      /* enable h/w interrupt 5 */
  91 #define SR_HINT5        0x00008000      /* enable h/w interrupt 6 */
  92
  93 /* alternative interrupt mask naming */
  94 #define SR_IM0          0x00000100
  95 #define SR_IM1          0x00000200
  96 #define SR_IM2          0x00000400
  97 #define SR_IM3          0x00000800
  98 #define SR_IM4          0x00001000
  99 #define SR_IM5          0x00002000
 100 #define SR_IM6          0x00004000
 101 #define SR_IM7          0x00008000
 102
 103 #define SR_IMASK        0x0000ff00
 104
 105 /* diagnostic field */
 106 #define SR_DE           0x00010000      /* disable cache/ecc errors */
 107 #define SR_CE           0x00020000      /* use ecc register */
 108 #define SR_CH           0x00040000      /* cache hit indicator */
 109 #define SR_SR           0x00100000      /* soft reset occurred */
 110 #define SR_TS           0x00200000      /* TLB shutdown */
 111 #define SR_BEV          0x00400000      /* boot exception vectors */
 112 #if #cpu(rm52xx)
 113 #define SR_IL           0x00800000      /* icache lock */
 114 #define SR_DL           0x01000000      /* dcache lock */
 115 #endif
 116
 117 #define SR_RE           0x02000000      /* reverse endian (user mode) */
 118 #define SR_FR           0x04000000      /* 64-bit fpu registers */
 119 #define SR_RP           0x08000000      /* reduce power */
 120
 121 #define SR_CU0          0x10000000      /* coprocessor 0 enable */
 122 #define SR_CU1          0x20000000      /* coprocessor 1 enable */
 123 #define SR_CU2          0x40000000      /* coprocessor 2 enable */
 124 #define SR_XX           0x80000000      /* Mips IV ISA enable */
 125
 126
 127 /*
 128  * R5000 Config Register
 129  */
 130 #define CFG_ECMASK      0x70000000      /* System Clock Ratio */
 131 #define CFG_ECSHIFT     28
 132 #define CFG_EPMASK      0x0f000000      /* Transmit data pattern */
 133 #define CFG_EPD         0x00000000      /* D */
 134 #define CFG_EPDDX       0x01000000      /* DDX */
 135 #define CFG_EPDDXX      0x02000000      /* DDXX */
 136 #define CFG_EPDXDX      0x03000000      /* DXDX */
 137 #define CFG_EPDDXXX     0x04000000      /* DDXXX */
 138 #define CFG_EPDDXXXX    0x05000000      /* DDXXXX */
 139 #define CFG_EPDXXDXX    0x06000000      /* DXXDXX */
 140 #define CFG_EPDDXXXXX   0x07000000      /* DDXXXXX */
 141 #define CFG_EPDXXXDXXX  0x08000000      /* DXXXDXXX */
 142 #define CFG_SSMASK      0x00300000      /* Secondary cache Size */
 143 #define CFG_SSSHIFT     20
 144 #define CFG_SS_512KB    0x00000000
 145 #define CFG_SS_1MB      0x00100000
 146 #define CFG_SS_2MB      0x00200000
 147 #define CFG_SS_NONE     0x00300000
 148 #define CFG_SC          0x00020000      /* Secondary cache absent */
 149 #define CFG_BE          0x00008000      /* Big Endian */
 150 #define CFG_SE          0x00001000      /* Secondary cache Enable */
 151 #define CFG_ICMASK      0x00000e00      /* Instruction cache size */
 152 #define CFG_ICSHIFT     9
 153 #define CFG_DCMASK      0x000001c0      /* Data cache size */
 154 #define CFG_DCSHIFT     6
 155 #define CFG_IB          0x00000020      /* Instruction cache block size */
 156 #define CFG_DB          0x00000010      /* Data cache block size */
 157 #define CFG_K0MASK      0x00000007      /* KSEG0 coherency algorithm */
 158
 159 /*
 160  * Primary cache mode
 161  */
 162 #define CFG_C_WTHRU_NOALLOC     0
 163 #define CFG_C_WTHRU_ALLOC       1
 164 #define CFG_C_UNCACHED          2
 165 #define CFG_C_NONCOHERENT       3
 166 #define CFG_C_WBACK             3
 167
 168 /*
 169  * Primary Cache TagLo
 170  */
 171 #define TAG_PTAG_MASK           0xffffff00      /* Primary Tag */
 172 #define TAG_PTAG_SHIFT          8
 173 #define TAG_PSTATE_MASK         0x000000c0      /* Primary Cache State */
 174 #define TAG_PSTATE_SHIFT        6
 175 #define TAG_ICDEC_MASK          0x0000003c
 176 #define TAG_ICDEC_SHIFT         2
 177 #define TAG_FIFO_MASK           0x00000002      /* Primary Tag Parity */
 178 #define TAG_FIFO_SHIFT          1
 179 #define TAG_PARITY_MASK         0x00000001      /* Primary Tag Parity */
 180 #define TAG_PARITY_SHIFT        0
 181
 182 #define PSTATE_INVAL            0
 183 #define PSTATE_VALID            3
 184
 185
 186 /*
 187  * Secondary Cache TagLo
 188  * (write through, so no dirty bits)
 189  */
 190 #define TAG_STAG_MASK           0xffff8000      /* Secondary Tag */
 191 #define TAG_STAG_SHIFT          15
 192 #define TAG_SSTATE_MASK         0x00001c00      /* Secondary Cache State */
 193 #define TAG_SSTATE_SHIFT        10
 194 #define TAG_VINDEX_MASK         0x00000380      /* Secondary Cache VIndex */
 195 #define TAG_VINDEX_SHIFT        7
 196 #define TAG_STAG_SIZE           19              /* Secondary Tag Width */
 197
 198 #define SSTATE_INVAL            0
 199 #define SSTATE_VALID            4
 200
 201 /*
 202  * CacheErr register
 203  */
 204 #define CACHEERR_ER             0x80000000
 205 #define CACHEERR_TYPE           0x80000000      /* reference type:
 206                                                    0=Instr, 1=Data */
 207 #define CACHEERR_EC             0x40000000
 208 #define CACHEERR_LEVEL          0x40000000      /* cache level:
 209                                                    0=Primary, 1=Secondary */
 210
 211 #define CACHEERR_ED             0x20000000
 212 #define CACHEERR_DATA           0x20000000      /* data field:
 213                                                    0=No error, 1=Error */
 214
 215 #define CACHEERR_ET             0x10000000
 216 #define CACHEERR_TAG            0x10000000      /* tag field:
 217                                                    0=No error, 1=Error */
 218 #define CACHEERR_ES             0x08000000
 219 #define CACHEERR_REQ            0x08000000      /* request type:
 220                                                    0=Internal, 1=External */
 221 #define CACHEERR_EE             0x04000000
 222 #define CACHEERR_BUS            0x04000000      /* error on bus:
 223                                                    0=No, 1=Yes */
 224 #define CACHEERR_EB             0x02000000
 225 #define CACHEERR_BOTH           0x02000000      /* Data & Instruction error:
 226                                                    0=No, 1=Yes */
 227 #define CACHEERR_SIDX_MASK      0x003ffff8      /* PADDR(21..3) */
 228 #define CACHEERR_SIDX_SHIFT              3
 229 #define CACHEERR_PIDX_MASK      0x00000007      /* VADDR(14..12) */
 230 #define CACHEERR_PIDX_SHIFT             12
 231
 232 /*
 233  * Cache operations
 234  */
 235 #define Index_Invalidate_I               0x0         /* 0       0 */
 236 #define Index_Writeback_Inv_D            0x1         /* 0       1 */
 237 #define Flash_Invalidate_S               0x3         /* 0       3 */
 238 #define Index_Load_Tag_I                 0x4         /* 1       0 */
 239 #define Index_Load_Tag_D                 0x5         /* 1       1 */
 240 #define Index_Load_Tag_S                 0x7         /* 1       3 */
 241 #define Index_Store_Tag_I                0x8         /* 2       0 */
 242 #define Index_Store_Tag_D                0x9         /* 2       1 */
 243 #define Index_Store_Tag_S                0xB         /* 2       3 */
 244 #define Create_Dirty_Exc_D               0xD         /* 3       1 */
 245 #define Hit_Invalidate_I                 0x10        /* 4       0 */
 246 #define Hit_Invalidate_D                 0x11        /* 4       1 */
 247 #define Fill_I                           0x14        /* 5       0 */
 248 #define Hit_Writeback_Inv_D              0x15        /* 5       1 */
 249 #define Page_Invalidate_S                0x17        /* 5       3 */
 250 #define Hit_Writeback_I                  0x18        /* 6       0 */
 251 #define Hit_Writeback_D                  0x19        /* 6       1 */
 252
 253
 254 /* R5000 EntryHi bits */
 255 #define TLBHI_VPN2MASK  0xffffe000
 256 #define TLBHI_VPN2SHIFT 13
 257 #define TLBHI_VPNMASK   0xfffff000
 258 #define TLBHI_VPNSHIFT  12
 259 #define TLBHI_PIDMASK   0x000000ff
 260 #define TLBHI_PIDSHIFT  0x00000000
 261
 262
 263 /* R5000 EntryLo bits */
 264 #define TLB_PFNMASK     0x3fffffc0
 265 #define TLB_PFNSHIFT    6
 266 #define TLB_FLAGS       0x0000003f
 267 #define TLB_CMASK       0x00000038
 268 #define TLB_CSHIFT      3
 269 #define TLB_D           0x00000004
 270 #define TLB_V           0x00000002
 271 #define TLB_G           0x00000001
 272
 273 #define TLB_WTHRU_NOALLOC       (CFG_C_WTHRU_NOALLOC    << TLB_CSHIFT)
 274 #define TLB_WTHRU_ALLOC         (CFG_C_WTHRU_ALLOC      << TLB_CSHIFT)
 275 #define TLB_UNCACHED            (CFG_C_UNCACHED         << TLB_CSHIFT)
 276 #define TLB_NONCOHERENT         (CFG_C_NONCOHERENT      << TLB_CSHIFT)
 277 #define TLB_WBACK               (CFG_C_WBACK            << TLB_CSHIFT)
 278
 279 /* R5000 Index bits */
 280 #define TLBIDX_MASK     0x3f
 281 #define TLBIDX_SHIFT    0
 282
 283 /* R5000 Random bits */
 284 #define TLBRAND_MASK    0x3f
 285 #define TLBRAND_SHIFT   0
 286
 287 #define NTLBID          48      /* total number of tlb entry pairs */
 288
 289 /* macros to constuct tlbhi and tlblo */
 290 #define mktlbhi(vpn,id)   ((((tlbhi_t)(vpn)>>1) << TLBHI_VPN2SHIFT) | \
 291                            ((id) << TLBHI_PIDSHIFT))
 292 #define mktlblo(pn,flags) (((tlblo_t)(pn) << TLB_PFNSHIFT) | (flags))
 293
 294 /* and destruct them */
 295 #define tlbhiVpn(hi)    ((hi) >> TLBHI_VPNSHIFT)
 296 #define tlbhiId(hi)     ((hi) & TLBHI_PIDMASK)
 297 #define tlbloPn(lo)     ((lo) >> TLB_PFNSHIFT)
 298 #define tlbloFlags(lo)  ((lo) & TLB_FLAGS)
 299
 300 #if #cpu(rm52xx)
 301 /* Watchpoint Register (not on all variants) */
 302 #define WATCHLO_PA      0xfffffff8
 303 #define WATCHLO_R       0x00000002
 304 #define WATCHLO_W       0x00000001
 305 #endif
 306
 307 #ifdef __ASSEMBLER__
 308 /*
 309  * R5000 Coprocessor 0 register numbers
 310  */
 311 #define C0_INDEX        $0
 312 #define C0_INX          $0
 313 #define C0_RANDOM       $1
 314 #define C0_RAND         $1
 315 #define C0_ENTRYLO0     $2
 316 #define C0_TLBLO0       $2
 317 #define C0_ENTRYLO1     $3
 318 #define C0_TLBLO1       $3
 319 #define C0_CONTEXT      $4
 320 #define C0_CTXT         $4
 321 #define C0_PAGEMASK     $5
 322 #define C0_WIRED        $6
 323 #define C0_BADVADDR     $8
 324 #define C0_VADDR        $8
 325 #define C0_COUNT        $9
 326 #define C0_ENTRYHI      $10
 327 #define C0_TLBHI        $10
 328 #define C0_COMPARE      $11
 329 #define C0_SR           $12
 330 #define C0_CAUSE        $13
 331 #define C0_CR           $13
 332 #define C0_EPC          $14
 333 #define C0_PRID         $15
 334 #define C0_CONFIG       $16
 335 #define C0_LLADDR       $17
 336 #if #cpu(rm52xx)
 337 #define C0_WATCHLO      $18
 338 #define C0_WATCHHI      $19
 339 #endif
 340 #define C0_ECC          $26
 341 #define C0_CACHEERR     $27
 342 #define C0_TAGLO        $28
 343 #define C0_TAGHI        $29
 344 #define C0_ERRPC        $30
 345
 346 $index          =       $0
 347 $random         =       $1
 348 $entrylo0       =       $2
 349 $entrylo1       =       $3
 350 $context        =       $4
 351 $pagemask       =       $5
 352 $wired          =       $6
 353 $vaddr          =       $8
 354 $count          =       $9
 355 $entryhi        =       $10
 356 $compare        =       $11
 357 $sr             =       $12
 358 $cr             =       $13
 359 $epc            =       $14
 360 $prid           =       $15
 361 $config         =       $16
 362 $lladdr         =       $17
 363 #if #cpu(rm52xx)
 364 $watchlo        =       $18
 365 $watchhi        =       $19
 366 #endif
 367 $ecc            =       $26
 368 $cacheerr       =       $27
 369 $taglo          =       $28
 370 $taghi          =       $29
 371 $errpc          =       $30
 372
 373 /*
 374  * R5000 virtual memory regions (SDE-MIPS only supports 32-bit addressing)
 375  */
 376 #define KSEG0_BASE      0x80000000
 377 #define KSEG1_BASE      0xa0000000
 378 #define KSEG2_BASE      0xc0000000
 379 #define KSEGS_BASE      0xc0000000
 380 #define KSEG3_BASE      0xe0000000
 381 #define RVEC_BASE       0xbfc00000      /* reset vector base */
 382
 383 #define KUSEG_SIZE      0x80000000
 384 #define KSEG0_SIZE      0x20000000
 385 #define KSEG1_SIZE      0x20000000
 386 #define KSEG2_SIZE      0x40000000
 387 #define KSEGS_SIZE      0x20000000
 388 #define KSEG3_SIZE      0x20000000
 389
 390 /*
 391  * Translate a kernel virtual address in KSEG0 or KSEG1 to a real
 392  * physical address and back.
 393  */
 394 #define KVA_TO_PA(v)    ((v) & 0x1fffffff)
 395 #define PA_TO_KVA0(pa)  ((pa) | 0x80000000)
 396 #define PA_TO_KVA1(pa)  ((pa) | 0xa0000000)
 397
 398 /* translate betwwen KSEG0 and KSEG1 virtual addresses */
 399 #define KVA0_TO_KVA1(v) ((v) | 0x20000000)
 400 #define KVA1_TO_KVA0(v) ((v) & ~0x20000000)
 401
 402 #else
 403
 404 /*
 405  * Standard types
 406  */
 407 typedef unsigned long           paddr_t;        /* a physical address */
 408 typedef unsigned long           vaddr_t;        /* a virtual address */
 409 typedef unsigned long           reg32_t;        /* a 32-bit register */
 410 typedef unsigned long long      reg64_t;        /* a 64-bit register */
 411 #if __mips >= 3
 412 typedef unsigned long long      reg_t;
 413 #else
 414 typedef unsigned long           reg_t;
 415 #endif
 416 #if __mips64
 417 typedef unsigned long long      tlbhi_t;        /* the tlbhi field */
 418 #else
 419 typedef unsigned long           tlbhi_t;        /* the tlbhi field */
 420 #endif
 421 typedef unsigned long           tlblo_t;        /* the tlblo field */
 422
 423 /*
 424  * R5000 Coprocessor 0 register numbers
 425  */
 426 #define C0_INDEX        0
 427 #define C0_INX          0
 428 #define C0_RANDOM       1
 429 #define C0_RAND         1
 430 #define C0_ENTRYLO0     2
 431 #define C0_TLBLO0       2
 432 #define C0_ENTRYLO1     3
 433 #define C0_TLBLO1       3
 434 #define C0_CONTEXT      4
 435 #define C0_CTXT         4
 436 #define C0_PAGEMASK     5
 437 #define C0_WIRED        6
 438 #define C0_BADVADDR     8
 439 #define C0_VADDR        8
 440 #define C0_COUNT        9
 441 #define C0_ENTRYHI      10
 442 #define C0_TLBHI        10
 443 #define C0_COMPARE      11
 444 #define C0_STATUS       12
 445 #define C0_SR           12
 446 #define C0_CAUSE        13
 447 #define C0_CR           13
 448 #define C0_EPC          14
 449 #define C0_PRID         15
 450 #define C0_CONFIG       16
 451 #define C0_LLADDR       17
 452 #if #cpu(rm52xx)
 453 #define C0_WATCHLO      18
 454 #define C0_WATCHHI      19
 455 #endif
 456 #define C0_ECC          26
 457 #define C0_CACHEERR     27
 458 #define C0_TAGLO        28
 459 #define C0_TAGHI        29
 460 #define C0_ERRPC        30
 461
 462 #define r5kc0_nop() \
 463   __asm__ __volatile ("%(nop%)")
 464
 465 #define r5k_sync() \
 466   __asm__ __volatile ("sync")
 467
 468 /*
 469  * Define generic macros for accessing the R3000 coprocessor 0 registers.
 470  * Most apart from "set" return the original register value.
 471  */
 472
 473 #define r5kc0_get(reg) \
 474 ({ \
 475   register reg32_t __r; \
 476   __asm__ __volatile ("mfc0 %0,$" #reg : "=r" (__r)); \
 477   __r; \
 478 })
 479
 480 #define r5kc0_set(reg, val) \
 481 ({ \
 482     register reg32_t __r = (val); \
 483     __asm__ __volatile ("%(mtc0 %0,$" #reg "; nop; nop; nop%)" : : "r" (__r) : "memory");\
 484     __r; \
 485 })
 486
 487 #define r5kc0_xch(reg, val) \
 488 ({ \
 489     register reg32_t __o, __n = (val); \
 490     __asm__ __volatile ("mfc0 %0,$" #reg : "=r" (__o)); \
 491     __asm__ __volatile ("%(mtc0 %0,$" #reg "; nop; nop; nop%)" : : "r" (__n) : "memory");\
 492     __o; \
 493 })
 494
 495
 496 #define r5kc0_bis(reg, val) \
 497 ({ \
 498     register reg32_t __o, __n; \
 499     __asm__ __volatile ("mfc0 %0,$" #reg : "=r" (__o)); \
 500     __n = __o | (val); \
 501     __asm__ __volatile ("%(mtc0 %0,$" #reg "; nop; nop; nop%)" : : "r" (__n) : "memory");\
 502     __o; \
 503 })
 504
 505
 506 #define r5kc0_bic(reg, val) \
 507 ({ \
 508     register reg32_t __o, __n; \
 509     __asm__ __volatile ("mfc0 %0,$" #reg : "=r" (__o)); \
 510     __n = __o &~ (val); \
 511     __asm__ __volatile ("%(mtc0 %0,$" #reg "; nop; nop; nop%)" : : "r" (__n) : "memory");\
 512     __o; \
 513 })
 514
 515
 516 /* R5000 Status register (NOTE they are NOT atomic operations) */
 517 #define r5k_getsr()             r5kc0_get(12)
 518 #define r5k_setsr(v)            r5kc0_set(12,v)
 519 #define r5k_xchsr(v)            r5kc0_xch(12,v)
 520 #define r5k_bicsr(v)            r5kc0_bic(12,v)
 521 #define r5k_bissr(v)            r5kc0_bis(12,v)
 522
 523 /* R5000 Cause register (NOTE they are NOT atomic operations) */
 524 #define r5k_getcr()             r5kc0_get(13)
 525 #define r5k_setcr(v)            r5kc0_set(13,v)
 526 #define r5k_xchcr(v)            r5kc0_xch(13,v)
 527 #define r5k_biccr(v)            r5kc0_bic(13,v)
 528 #define r5k_biscr(v)            r5kc0_bis(13,v)
 529
 530 /* R5000 Context register */
 531 #define r5k_getcontext()        r5kc0_get(4)
 532 #define r5k_setcontext(v)       r5kc0_set(4,v)
 533 #define r5k_xchcontext(v)       r5kc0_xch(4,v)
 534
 535 /* R5000 EntryHi register */
 536 #define r5k_getentryhi()        r5kc0_get(10)
 537 #define r5k_setentryhi(v)       r5kc0_set(10,v)
 538 #define r5k_xchentryhi(v)       r5kc0_xch(10,v)
 539
 540 /* R5000 PrID register */
 541 #define r5k_getprid()           r5kc0_get(15)
 542
 543 /* R5000 PageMask register */
 544 #define r5k_getpagemask()       r5kc0_get(5)
 545 #define r5k_setpagemask(v)      r5kc0_set(5,v)
 546 #define r5k_xchpagemask(v)      r5kc0_xch(5,v)
 547
 548 /* R5000 Wired register */
 549 #define r5k_getwired()          r5kc0_get(6)
 550 #define r5k_setwired(v)         r5kc0_set(6,v)
 551 #define r5k_xchwired(v)         r5kc0_xch(6,v)
 552
 553 /* R5000 Count register */
 554 #define r5k_getcount()          r5kc0_get(9)
 555 #define r5k_setcount(v)         r5kc0_set(9,v)
 556 #define r5k_xchcount(v)         r5kc0_xch(9,v)
 557
 558 /* R5000 Compare register*/
 559 #define r5k_getcompare()        r5kc0_get(11)
 560 #define r5k_setcompare(v)       r5kc0_set(11,v)
 561 #define r5k_xchcompare(v)       r5kc0_xch(11,v)
 562
 563 /* R5000 Config register */
 564 #define r5k_getconfig()         r5kc0_get(16)
 565 #define r5k_setconfig(v)        r5kc0_set(16,v)
 566 #define r5k_xchconfig(v)        r5kc0_xch(16,v)
 567 #define r5k_bicconfig(v)        r5kc0_bic(16,v)
 568 #define r5k_bisconfig(v)        r5kc0_bis(16,v)
 569
 570 #if #cpu(rm52xx)
 571 /* R5000 WatchLo register */
 572 #define r5k_getwatchlo()        r5kc0_get(18)
 573 #define r5k_setwatchlo(v)       r5kc0_set(18,v)
 574 #define r5k_xchwatchlo(v)       r5kc0_xch(18,v)
 575 #endif
 576
 577 /* R5000 ECC register */
 578 #define r5k_getecc()            r5kc0_get(26)
 579 #define r5k_setecc(x)           r5kc0_set(26, x)
 580
 581 /* R5000 TagLo register */
 582 #define r5k_gettaglo()          r5kc0_get(28)
 583 #define r5k_settaglo(x)         r5kc0_set(28, x)
 584
 585 /* Generic equivalents */
 586 #define mips_getsr()            r5k_getsr()
 587 #define mips_setsr(v)           r5k_setsr(v)
 588 #define mips_xchsr(v)           r5k_xchsr(v)
 589 #define mips_bicsr(v)           r5k_bicsr(v)
 590 #define mips_bissr(v)           r5k_bissr(v)
 591
 592 #define mips_getcr()            r5k_getcr()
 593 #define mips_setcr(v)           r5k_setcr(v)
 594 #define mips_xchcr(v)           r5k_xchcr(v)
 595 #define mips_biccr(v)           r5k_biccr(v)
 596 #define mips_biscr(v)           r5k_biscr(v)
 597
 598 #define mips_getprid()          r5k_getprid()
 599
 600 /*
 601  * R5000 cache functions
 602  */
 603 void r5k_hit_writeback_inv_dcache (vaddr_t va, size_t n);
 604
 605
 606 /*
 607  * R5000 TLB acccess
 608  */
 609 void    r5k_tlbri (tlbhi_t *, tlblo_t *, tlblo_t *, unsigned *, unsigned);
 610 void    r5k_tlbwi (tlbhi_t, tlblo_t, tlblo_t, unsigned, unsigned);
 611 void    r5k_tlbwr (tlbhi_t, tlblo_t, tlblo_t, unsigned);
 612 int     r5k_tlbrwr (tlbhi_t, tlblo_t, tlblo_t, unsigned);
 613 int     r5k_tlbprobe (tlbhi_t, tlblo_t *, tlblo_t *, unsigned *);
 614 void    r5k_tlbinval (tlbhi_t);
 615 void    r5k_tlbinvalall (void);
 616
 617 /*
 618  * R5000 virtual memory regions (SDE-MIPS only supports 32-bit addressing)
 619  */
 620 #define KUSEG_BASE      ((void *)0x00000000)
 621 #define KSEG0_BASE      ((void *)0x80000000)
 622 #define KSEG1_BASE      ((void *)0xa0000000)
 623 #define KSEG2_BASE      ((void *)0xc0000000)
 624 #define KSEGS_BASE      ((void *)0xc0000000)
 625 #define KSEG3_BASE      ((void *)0xe0000000)
 626 #define RVEC_BASE       ((void *)0xbfc00000)    /* reset vector base */
 627
 628 #define KUSEG_SIZE      0x80000000u
 629 #define KSEG0_SIZE      0x20000000u
 630 #define KSEG1_SIZE      0x20000000u
 631 #define KSEG2_SIZE      0x40000000u
 632 #define KSEGS_SIZE      0x20000000u
 633 #define KSEG3_SIZE      0x20000000u
 634
 635 /*
 636  * Translate a kernel virtual address in KSEG0 or KSEG1 to a real
 637  * physical address and back.
 638  */
 639 #define KVA_TO_PA(v)    ((paddr_t)(v) & 0x1fffffff)
 640 #define PA_TO_KVA0(pa)  ((void *) ((pa) | 0x80000000))
 641 #define PA_TO_KVA1(pa)  ((void *) ((pa) | 0xa0000000))
 642
 643 /* translate betwwen KSEG0 and KSEG1 virtual addresses */
 644 #define KVA0_TO_KVA1(v) ((void *) ((unsigned)(v) | 0x20000000))
 645 #define KVA1_TO_KVA0(v) ((void *) ((unsigned)(v) & ~0x20000000))
 646
 647 /* Test for KSEGS */
 648 #define IS_KVA(v)       ((int)(v) < 0)
 649 #define IS_KVA0(v)      (((unsigned)(v) >> 29) == 0x4)
 650 #define IS_KVA1(v)      (((unsigned)(v) >> 29) == 0x5)
 651 #define IS_KVA01(v)     (((unsigned)(v) >> 30) == 0x2)
 652 #define IS_KVAS(v)      (((unsigned)(v) >> 29) == 0x6)
 653 #define IS_KVA2(v)      (((unsigned)(v) >> 29) == 0x7)
 654 #define IS_UVA(v)       ((int)(v) >= 0)
 655
 656 /* convert register type to address and back */
 657 #define VA_TO_REG(v)    ((long)(v))             /* sign-extend 32->64 */
 658 #define REG_TO_VA(v)    ((void *)(long)(v))     /* truncate 64->32 */
 659
 660 /*
 661  * R5000 can set the page size on each TLB entry,
 662  * we present the common case here.
 663  */
 664 #define VMPGSIZE        4096
 665 #define VMPGMASK        (VMPGSIZE-1)
 666 #define VMPGSHIFT       12
 667
 668 /* virtual address to virtual page number and back */
 669 #define vaToVpn(va)     ((reg_t)(va) >> VMPGSHIFT)
 670 #define vpnToVa(vpn)    (void *)((vpn) << VMPGSHIFT)
 671
 672 /* physical address to physical page number and back */
 673 #define paToPn(pa)      ((pa) >> VMPGSHIFT)
 674 #define pnToPa(pn)      ((paddr_t)((pn) << VMPGSHIFT))
 675
 676 #endif /* !ASSEMBLER */
 677
 678 #ifdef __cplusplus
 679 }
 680 #endif
 681 #endif /* _R5KC0_H_ */