release/src-rt/cfe/cfe/arch/mips/board/bcm1250cpci/src/bcm1250cpci_pci.c

   1 /*  *********************************************************************
   2     *  Broadcom Common Firmware Environment (CFE)
   3     *
   4     *  Board device initialization              File: bcm1250cpci_pci.c
   5     *
   6     *  This is the part of the board support package for boards
   7     *  that support PCI. It describes the board-specific slots/devices
   8     *  and wiring thereof.
   9     *
  10     *********************************************************************
  11     *
  12     *  Copyright 2000,2001,2002,2003
  13     *  Broadcom Corporation. All rights reserved.
  14     *
  15     *  This software is furnished under license and may be used and
  16     *  copied only in accordance with the following terms and
  17     *  conditions.  Subject to these conditions, you may download,
  18     *  copy, install, use, modify and distribute modified or unmodified
  19     *  copies of this software in source and/or binary form.  No title
  20     *  or ownership is transferred hereby.
  21     *
  22     *  1) Any source code used, modified or distributed must reproduce
  23     *     and retain this copyright notice and list of conditions
  24     *     as they appear in the source file.
  25     *
  26     *  2) No right is granted to use any trade name, trademark, or
  27     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  28     *     name may not be used to endorse or promote products derived
  29     *     from this software without the prior written permission of
  30     *     Broadcom Corporation.
  31     *
  32     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  33     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  34     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  35     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  36     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  37     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  38     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  39     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  40     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  41     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  42     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  43     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  44     *     THE POSSIBILITY OF SUCH DAMAGE.
  45     ********************************************************************* */
  46
  47 #include "lib_types.h"
  48
  49 #include "sbmips.h"
  50 #include "sb1250_defs.h"
  51 #include "sb1250_regs.h"
  52 #include "sb1250_scd.h"
  53
  54 #include "pcireg.h"
  55 #include "pcivar.h"
  56
  57 /* PCI interrupt mapping on the BCM 1250 CPCI board:
  58    The mapping follows the standard for CPCI backplanes,
  59    with IDSEL 31:25 -> CPCI logical slots 2 to 8.
  60 */
  61
  62 extern int _pciverbose;
  63
  64 /* Return the base shift of a slot or device on the motherboard (bus 0).
  65    This is board specific, for the CPCI board only. */
  66 uint8_t
  67 pci_int_shift_0(pcitag_t tag)
  68 {
  69     int bus, device;
  70
  71     pci_break_tag(tag, NULL, &bus, &device, NULL);
  72
  73     if (bus == 0 && (device >= 14 && device <= 20))
  74 //      return ((21 - device) % 4);
  75         return ((device - 5) % 4);
  76     else
  77         return 0;
  78 }
  79
  80 /* Return the mapping of a CPCI device/function interrupt to an
  81    interrupt line. */
  82 uint8_t
  83 pci_int_map_0(pcitag_t tag)
  84 {
  85     pcireg_t data;
  86     int pin, bus, device;
  87     uint64_t syscfg;
  88         int bcm1250cpci_board_rev;
  89
  90     data = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG);
  91     pin = PCI_INTERRUPT_PIN(data);
  92     if (pin == 0) {
  93         /* No IRQ used. */
  94         return 0;
  95     }
  96     if (pin > 4) {
  97         if (_pciverbose >= 1)
  98             pci_tagprintf(tag, "pci_map_int: bad interrupt pin %d\n", pin);
  99         return 0;
 100     }
 101
 102     pci_break_tag(tag, NULL, &bus, &device, NULL);
 103
 104     /* Added code to take care of differences in Rev 0 and Rev 1
 105        board.  Rev 0 board has PCI connection only for INTA on the pci
 106        bus.  To overcome this problem, the CPLD was setup to input
 107        Interrupt B,C,and D and route them through A.  This will only
 108        allow for one interrupt for cards, but makes the cards slot
 109        independant.
 110
 111        Rev 1 board has the interrupt problems fixed and should just
 112        map them appropriately.  */
 113     syscfg = SBREADCSR(A_SCD_SYSTEM_CFG);
 114     bcm1250cpci_board_rev = G_SYS_CONFIG(syscfg) & 0x3;
 115     switch (bcm1250cpci_board_rev) {
 116         case 0:
 117             if (bus == 0 && (device >= 14 && device <= 20))
 118                 return (1);                     /* Always return Interrupt A */
 119             else
 120                 return 0;
 121             break;
 122
 123         default:
 124             if (bus == 0 && (device >= 14 && device <= 20))
 125                 return (((pin - 1) + pci_int_shift_0(tag)) % 4) + 1;
 126             else
 127                 return 0;
 128             break;
 129     }
 130
 131 }