release/src-rt/shared/siutils_priv.h

   1 /*
   2  * Include file private to the SOC Interconnect support files.
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: siutils_priv.h,v 1.17 2009-10-30 21:23:33 Exp $
  19  */
  20
  21 #ifndef _siutils_priv_h_
  22 #define _siutils_priv_h_
  23
  24 #ifdef BCMDBG_ERR
  25 #define SI_ERROR(args)  printf args
  26 #else
  27 #define SI_ERROR(args)
  28 #endif  /* BCMDBG_ERR */
  29
  30 #ifdef BCMDBG
  31 #define SI_MSG(args)    printf args
  32 #else
  33 #define SI_MSG(args)
  34 #endif  /* BCMDBG */
  35
  36 /* Define SI_VMSG to printf for verbose debugging, but don't check it in */
  37 #define SI_VMSG(args)
  38
  39 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
  40
  41
  42 typedef uint32 (*si_intrsoff_t)(void *intr_arg);
  43 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
  44 typedef bool (*si_intrsenabled_t)(void *intr_arg);
  45
  46 typedef struct gpioh_item {
  47         void                    *arg;
  48         bool                    level;
  49         gpio_handler_t          handler;
  50         uint32                  event;
  51         struct gpioh_item       *next;
  52 } gpioh_item_t;
  53
  54 /* misc si info needed by some of the routines */
  55 typedef struct si_info {
  56         struct si_pub pub;              /* back plane public state (must be first field) */
  57
  58         void    *osh;                   /* osl os handle */
  59         void    *sdh;                   /* bcmsdh handle */
  60
  61         uint    dev_coreid;             /* the core provides driver functions */
  62         void    *intr_arg;              /* interrupt callback function arg */
  63         si_intrsoff_t intrsoff_fn;      /* turns chip interrupts off */
  64         si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
  65         si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
  66
  67         void *pch;                      /* PCI/E core handle */
  68
  69         gpioh_item_t *gpioh_head;       /* GPIO event handlers list */
  70
  71         bool    memseg;                 /* flag to toggle MEM_SEG register */
  72
  73         char *vars;
  74         uint varsz;
  75
  76         void    *curmap;                /* current regs va */
  77         void    *regs[SI_MAXCORES];     /* other regs va */
  78
  79         uint    curidx;                 /* current core index */
  80         uint    numcores;               /* # discovered cores */
  81         uint    coreid[SI_MAXCORES];    /* id of each core */
  82         uint32  coresba[SI_MAXCORES];   /* backplane address of each core */
  83         void    *regs2[SI_MAXCORES];    /* va of each core second register set (usbh20) */
  84         uint32  coresba2[SI_MAXCORES];  /* address of each core second register set (usbh20) */
  85         uint32  coresba_size[SI_MAXCORES]; /* backplane address space size */
  86         uint32  coresba2_size[SI_MAXCORES]; /* second address space size */
  87
  88         void    *curwrap;               /* current wrapper va */
  89         void    *wrappers[SI_MAXCORES]; /* other cores wrapper va */
  90         uint32  wrapba[SI_MAXCORES];    /* address of controlling wrapper */
  91
  92         uint32  cia[SI_MAXCORES];       /* erom cia entry for each core */
  93         uint32  cib[SI_MAXCORES];       /* erom cia entry for each core */
  94         uint32  oob_router;             /* oob router registers for axi */
  95 } si_info_t;
  96
  97 #define SI_INFO(sih)    (si_info_t *)(uintptr)sih
  98
  99 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
 100                 ISALIGNED((x), SI_CORE_SIZE))
 101 #define GOODREGS(regs)  ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
 102 #define BADCOREADDR     0
 103 #define GOODIDX(idx)    (((uint)idx) < SI_MAXCORES)
 104 #define NOREV           -1              /* Invalid rev */
 105
 106 #define PCI(si)         ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 107                          ((si)->pub.buscoretype == PCI_CORE_ID))
 108 #define PCIE(si)        ((BUSTYPE((si)->pub.bustype) == PCI_BUS) &&     \
 109                          ((si)->pub.buscoretype == PCIE_CORE_ID))
 110 #define PCMCIA(si)      ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
 111
 112 /* Newer chips can access PCI/PCIE and CC core without requiring to change
 113  * PCI BAR0 WIN
 114  */
 115 #define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
 116                      (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
 117
 118 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
 119 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
 120
 121 /*
 122  * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
 123  * after core switching to avoid invalid register accesss inside ISR.
 124  */
 125 #define INTR_OFF(si, intr_val) \
 126         if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {      \
 127                 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
 128 #define INTR_RESTORE(si, intr_val) \
 129         if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) {  \
 130                 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
 131
 132 /* dynamic clock control defines */
 133 #define LPOMINFREQ              25000           /* low power oscillator min */
 134 #define LPOMAXFREQ              43000           /* low power oscillator max */
 135 #define XTALMINFREQ             19800000        /* 20 MHz - 1% */
 136 #define XTALMAXFREQ             20200000        /* 20 MHz + 1% */
 137 #define PCIMINFREQ              25000000        /* 25 MHz */
 138 #define PCIMAXFREQ              34000000        /* 33 MHz + fudge */
 139
 140 #define ILP_DIV_5MHZ            0               /* ILP = 5 MHz */
 141 #define ILP_DIV_1MHZ            4               /* ILP = 1 MHz */
 142
 143 #define PCI_FORCEHT(si) \
 144         (((PCIE(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
 145         ((PCI(si) || PCIE(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \
 146         (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID)))
 147
 148 /* GPIO Based LED powersave defines */
 149 #define DEFAULT_GPIO_ONTIME     10              /* Default: 10% on */
 150 #define DEFAULT_GPIO_OFFTIME    90              /* Default: 10% on */
 151
 152 #ifndef DEFAULT_GPIOTIMERVAL
 153 #define DEFAULT_GPIOTIMERVAL  ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
 154 #endif
 155
 156 /* Silicon Backplane externs */
 157 extern void sb_scan(si_t *sih, void *regs, uint devid);
 158 extern uint sb_coreid(si_t *sih);
 159 extern uint sb_intflag(si_t *sih);
 160 extern uint sb_flag(si_t *sih);
 161 extern void sb_setint(si_t *sih, int siflag);
 162 extern uint sb_corevendor(si_t *sih);
 163 extern uint sb_corerev(si_t *sih);
 164 extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 165 extern bool sb_iscoreup(si_t *sih);
 166 extern void *sb_setcoreidx(si_t *sih, uint coreidx);
 167 extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val);
 168 extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 169 extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val);
 170 extern void sb_commit(si_t *sih);
 171 extern uint32 sb_base(uint32 admatch);
 172 extern uint32 sb_size(uint32 admatch);
 173 extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 174 extern void sb_core_disable(si_t *sih, uint32 bits);
 175 extern uint32 sb_addrspace(si_t *sih, uint asidx);
 176 extern uint32 sb_addrspacesize(si_t *sih, uint asidx);
 177 extern int sb_numaddrspaces(si_t *sih);
 178
 179 extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx);
 180
 181 extern bool sb_taclear(si_t *sih, bool details);
 182
 183 #ifdef BCMDBG
 184 extern void sb_view(si_t *sih, bool verbose);
 185 extern void sb_viewall(si_t *sih, bool verbose);
 186 #endif
 187 #if defined(BCMDBG_DUMP)
 188 extern void sb_dump(si_t *sih, struct bcmstrbuf *b);
 189 #endif
 190 #if defined(BCMDBG) || defined(BCMDBG_DUMP)
 191 extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b);
 192 #endif
 193
 194 /* Wake-on-wireless-LAN (WOWL) */
 195 extern bool sb_pci_pmecap(si_t *sih);
 196 struct osl_info;
 197 extern bool sb_pci_fastpmecap(struct osl_info *osh);
 198 extern bool sb_pci_pmeclr(si_t *sih);
 199 extern void sb_pci_pmeen(si_t *sih);
 200 extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset);
 201
 202 /* AMBA Interconnect exported externs */
 203 extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 204                        void *sdh, char **vars, uint *varsz);
 205 extern si_t *ai_kattach(osl_t *osh);
 206 extern void ai_scan(si_t *sih, void *regs, uint devid);
 207
 208 extern uint ai_flag(si_t *sih);
 209 extern void ai_setint(si_t *sih, int siflag);
 210 extern uint ai_coreidx(si_t *sih);
 211 extern uint ai_corevendor(si_t *sih);
 212 extern uint ai_corerev(si_t *sih);
 213 extern bool ai_iscoreup(si_t *sih);
 214 extern void *ai_setcoreidx(si_t *sih, uint coreidx);
 215 extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val);
 216 extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 217 extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val);
 218 extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 219 extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 220 extern void ai_core_disable(si_t *sih, uint32 bits);
 221 extern int ai_numaddrspaces(si_t *sih);
 222 extern uint32 ai_addrspace(si_t *sih, uint asidx);
 223 extern uint32 ai_addrspacesize(si_t *sih, uint asidx);
 224 extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
 225 extern void ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val);
 226
 227 #ifdef BCMDBG
 228 extern void ai_view(si_t *sih, bool verbose);
 229 #endif
 230 #if defined(BCMDBG) || defined(BCMDBG_DUMP)
 231 extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b);
 232 #endif
 233
 234 #ifdef SI_ENUM_BASE_VARIABLE
 235 extern void si_enum_base_init(si_t *sih, uint bustype);
 236 #endif /* SI_ENUM_BASE_VARIABLE */
 237
 238 #define ub_scan(a, b, c) do {} while (0)
 239 #define ub_flag(a) (0)
 240 #define ub_setint(a, b) do {} while (0)
 241 #define ub_coreidx(a) (0)
 242 #define ub_corevendor(a) (0)
 243 #define ub_corerev(a) (0)
 244 #define ub_iscoreup(a) (0)
 245 #define ub_setcoreidx(a, b) (0)
 246 #define ub_core_cflags(a, b, c) (0)
 247 #define ub_core_cflags_wo(a, b, c) do {} while (0)
 248 #define ub_core_sflags(a, b, c) (0)
 249 #define ub_corereg(a, b, c, d, e) (0)
 250 #define ub_core_reset(a, b, c) do {} while (0)
 251 #define ub_core_disable(a, b) do {} while (0)
 252 #define ub_numaddrspaces(a) (0)
 253 #define ub_addrspace(a, b)  (0)
 254 #define ub_addrspacesize(a, b) (0)
 255 #define ub_view(a, b) do {} while (0)
 256 #define ub_dumpregs(a, b) do {} while (0)
 257
 258 #endif  /* _siutils_priv_h_ */