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Resync with broadcom drivers 5.100.138.20 and utilities.
[tomato.git] / release / src-rt / shared / aiutils.c
blob059370c6fe27ce94ef5edeca250cce26b45f68ae
1 /*
2 * Misc utility routines for accessing chip-specific features
3 * of the SiliconBackplane-based Broadcom chips.
4 *
5 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 *
19 * $Id: aiutils.c,v 1.27.2.5 2011-01-26 18:24:11 Exp $
20 */
21
22 #include <typedefs.h>
23 #include <bcmdefs.h>
24 #include <osl.h>
25 #include <bcmutils.h>
26 #include <siutils.h>
27 #include <hndsoc.h>
28 #include <sbchipc.h>
29 #include <pcicfg.h>
30
31 #include "siutils_priv.h"
32
33 #include <bcmdevs.h>
34
35 #define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
36 (CHIPREV(sih->chiprev) == 0) && \
37 (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
38
39 #define BCM5357_DMP() (((CHIPID(sih->chip) == BCM5357_CHIP_ID) || \
40 (CHIPID(sih->chip) == BCM4749_CHIP_ID)) && \
41 (sih->chippkg == BCM5357_PKG_ID) && \
42 (sii->coreid[sii->curidx] == USB20H_CORE_ID))
43
44 /* EROM parsing */
45
46 static uint32
47 get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match)
48 {
49 uint32 ent;
50 uint inv = 0, nom = 0;
51
52 while (TRUE) {
53 ent = R_REG(si_osh(sih), *eromptr);
54 (*eromptr)++;
55
56 if (mask == 0)
57 break;
58
59 if ((ent & ER_VALID) == 0) {
60 inv++;
61 continue;
62 }
63
64 if (ent == (ER_END | ER_VALID))
65 break;
66
67 if ((ent & mask) == match)
68 break;
69
70 nom++;
71 }
72
73 SI_VMSG(("%s: Returning ent 0x%08x\n", __FUNCTION__, ent));
74 if (inv + nom) {
75 SI_VMSG((" after %d invalid and %d non-matching entries\n", inv, nom));
76 }
77 return ent;
78 }
79
80 static uint32
81 get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh,
82 uint32 *sizel, uint32 *sizeh)
83 {
84 uint32 asd, sz, szd;
85
86 asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
87 if (((asd & ER_TAG1) != ER_ADD) ||
88 (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
89 ((asd & AD_ST_MASK) != st)) {
90 /* This is not what we want, "push" it back */
91 (*eromptr)--;
92 return 0;
93 }
94 *addrl = asd & AD_ADDR_MASK;
95 if (asd & AD_AG32)
96 *addrh = get_erom_ent(sih, eromptr, 0, 0);
97 else
98 *addrh = 0;
99 *sizeh = 0;
100 sz = asd & AD_SZ_MASK;
101 if (sz == AD_SZ_SZD) {
102 szd = get_erom_ent(sih, eromptr, 0, 0);
103 *sizel = szd & SD_SZ_MASK;
104 if (szd & SD_SG32)
105 *sizeh = get_erom_ent(sih, eromptr, 0, 0);
106 } else
107 *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
108
109 SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
110 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
111
112 return asd;
113 }
114
115 static void
116 ai_hwfixup(si_info_t *sii)
117 {
118 #ifdef _CFE_
119 /* Fixup the interrupts in 4716 for i2s core so that ai_flag
120 * works without having to look at the core sinking the
121 * interrupt. We should have done this as the hardware default.
122 *
123 * Future chips should allocate interrupt lines in order (meaning
124 * no line should be skipped), without regard for core index.
125 */
126 if (BUSTYPE(sii->pub.bustype) == SI_BUS &&
127 ((CHIPID(sii->pub.chip) == BCM4716_CHIP_ID) ||
128 (CHIPID(sii->pub.chip) == BCM4748_CHIP_ID))) {
129 aidmp_t *i2s, *pcie, *cpu;
130
131 ASSERT(sii->coreid[3] == MIPS74K_CORE_ID);
132 cpu = REG_MAP(sii->wrapba[3], SI_CORE_SIZE);
133 ASSERT(sii->coreid[5] == PCIE_CORE_ID);
134 pcie = REG_MAP(sii->wrapba[5], SI_CORE_SIZE);
135 ASSERT(sii->coreid[8] == I2S_CORE_ID);
136 i2s = REG_MAP(sii->wrapba[8], SI_CORE_SIZE);
137 if ((R_REG(sii->osh, &cpu->oobselina74) != 0x08060504) ||
138 (R_REG(sii->osh, &pcie->oobselina74) != 0x08060504) ||
139 (R_REG(sii->osh, &i2s->oobselouta30) != 0x88)) {
140 SI_VMSG(("Unexpected oob values, not fixing i2s interrupt\n"));
141 } else {
142 /* Move i2s interrupt to oob line 7 instead of 8 */
143 W_REG(sii->osh, &cpu->oobselina74, 0x07060504);
144 W_REG(sii->osh, &pcie->oobselina74, 0x07060504);
145 W_REG(sii->osh, &i2s->oobselouta30, 0x87);
146 SI_VMSG(("Changed i2s interrupt to use oob line 7 instead of 8\n"));
147 }
148 }
149 #endif /* _CFE_ */
150 }
151
152 struct _corerev_entry {
153 uint corerev;
154 uint corerev_alias;
155 };
156 static struct _corerev_entry bcm4706_corerev_cc[] = {
157 { 0x1f, CC_4706B0_CORE_REV },
158 { 0, 0 }
159 };
160 static struct _corerev_entry bcm4706_corerev_socsram[] = {
161 { 0x05, SOCRAM_4706B0_CORE_REV },
162 { 0, 0 }
163 };
164 static struct _corerev_entry bcm4706_corerev_gmac[] = {
165 { 0x00, GMAC_4706B0_CORE_REV },
166 { 0, 0 }
167 };
168
169 struct _coreid_entry {
170 uint coreid;
171 uint coreid_alias;
172 };
173 static struct _coreid_entry bcm4706_coreid_table[] = {
174 { CC_4706_CORE_ID, CC_CORE_ID },
175 { SOCRAM_4706_CORE_ID, SOCRAM_CORE_ID },
176 { GMAC_4706_CORE_ID, GMAC_CORE_ID },
177 { 0, 0 }
178 };
179
180 static uint
181 remap_coreid(si_t *sih, uint coreid)
182 {
183 struct _coreid_entry *coreid_table = NULL;
184
185 if (CHIPID(sih->chip) == BCM4706_CHIP_ID)
186 coreid_table = &bcm4706_coreid_table[0];
187
188 if (coreid_table != NULL) {
189 uint i;
190
191 for (i = 0; coreid_table[i].coreid; i++)
192 if (coreid_table[i].coreid == coreid)
193 return coreid_table[i].coreid_alias;
194 }
195
196 return coreid;
197 }
198
199 static uint
200 remap_corerev(si_t *sih, uint corerev)
201 {
202 if (CHIPID(sih->chip) == BCM4706_CHIP_ID) {
203 si_info_t *sii = SI_INFO(sih);
204 uint i, coreid = sii->coreid[sii->curidx];
205 struct _corerev_entry *corerev_table = NULL;
206
207 if (coreid == CC_CORE_ID)
208 corerev_table = bcm4706_corerev_cc;
209 else if (coreid == GMAC_CORE_ID)
210 corerev_table = bcm4706_corerev_gmac;
211 else if (coreid == SOCRAM_CORE_ID)
212 corerev_table = bcm4706_corerev_socsram;
213 if (corerev_table != NULL) {
214 for (i = 0; corerev_table[i].corerev_alias; i++)
215 if (corerev_table[i].corerev == corerev)
216 return corerev_table[i].corerev_alias;
217 }
218 }
219
220 return corerev;
221 }
222
223 /* parse the enumeration rom to identify all cores */
224 void
225 BCMATTACHFN(ai_scan)(si_t *sih, void *regs, uint devid)
226 {
227 si_info_t *sii = SI_INFO(sih);
228 chipcregs_t *cc = (chipcregs_t *)regs;
229 uint32 erombase, *eromptr, *eromlim;
230
231 erombase = R_REG(sii->osh, &cc->eromptr);
232
233 switch (BUSTYPE(sih->bustype)) {
234 case SI_BUS:
235 eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
236 break;
237
238 case PCI_BUS:
239 /* Set wrappers address */
240 sii->curwrap = (void *)((uintptr)regs + SI_CORE_SIZE);
241
242 /* Now point the window at the erom */
243 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
244 eromptr = regs;
245 break;
246
247 #ifdef BCMJTAG
248 case JTAG_BUS:
249 eromptr = (uint32 *)(uintptr)erombase;
250 break;
251 #endif /* BCMJTAG */
252
253 case PCMCIA_BUS:
254 default:
255 SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n", sih->bustype));
256 ASSERT(0);
257 return;
258 }
259 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
260
261 SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n",
262 regs, erombase, eromptr, eromlim));
263 while (eromptr < eromlim) {
264 uint32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
265 uint32 mpd, asd, addrl, addrh, sizel, sizeh;
266 uint32 *base;
267 uint i, j, idx;
268 bool br;
269
270 br = FALSE;
271
272 /* Grok a component */
273 cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
274 if (cia == (ER_END | ER_VALID)) {
275 SI_VMSG(("Found END of erom after %d cores\n", sii->numcores));
276 ai_hwfixup(sii);
277 return;
278 }
279 base = eromptr - 1;
280 cib = get_erom_ent(sih, &eromptr, 0, 0);
281
282 if ((cib & ER_TAG) != ER_CI) {
283 SI_ERROR(("CIA not followed by CIB\n"));
284 goto error;
285 }
286
287 cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
288 mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
289 crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
290 nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
291 nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
292 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
293 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
294
295 SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, "
296 "nsw = %d, nmp = %d & nsp = %d\n",
297 mfg, cid, crev, base, nmw, nsw, nmp, nsp));
298
299 if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
300 continue;
301 if ((nmw + nsw == 0)) {
302 /* A component which is not a core */
303 if (cid == OOB_ROUTER_CORE_ID) {
304 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
305 &addrl, &addrh, &sizel, &sizeh);
306 if (asd != 0) {
307 sii->oob_router = addrl;
308 }
309 }
310 if (cid != GMAC_COMMON_4706_CORE_ID)
311 continue;
312 }
313
314 idx = sii->numcores;
315 /* sii->eromptr[idx] = base; */
316 sii->cia[idx] = cia;
317 sii->cib[idx] = cib;
318 sii->coreid[idx] = remap_coreid(sih, cid);
319
320 for (i = 0; i < nmp; i++) {
321 mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
322 if ((mpd & ER_TAG) != ER_MP) {
323 SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
324 goto error;
325 }
326 SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
327 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
328 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
329 }
330
331 /* First Slave Address Descriptor should be port 0:
332 * the main register space for the core
333 */
334 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
335 if (asd == 0) {
336 /* Try again to see if it is a bridge */
337 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
338 &sizel, &sizeh);
339 if (asd != 0)
340 br = TRUE;
341 else
342 if ((addrh != 0) || (sizeh != 0) || (sizel != SI_CORE_SIZE)) {
343 SI_ERROR(("First Slave ASD for core 0x%04x malformed "
344 "(0x%08x)\n", cid, asd));
345 goto error;
346 }
347 }
348 sii->coresba[idx] = addrl;
349 sii->coresba_size[idx] = sizel;
350 /* Get any more ASDs in port 0 */
351 j = 1;
352 do {
353 asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
354 &sizel, &sizeh);
355 if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
356 sii->coresba2[idx] = addrl;
357 sii->coresba2_size[idx] = sizel;
358 }
359 j++;
360 } while (asd != 0);
361
362 /* Go through the ASDs for other slave ports */
363 for (i = 1; i < nsp; i++) {
364 j = 0;
365 do {
366 asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
367 &sizel, &sizeh);
368
369 if (asd == 0)
370 break;
371 j++;
372 } while (1);
373 if (j == 0) {
374 SI_ERROR((" SP %d has no address descriptors\n", i));
375 goto error;
376 }
377 }
378
379 /* Now get master wrappers */
380 for (i = 0; i < nmw; i++) {
381 asd = get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl, &addrh,
382 &sizel, &sizeh);
383 if (asd == 0) {
384 SI_ERROR(("Missing descriptor for MW %d\n", i));
385 goto error;
386 }
387 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
388 SI_ERROR(("Master wrapper %d is not 4KB\n", i));
389 goto error;
390 }
391 if (i == 0)
392 sii->wrapba[idx] = addrl;
393 }
394
395 /* And finally slave wrappers */
396 for (i = 0; i < nsw; i++) {
397 uint fwp = (nsp == 1) ? 0 : 1;
398 asd = get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP, &addrl, &addrh,
399 &sizel, &sizeh);
400 if (asd == 0) {
401 SI_ERROR(("Missing descriptor for SW %d\n", i));
402 goto error;
403 }
404 if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
405 SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
406 goto error;
407 }
408 if ((nmw == 0) && (i == 0))
409 sii->wrapba[idx] = addrl;
410 }
411
412 /* Don't record bridges */
413 if (br)
414 continue;
415
416 /* Done with core */
417 sii->numcores++;
418 }
419
420 SI_ERROR(("Reached end of erom without finding END"));
421
422 error:
423 sii->numcores = 0;
424 return;
425 }
426
427 /* This function changes the logical "focus" to the indicated core.
428 * Return the current core's virtual address.
429 */
430 void *
431 ai_setcoreidx(si_t *sih, uint coreidx)
432 {
433 si_info_t *sii = SI_INFO(sih);
434 uint32 addr = sii->coresba[coreidx];
435 uint32 wrap = sii->wrapba[coreidx];
436 void *regs;
437
438 if (coreidx >= sii->numcores)
439 return (NULL);
440
441 /*
442 * If the user has provided an interrupt mask enabled function,
443 * then assert interrupts are disabled before switching the core.
444 */
445 ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
446
447 switch (BUSTYPE(sih->bustype)) {
448 case SI_BUS:
449 /* map new one */
450 if (!sii->regs[coreidx]) {
451 sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
452 ASSERT(GOODREGS(sii->regs[coreidx]));
453 }
454 sii->curmap = regs = sii->regs[coreidx];
455 if (!sii->wrappers[coreidx]) {
456 sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
457 ASSERT(GOODREGS(sii->wrappers[coreidx]));
458 }
459 sii->curwrap = sii->wrappers[coreidx];
460 break;
461
462 case PCI_BUS:
463 /* point bar0 window */
464 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
465 regs = sii->curmap;
466 /* point bar0 2nd 4KB window */
467 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
468 break;
469
470 #ifdef BCMJTAG
471 case JTAG_BUS:
472 sii->curmap = regs = (void *)((uintptr)addr);
473 sii->curwrap = (void *)((uintptr)wrap);
474 break;
475 #endif /* BCMJTAG */
476
477 case PCMCIA_BUS:
478 default:
479 ASSERT(0);
480 regs = NULL;
481 break;
482 }
483
484 sii->curmap = regs;
485 sii->curidx = coreidx;
486
487 return regs;
488 }
489
490 void
491 ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size)
492 {
493 si_info_t *sii = SI_INFO(sih);
494 chipcregs_t *cc = NULL;
495 uint32 erombase, *eromptr, *eromlim;
496 uint i, j, cidx;
497 uint32 cia, cib, nmp, nsp;
498 uint32 asd, addrl, addrh, sizel, sizeh;
499
500 for (i = 0; i < sii->numcores; i++) {
501 if (sii->coreid[i] == CC_CORE_ID) {
502 cc = (chipcregs_t *)sii->regs[i];
503 break;
504 }
505 }
506 if (cc == NULL)
507 goto error;
508
509 erombase = R_REG(sii->osh, &cc->eromptr);
510 eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE);
511 eromlim = eromptr + (ER_REMAPCONTROL / sizeof(uint32));
512
513 cidx = sii->curidx;
514 cia = sii->cia[cidx];
515 cib = sii->cib[cidx];
516
517 nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
518 nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
519
520 /* scan for cores */
521 while (eromptr < eromlim) {
522 if ((get_erom_ent(sih, &eromptr, ER_TAG, ER_CI) == cia) &&
523 (get_erom_ent(sih, &eromptr, 0, 0) == cib)) {
524 break;
525 }
526 }
527
528 /* skip master ports */
529 for (i = 0; i < nmp; i++)
530 get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
531
532 /* Skip ASDs in port 0 */
533 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh, &sizel, &sizeh);
534 if (asd == 0) {
535 /* Try again to see if it is a bridge */
536 asd = get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl, &addrh,
537 &sizel, &sizeh);
538 }
539
540 j = 1;
541 do {
542 asd = get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl, &addrh,
543 &sizel, &sizeh);
544 j++;
545 } while (asd != 0);
546
547 /* Go through the ASDs for other slave ports */
548 for (i = 1; i < nsp; i++) {
549 j = 0;
550 do {
551 asd = get_asd(sih, &eromptr, i, j, AD_ST_SLAVE, &addrl, &addrh,
552 &sizel, &sizeh);
553 if (asd == 0)
554 break;
555
556 if (!asidx--) {
557 *addr = addrl;
558 *size = sizel;
559 return;
560 }
561 j++;
562 } while (1);
563
564 if (j == 0) {
565 SI_ERROR((" SP %d has no address descriptors\n", i));
566 break;
567 }
568 }
569
570 error:
571 *size = 0;
572 return;
573 }
574
575 /* Return the number of address spaces in current core */
576 int
577 ai_numaddrspaces(si_t *sih)
578 {
579 return 2;
580 }
581
582 /* Return the address of the nth address space in the current core */
583 uint32
584 ai_addrspace(si_t *sih, uint asidx)
585 {
586 si_info_t *sii;
587 uint cidx;
588
589 sii = SI_INFO(sih);
590 cidx = sii->curidx;
591
592 if (asidx == 0)
593 return sii->coresba[cidx];
594 else if (asidx == 1)
595 return sii->coresba2[cidx];
596 else {
597 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
598 __FUNCTION__, asidx));
599 return 0;
600 }
601 }
602
603 /* Return the size of the nth address space in the current core */
604 uint32
605 ai_addrspacesize(si_t *sih, uint asidx)
606 {
607 si_info_t *sii;
608 uint cidx;
609
610 sii = SI_INFO(sih);
611 cidx = sii->curidx;
612
613 if (asidx == 0)
614 return sii->coresba_size[cidx];
615 else if (asidx == 1)
616 return sii->coresba2_size[cidx];
617 else {
618 SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n",
619 __FUNCTION__, asidx));
620 return 0;
621 }
622 }
623
624 uint
625 ai_flag(si_t *sih)
626 {
627 si_info_t *sii;
628 aidmp_t *ai;
629
630 sii = SI_INFO(sih);
631 if (BCM47162_DMP()) {
632 SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __FUNCTION__));
633 return sii->curidx;
634 }
635 if (BCM5357_DMP()) {
636 SI_ERROR(("%s: Attempting to read USB20H DMP registers on 5357b0\n", __FUNCTION__));
637 return sii->curidx;
638 }
639 ai = sii->curwrap;
640
641 return (R_REG(sii->osh, &ai->oobselouta30) & 0x1f);
642 }
643
644 void
645 ai_setint(si_t *sih, int siflag)
646 {
647 }
648
649 void
650 ai_write_wrap_reg(si_t *sih, uint32 offset, uint32 val)
651 {
652 si_info_t *sii = SI_INFO(sih);
653 uint32 *w = (uint32 *) sii->curwrap;
654 W_REG(sii->osh, w+(offset/4), val);
655 return;
656 }
657
658 uint
659 ai_corevendor(si_t *sih)
660 {
661 si_info_t *sii;
662 uint32 cia;
663
664 sii = SI_INFO(sih);
665 cia = sii->cia[sii->curidx];
666 return ((cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT);
667 }
668
669 uint
670 ai_corerev(si_t *sih)
671 {
672 si_info_t *sii;
673 uint32 cib;
674
675 sii = SI_INFO(sih);
676 cib = sii->cib[sii->curidx];
677 return remap_corerev(sih, (cib & CIB_REV_MASK) >> CIB_REV_SHIFT);
678 }
679
680 bool
681 ai_iscoreup(si_t *sih)
682 {
683 si_info_t *sii;
684 aidmp_t *ai;
685
686 sii = SI_INFO(sih);
687 ai = sii->curwrap;
688
689 return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) == SICF_CLOCK_EN) &&
690 ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
691 }
692
693 /*
694 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
695 * switch back to the original core, and return the new value.
696 *
697 * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
698 *
699 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
700 * and (on newer pci cores) chipcommon registers.
701 */
702 uint
703 ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
704 {
705 uint origidx = 0;
706 uint32 *r = NULL;
707 uint w;
708 uint intr_val = 0;
709 bool fast = FALSE;
710 si_info_t *sii;
711
712 sii = SI_INFO(sih);
713
714 ASSERT(GOODIDX(coreidx));
715 ASSERT(regoff < SI_CORE_SIZE);
716 ASSERT((val & ~mask) == 0);
717
718 if (coreidx >= SI_MAXCORES)
719 return 0;
720
721 if (BUSTYPE(sih->bustype) == SI_BUS) {
722 /* If internal bus, we can always get at everything */
723 fast = TRUE;
724 /* map if does not exist */
725 if (!sii->regs[coreidx]) {
726 sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
727 SI_CORE_SIZE);
728 ASSERT(GOODREGS(sii->regs[coreidx]));
729 }
730 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
731 } else if (BUSTYPE(sih->bustype) == PCI_BUS) {
732 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
733
734 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
735 /* Chipc registers are mapped at 12KB */
736
737 fast = TRUE;
738 r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
739 } else if (sii->pub.buscoreidx == coreidx) {
740 /* pci registers are at either in the last 2KB of an 8KB window
741 * or, in pcie and pci rev 13 at 8KB
742 */
743 fast = TRUE;
744 if (SI_FAST(sii))
745 r = (uint32 *)((char *)sii->curmap +
746 PCI_16KB0_PCIREGS_OFFSET + regoff);
747 else
748 r = (uint32 *)((char *)sii->curmap +
749 ((regoff >= SBCONFIGOFF) ?
750 PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
751 regoff);
752 }
753 }
754
755 if (!fast) {
756 INTR_OFF(sii, intr_val);
757
758 /* save current core index */
759 origidx = si_coreidx(&sii->pub);
760
761 /* switch core */
762 r = (uint32*) ((uchar*) ai_setcoreidx(&sii->pub, coreidx) + regoff);
763 }
764 ASSERT(r != NULL);
765
766 /* mask and set */
767 if (mask || val) {
768 w = (R_REG(sii->osh, r) & ~mask) | val;
769 W_REG(sii->osh, r, w);
770 }
771
772 /* readback */
773 w = R_REG(sii->osh, r);
774
775 if (!fast) {
776 /* restore core index */
777 if (origidx != coreidx)
778 ai_setcoreidx(&sii->pub, origidx);
779
780 INTR_RESTORE(sii, intr_val);
781 }
782
783 return (w);
784 }
785
786 void
787 ai_core_disable(si_t *sih, uint32 bits)
788 {
789 si_info_t *sii;
790 volatile uint32 dummy;
791 aidmp_t *ai;
792
793 sii = SI_INFO(sih);
794
795 ASSERT(GOODREGS(sii->curwrap));
796 ai = sii->curwrap;
797
798 /* if core is already in reset, just return */
799 if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
800 return;
801
802 W_REG(sii->osh, &ai->ioctrl, bits);
803 dummy = R_REG(sii->osh, &ai->ioctrl);
804 OSL_DELAY(10);
805
806 W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
807 dummy = R_REG(sii->osh, &ai->resetctrl);
808 OSL_DELAY(1);
809 }
810
811 /* reset and re-enable a core
812 * inputs:
813 * bits - core specific bits that are set during and after reset sequence
814 * resetbits - core specific bits that are set only during reset sequence
815 */
816 void
817 ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
818 {
819 si_info_t *sii;
820 aidmp_t *ai;
821 volatile uint32 dummy;
822
823 sii = SI_INFO(sih);
824 ASSERT(GOODREGS(sii->curwrap));
825 ai = sii->curwrap;
826
827 /*
828 * Must do the disable sequence first to work for arbitrary current core state.
829 */
830 ai_core_disable(sih, (bits | resetbits));
831
832 /*
833 * Now do the initialization sequence.
834 */
835 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
836 dummy = R_REG(sii->osh, &ai->ioctrl);
837 W_REG(sii->osh, &ai->resetctrl, 0);
838 OSL_DELAY(1);
839
840 W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
841 dummy = R_REG(sii->osh, &ai->ioctrl);
842 OSL_DELAY(1);
843 }
844
845
846 void
847 ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
848 {
849 si_info_t *sii;
850 aidmp_t *ai;
851 uint32 w;
852
853 sii = SI_INFO(sih);
854
855 if (BCM47162_DMP()) {
856 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
857 __FUNCTION__));
858 return;
859 }
860 if (BCM5357_DMP()) {
861 SI_ERROR(("%s: Accessing USB20H DMP register (ioctrl) on 5357\n",
862 __FUNCTION__));
863 return;
864 }
865
866 ASSERT(GOODREGS(sii->curwrap));
867 ai = sii->curwrap;
868
869 ASSERT((val & ~mask) == 0);
870
871 if (mask || val) {
872 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
873 W_REG(sii->osh, &ai->ioctrl, w);
874 }
875 }
876
877 uint32
878 ai_core_cflags(si_t *sih, uint32 mask, uint32 val)
879 {
880 si_info_t *sii;
881 aidmp_t *ai;
882 uint32 w;
883
884 sii = SI_INFO(sih);
885 if (BCM47162_DMP()) {
886 SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
887 __FUNCTION__));
888 return 0;
889 }
890 if (BCM5357_DMP()) {
891 SI_ERROR(("%s: Accessing USB20H DMP register (ioctrl) on 5357\n",
892 __FUNCTION__));
893 return 0;
894 }
895
896 ASSERT(GOODREGS(sii->curwrap));
897 ai = sii->curwrap;
898
899 ASSERT((val & ~mask) == 0);
900
901 if (mask || val) {
902 w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
903 W_REG(sii->osh, &ai->ioctrl, w);
904 }
905
906 return R_REG(sii->osh, &ai->ioctrl);
907 }
908
909 uint32
910 ai_core_sflags(si_t *sih, uint32 mask, uint32 val)
911 {
912 si_info_t *sii;
913 aidmp_t *ai;
914 uint32 w;
915
916 sii = SI_INFO(sih);
917 if (BCM47162_DMP()) {
918 SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0",
919 __FUNCTION__));
920 return 0;
921 }
922 if (BCM5357_DMP()) {
923 SI_ERROR(("%s: Accessing USB20H DMP register (iostatus) on 5357\n",
924 __FUNCTION__));
925 return 0;
926 }
927
928 ASSERT(GOODREGS(sii->curwrap));
929 ai = sii->curwrap;
930
931 ASSERT((val & ~mask) == 0);
932 ASSERT((mask & ~SISF_CORE_BITS) == 0);
933
934 if (mask || val) {
935 w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
936 W_REG(sii->osh, &ai->iostatus, w);
937 }
938
939 return R_REG(sii->osh, &ai->iostatus);
940 }
941
942 #if defined(BCMDBG) || defined(BCMDBG_DUMP)
943 /* print interesting aidmp registers */
944 void
945 ai_dumpregs(si_t *sih, struct bcmstrbuf *b)
946 {
947 si_info_t *sii;
948 osl_t *osh;
949 aidmp_t *ai;
950 uint i;
951
952 sii = SI_INFO(sih);
953 osh = sii->osh;
954
955 for (i = 0; i < sii->numcores; i++) {
956 si_setcoreidx(&sii->pub, i);
957 ai = sii->curwrap;
958
959 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
960 if (BCM47162_DMP()) {
961 bcm_bprintf(b, "Skipping mips74k in 47162a0\n");
962 continue;
963 }
964 if (BCM5357_DMP()) {
965 bcm_bprintf(b, "Skipping usb20h in 5357\n");
966 continue;
967 }
968
969 bcm_bprintf(b, "ioctrlset 0x%x ioctrlclear 0x%x ioctrl 0x%x iostatus 0x%x"
970 "ioctrlwidth 0x%x iostatuswidth 0x%x\n"
971 "resetctrl 0x%x resetstatus 0x%x resetreadid 0x%x resetwriteid 0x%x\n"
972 "errlogctrl 0x%x errlogdone 0x%x errlogstatus 0x%x"
973 "errlogaddrlo 0x%x errlogaddrhi 0x%x\n"
974 "errlogid 0x%x errloguser 0x%x errlogflags 0x%x\n"
975 "intstatus 0x%x config 0x%x itcr 0x%x\n",
976 R_REG(osh, &ai->ioctrlset),
977 R_REG(osh, &ai->ioctrlclear),
978 R_REG(osh, &ai->ioctrl),
979 R_REG(osh, &ai->iostatus),
980 R_REG(osh, &ai->ioctrlwidth),
981 R_REG(osh, &ai->iostatuswidth),
982 R_REG(osh, &ai->resetctrl),
983 R_REG(osh, &ai->resetstatus),
984 R_REG(osh, &ai->resetreadid),
985 R_REG(osh, &ai->resetwriteid),
986 R_REG(osh, &ai->errlogctrl),
987 R_REG(osh, &ai->errlogdone),
988 R_REG(osh, &ai->errlogstatus),
989 R_REG(osh, &ai->errlogaddrlo),
990 R_REG(osh, &ai->errlogaddrhi),
991 R_REG(osh, &ai->errlogid),
992 R_REG(osh, &ai->errloguser),
993 R_REG(osh, &ai->errlogflags),
994 R_REG(osh, &ai->intstatus),
995 R_REG(osh, &ai->config),
996 R_REG(osh, &ai->itcr));
997 if ((sih->chip == BCM4331_CHIP_ID) && (sii->coreid[i] == PCIE_CORE_ID)) {
998 /* point bar0 2nd 4KB window */
999 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, 0x18103000);
1000 bcm_bprintf(b, "ioctrlset 0x%x ioctrlclear 0x%x ioctrl 0x%x iostatus 0x%x"
1001 "ioctrlwidth 0x%x iostatuswidth 0x%x\n"
1002 "resetctrl 0x%x resetstatus 0x%x resetreadid 0x%x"
1003 " resetwriteid 0x%x\n"
1004 "errlogctrl 0x%x errlogdone 0x%x errlogstatus 0x%x"
1005 "errlogaddrlo 0x%x errlogaddrhi 0x%x\n"
1006 "errlogid 0x%x errloguser 0x%x errlogflags 0x%x\n"
1007 "intstatus 0x%x config 0x%x itcr 0x%x\n",
1008 R_REG(osh, &ai->ioctrlset),
1009 R_REG(osh, &ai->ioctrlclear),
1010 R_REG(osh, &ai->ioctrl),
1011 R_REG(osh, &ai->iostatus),
1012 R_REG(osh, &ai->ioctrlwidth),
1013 R_REG(osh, &ai->iostatuswidth),
1014 R_REG(osh, &ai->resetctrl),
1015 R_REG(osh, &ai->resetstatus),
1016 R_REG(osh, &ai->resetreadid),
1017 R_REG(osh, &ai->resetwriteid),
1018 R_REG(osh, &ai->errlogctrl),
1019 R_REG(osh, &ai->errlogdone),
1020 R_REG(osh, &ai->errlogstatus),
1021 R_REG(osh, &ai->errlogaddrlo),
1022 R_REG(osh, &ai->errlogaddrhi),
1023 R_REG(osh, &ai->errlogid),
1024 R_REG(osh, &ai->errloguser),
1025 R_REG(osh, &ai->errlogflags),
1026 R_REG(osh, &ai->intstatus),
1027 R_REG(osh, &ai->config),
1028 R_REG(osh, &ai->itcr));
1029 /* bar0 2nd 4KB window will be fixed in the next setcore */
1030 }
1031 }
1032 }
1033 #endif /* BCMDBG || BCMDBG_DUMP */
1034
1035 #ifdef BCMDBG
1036 void
1037 ai_view(si_t *sih, bool verbose)
1038 {
1039 si_info_t *sii;
1040 osl_t *osh;
1041 aidmp_t *ai;
1042 uint32 config;
1043
1044 sii = SI_INFO(sih);
1045 ai = sii->curwrap;
1046 osh = sii->osh;
1047 if (BCM47162_DMP()) {
1048 SI_ERROR(("Cannot access mips74k DMP in 47162a0\n"));
1049 return;
1050 }
1051 if (BCM5357_DMP()) {
1052 SI_ERROR(("Cannot access usb20h DMP in 5357\n"));
1053 return;
1054 }
1055
1056 SI_ERROR(("\nCore ID: 0x%x, config 0x%x\n", si_coreid(&sii->pub),
1057 (config = R_REG(osh, &ai->config))));
1058
1059 if (config & AICFG_RST)
1060 SI_ERROR(("resetctrl 0x%x, resetstatus 0x%x, resetreadid 0x%x, resetwriteid 0x%x\n",
1061 R_REG(osh, &ai->resetctrl), R_REG(osh, &ai->resetstatus),
1062 R_REG(osh, &ai->resetreadid), R_REG(osh, &ai->resetwriteid)));
1063
1064 if (config & AICFG_IOC)
1065 SI_ERROR(("ioctrl 0x%x, width %d\n", R_REG(osh, &ai->ioctrl),
1066 R_REG(osh, &ai->ioctrlwidth)));
1067
1068 if (config & AICFG_IOS)
1069 SI_ERROR(("iostatus 0x%x, width %d\n", R_REG(osh, &ai->iostatus),
1070 R_REG(osh, &ai->iostatuswidth)));
1071
1072 if (config & AICFG_ERRL) {
1073 SI_ERROR(("errlogctrl 0x%x, errlogdone 0x%x, errlogstatus 0x%x, intstatus 0x%x\n",
1074 R_REG(osh, &ai->errlogctrl), R_REG(osh, &ai->errlogdone),
1075 R_REG(osh, &ai->errlogstatus), R_REG(osh, &ai->intstatus)));
1076 SI_ERROR(("errlogid 0x%x, errloguser 0x%x, errlogflags 0x%x, errlogaddr "
1077 "0x%x/0x%x\n",
1078 R_REG(osh, &ai->errlogid), R_REG(osh, &ai->errloguser),
1079 R_REG(osh, &ai->errlogflags), R_REG(osh, &ai->errlogaddrhi),
1080 R_REG(osh, &ai->errlogaddrlo)));
1081 }
1082
1083 if (verbose && (config & AICFG_OOB)) {
1084 SI_ERROR(("oobselina30 0x%x, oobselina74 0x%x\n",
1085 R_REG(osh, &ai->oobselina30), R_REG(osh, &ai->oobselina74)));
1086 SI_ERROR(("oobselinb30 0x%x, oobselinb74 0x%x\n",
1087 R_REG(osh, &ai->oobselinb30), R_REG(osh, &ai->oobselinb74)));
1088 SI_ERROR(("oobselinc30 0x%x, oobselinc74 0x%x\n",
1089 R_REG(osh, &ai->oobselinc30), R_REG(osh, &ai->oobselinc74)));
1090 SI_ERROR(("oobselind30 0x%x, oobselind74 0x%x\n",
1091 R_REG(osh, &ai->oobselind30), R_REG(osh, &ai->oobselind74)));
1092 SI_ERROR(("oobselouta30 0x%x, oobselouta74 0x%x\n",
1093 R_REG(osh, &ai->oobselouta30), R_REG(osh, &ai->oobselouta74)));
1094 SI_ERROR(("oobseloutb30 0x%x, oobseloutb74 0x%x\n",
1095 R_REG(osh, &ai->oobseloutb30), R_REG(osh, &ai->oobseloutb74)));
1096 SI_ERROR(("oobseloutc30 0x%x, oobseloutc74 0x%x\n",
1097 R_REG(osh, &ai->oobseloutc30), R_REG(osh, &ai->oobseloutc74)));
1098 SI_ERROR(("oobseloutd30 0x%x, oobseloutd74 0x%x\n",
1099 R_REG(osh, &ai->oobseloutd30), R_REG(osh, &ai->oobseloutd74)));
1100 SI_ERROR(("oobsynca 0x%x, oobseloutaen 0x%x\n",
1101 R_REG(osh, &ai->oobsynca), R_REG(osh, &ai->oobseloutaen)));
1102 SI_ERROR(("oobsyncb 0x%x, oobseloutben 0x%x\n",
1103 R_REG(osh, &ai->oobsyncb), R_REG(osh, &ai->oobseloutben)));
1104 SI_ERROR(("oobsyncc 0x%x, oobseloutcen 0x%x\n",
1105 R_REG(osh, &ai->oobsyncc), R_REG(osh, &ai->oobseloutcen)));
1106 SI_ERROR(("oobsyncd 0x%x, oobseloutden 0x%x\n",
1107 R_REG(osh, &ai->oobsyncd), R_REG(osh, &ai->oobseloutden)));
1108 SI_ERROR(("oobaextwidth 0x%x, oobainwidth 0x%x, oobaoutwidth 0x%x\n",
1109 R_REG(osh, &ai->oobaextwidth), R_REG(osh, &ai->oobainwidth),
1110 R_REG(osh, &ai->oobaoutwidth)));
1111 SI_ERROR(("oobbextwidth 0x%x, oobbinwidth 0x%x, oobboutwidth 0x%x\n",
1112 R_REG(osh, &ai->oobbextwidth), R_REG(osh, &ai->oobbinwidth),
1113 R_REG(osh, &ai->oobboutwidth)));
1114 SI_ERROR(("oobcextwidth 0x%x, oobcinwidth 0x%x, oobcoutwidth 0x%x\n",
1115 R_REG(osh, &ai->oobcextwidth), R_REG(osh, &ai->oobcinwidth),
1116 R_REG(osh, &ai->oobcoutwidth)));
1117 SI_ERROR(("oobdextwidth 0x%x, oobdinwidth 0x%x, oobdoutwidth 0x%x\n",
1118 R_REG(osh, &ai->oobdextwidth), R_REG(osh, &ai->oobdinwidth),
1119 R_REG(osh, &ai->oobdoutwidth)));
1120 }
1121 }
1122 #endif /* BCMDBG */
Tomato firmware and modifications.