| blob | 6171dc0178d7cd8601b090650b18de6eb06fdf52 |
1 /*
2 * BCM47XX Denali based memory controller initialization
3 *
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id: aisdram.S,v 1.26.10.9 2011-01-20 04:28:14 Exp $
19 */
21 #include <hndsoc.h>
22 #include <bcmdevs.h>
23 #include <bcmnvram.h>
24 #include <sbsdram.h>
25 #include <sbmemc.h>
26 #include <sbsocram.h>
27 #include <dmemc_core.h>
28 #include <amemc_core.h>
29 #include <sbchipc.h>
31 #if defined(NFLASH_SUPPORT)
32 #include <nflash.h>
33 #endif
35 #include <mipsinc.h>
38 /* Debug macro - write a number to a chipc reg - use it with caution,
39 * it changes k0 and k1 registers.
40 */
41 #ifdef BCMDBG
43 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
44 #define FLADDR_OFF 0
45 #define FLDATA_OFF 12
46 #else
47 #define FLADDR_OFF 4
48 #define FLDATA_OFF 8
49 #endif
51 #define TRACEINIT(x) \
52 li k0,KSEG1ADDR(0x18000040); \
53 li k1,x; \
54 sw k1,FLADDR_OFF(k0)
56 #define TRACE(x) \
57 li k1,x; \
58 sw k1,FLADDR_OFF(k0)
60 #define TRACE2(x) \
61 li k1,x; \
62 sw k1,FLDATA_OFF(k0)
64 #else
65 #define TRACEINIT(x)
66 #define TRACE(x)
67 #define TRACE2(x)
68 #endif /* BCMDBG */
69 .text
71 dmemc_init:
72 .word 0, 0x00000101
73 .word 1, 0x01030100
74 .word 2, 0x01030101
75 .word 3, 0x01010101
76 .word 5, 0x00000100
77 .word 7, 0x01010000
78 .word 8, 0x00000100
79 .word 9, 0x00000100
80 .word 10, 0x01010101
81 .word 12, 0x00010200
82 .word 16, 0x0f00000a
83 .word 20, 0x64000000
84 .word 27, 0x00000001
85 .word 28, 0x0039000a
86 .word 29, 0x081b002b
87 .word 30, 0x00000000
88 .word 31, 0x00000000
89 .word 33, 0x000200c8
90 .word 35, 0x000000c8
91 .word 36, 0x00000000
92 .word 125, 0x01010000
93 .word 126, 0x02000100
94 .word 129, 0x02000200
95 .word 132, 0x00000000
96 .word 138, 0x00000000
97 .word 139, 0x00000000
98 .word 151, 0x00000005
99 .word DMEMC_TABLE_END
101 sdr_init:
102 .word 4, 0x00000100
103 .word 6, 0x00000000
104 .word 11, 0x00030001
105 .word 14, 0x00020000
106 .word 15, 0x0f000102
107 .word 17, 0x05000002
108 .word 18, 0x00000003
109 .word 19, 0x00090200
110 .word 21, 0x70006400
111 .word 22, 0x7f000070
112 .word 23, 0x00400000
113 .word 24, 0x09030600
114 .word 25, 0x00170017
115 .word 32, 0x00320000
116 .word 34, 0x000a4186
117 .word DMEMC_TABLE_END
119 ddr1_init:
120 .word 4, 0x00000100
121 .word 6, 0x00000100
122 .word 11, 0x00030000
123 .word 14, 0x02030200
124 .word 15, 0x0f010203
125 .word 17, 0x06000002
126 .word 18, 0x00000006
127 .word 19, 0x0010010e
128 .word 21, 0x20006400
129 .word 22, 0x5700002a
130 .word 23, 0x00340000
131 .word 24, 0x0e030800
132 .word 25, 0x000f000f
133 .word 26, 0x000f000f
134 .word 32, 0x00000000
135 .word 34, 0x000d2d89
136 .word 127, 0x00000001
137 .word 128, 0x07000300
138 .word 130, 0x00010103
139 .word 131, 0x00000200
140 .word 133, 0x06120000
141 .word 134, 0x06120612
142 .word 135, 0x06120612
143 .word 136, 0x00000612
144 .word 137, 0x00000032
145 .word 140, 0x001f4008
146 .word 141, 0x001f4008
147 .word 142, 0x002ee004
148 .word 143, 0x002ee004
149 .word 146, 0x000f0033
150 .word 147, 0xf4113c17
151 .word 148, 0xf4113c17
152 .word 149, 0x26c00300
153 .word 150, 0x26c00300
154 .word DMEMC_TABLE_END
156 ddr2_init:
157 .word 4, 0x00010100
158 .word 6, 0x00000000
159 .word 11, 0x00030000
160 .word 14, 0x02030203
161 .word 15, 0x0f030204
162 .word 17, 0x08000002
163 .word 18, 0x00000004
164 .word 19, 0x000f020e
165 .word 21, 0x16006400
166 .word 22, 0x6026162a
167 .word 23, 0x00340000
168 .word 24, 0x35060c00
169 .word 25, 0x00200020
170 .word 26, 0x00200020
171 .word 32, 0x006b0000
172 .word 34, 0x003848e1
173 .word 127, 0x00000002
174 .word 128, 0x07000404
175 .word 130, 0x03020304
176 .word 131, 0x00000400
177 .word 133, 0x081b0000
178 .word 134, 0x081b081b
179 .word 135, 0x081b081b
180 .word 136, 0x0000081b
181 .word 137, 0x00400642
182 .word 140, 0x00164008
183 .word 141, 0x00164008
184 .word 142, 0x00236004
185 .word 143, 0x00236004
186 .word 146, 0x000f0133
187 .word 147, 0xf4112c17
188 .word 148, 0xf4112c17
189 .word 149, 0x26c00300
190 .word 150, 0x26c00300
191 .word DMEMC_TABLE_END
193 #if defined(NFLASH_SUPPORT)
194 nfl_pagesz_map:
195 /* page size mapping */
196 .word 0x200, 0x800, 0x1000, 0x2000
198 nfl_blksz_map:
199 /* block size mapping */
200 .word 0x4000, 0x20000, 0x2000, 0x80000, 0x40000, 0, 0, 0
201 #endif
203 /* Register conventions.
204 * Inherited from sisdram.S:
205 * s2 = SI_ENUM_BASE
206 * s5 = Relocation factor
207 * s6 = ChipId reg
208 * s7 = ChipType
209 * Local:
210 * s0 = sdram_config + sdram_refresh values
211 * s1 = package opt
212 * s3 = Controller corerev
213 * s4 = Controller coreid
214 * s8 = config_ncdl
215 * a1 = dmemc regs
216 * a2 = dmemc DMP regs
217 * a3 = memory type (sdr,ddr1,ddr2)
218 */
220 LEAF(ai_draminit)
221 .set mips32
222 .set noreorder
224 TRACE(0x415301)
226 move t6,ra
228 /* Scan for a Denali DDR controller (a0) */
229 lw a0,CC_EROMPTR(s2)
230 li t0,KSEG1 # t0 = KSEG1
231 or a0,a0,t0 # a0 points to the EROM
232 TRACE(0x415302)
233 1:
234 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
235 xor t0,a0,4
236 lw t0,0(t0)
237 add t3,a0,4
238 xor t3,t3,4
239 lw t3,0(t3)
240 #else
241 lw t0,0(a0) # t0 = CIA
242 lw t3,4(a0) # t3 = CIB
243 #endif
244 and t1,t0,ER_TAG
245 TRACE(0x415303)
246 beq t1,ER_END,noctrl
247 nop
248 TRACE(0x415304)
249 beq t1,ER_CI,2f
250 nop
251 TRACE(0x415305)
252 b 1b
253 addi a0,4
255 2: TRACE(0x415306)
256 and s4,t0,CIA_CID_MASK
257 srl s4,s4,CIA_CID_SHIFT # s4 has controler coreid
259 beq s4,DMEMC_CORE_ID,founddmemc
260 nop
262 beq s4,DMEMS_CORE_ID,founddmemc
263 nop
265 beq s4,AMEMC_CORE_ID,founddmemc
266 nop
268 b 1b
269 addi a0,8 # Skip CIB too
271 /* No DMEMC controller found */
272 noctrl: TRACE(0x415307)
273 jr t6
274 li v0,-1
277 founddmemc:
278 TRACE(0x415308)
279 /* If we found the controller, but we are already in RAM, there is nothing
280 * to do. This will change if/when we have an AI chip with MIPS and
281 * SOCRAM only.
282 */
283 bnez s5,1f # Not running from RAM, go ahead
284 nop
286 jr t6 # Return with 0 rc.
287 move v0,zero
289 /* We'll cheat a little: memory controllers don't have master ports, so
290 * the EROM entry right after the CIDs is the slave port for the registers
291 */
292 1:
293 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
294 add a1,a0,8
295 xor a1,a1,4
296 lw a1,0(a1)
297 #else
298 lw a1,8(a0)
299 #endif
300 li t2,AD_ADDR_MASK
301 and a1,a1,t2
302 li t0,KSEG1 # t0 = KSEG1
303 or a1,a1,t0 # a1: dmemc regs
304 /* after that, the first slave wrapper will be its DMP registers */
305 addi a0,12
306 1:
307 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
308 xor t0,a0,4
309 lw t0,0(t0)
310 #else
311 lw t0,0(a0)
312 #endif
313 and t1,t0,ER_TAG
314 beq t1,ER_ADD,addesc
315 nop
316 b 1b
317 addi a0,4
319 addesc: and t1,t0,AD_ST_MASK
320 beq t1,AD_ST_SWRAP,swrap
321 nop
322 b 1b
323 addi a0,4
325 swrap: and a2,t0,t2
326 li t0,KSEG1 # t0 = KSEG1
327 or a2,a2,t0 # a2: dmemc DMP regs
329 /* Got our core, reset it */
330 TRACE(0x415309)
331 bal ai_core_reset
332 nop
334 /* Get package option for later */
335 TRACE(0x41530a)
336 li t0,CID_PKG_MASK
337 and t0,t0,s6
338 srl s1,t0,CID_PKG_SHIFT # s1 = package opt
340 /* Find out the type of memory from the straps */
341 /* Corerevs 0 & 1 did not have this register, so we have to
342 * check the corerev and use chipstatus for those two.
343 */
344 and t3,t3,CIB_REV_MASK
345 srl s3,t3,CIB_REV_SHIFT # s3 = core revision
346 beq s4,DMEMS_CORE_ID,1f
347 nop
349 /* Go find nvram if the controller is AMEMC. */
350 beq s4,AMEMC_CORE_ID,find_nvram
351 nop
353 ble s3,1,is16x
354 nop
356 1: /* Not a 4716/47162 (a0?) read the stat register */
357 lw t0,DMEMC_STAT(a1)
358 li t1,DM_STAT_MASK
359 and a3,t0,t1 # a3 == 4 if ddr2, 2 if ddr1, 1 if sdr.
360 b find_nvram
361 nop
363 /* Check chipc: chipstatus for the ddr1/ddr2 strapping option */
364 is16x: TRACE(0x41530b)
365 lw t0,CC_CHIPST(s2)
366 li t1,0x200
367 and t0,t0,t1
368 beqz t0,find_nvram
369 li a3,DM_STAT_DDR2
371 li a3,DM_STAT_DDR1
373 /* Read sdram_config from nvram */
374 find_nvram:
375 TRACE(0x41530c)
376 li t0,KSEG1ADDR(SI_FLASH2 - NVRAM_SPACE)
377 li t1,FLASH_MIN
378 li t2,SI_FLASH2_SZ
379 li t3,NVRAM_MAGIC
381 #if defined(NFLASH_SUPPORT)
382 /* Take care of 5357 NAND boot */
383 li t4,CID_ID_MASK
384 and t4,t4,s6
385 bne t4,BCM5357_CHIP_ID,1f
386 nop
387 lw t5,CC_CHIPST(s2)
388 li t4,0x10
389 and t4,t4,t5
390 beqz t4,1f
391 nop
393 la t4,nfl_size_block
394 add t4,t4,s5
395 jalr t4
396 nop
397 beqz v0,embedded_nv
398 nop
400 /* skip bad blocks and locate nvram */
401 move t1,v0 # block size
402 move t2,t1
403 check_badb:
404 move a0,t2
405 move t0,a1 # save a1
406 move a1,v1 # page size
407 la t4,nfl_check_badb
408 add t4,t4,s5
409 jalr t4
410 nop
411 move a1,t0 # restore a1
412 bnez v0,skip_badb
413 nop
415 li t0,KSEG1ADDR(SI_FLASH1)
416 add t4,t0,t2
417 lw t5,0(t4)
418 beq t3,t5,read_config
419 nop
420 skip_badb:
421 add t2,t2,t1
422 li t5,SI_FLASH1_SZ
423 blt t2,t5,check_badb
424 nop
425 b embedded_nv
426 nop
427 #endif
429 1: add t4,t0,t1
430 lw t5,0(t4)
431 beq t3,t5,read_config
432 nop
434 sll t1,t1,1
435 ble t1,t2,1b
436 nop
438 #if defined(NFLASH_SUPPORT)
439 embedded_nv:
440 #endif
441 /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
442 TRACE(0x41530d)
443 li t4,KSEG1ADDR(SI_FLASH1 + 0x1000)
444 lw t5,0(t4)
445 beq t3,t5,read_config
446 nop
448 TRACE(0x41530e)
449 li t4,KSEG1ADDR(SI_FLASH1 + 0x400)
450 lw t5,0(t4)
451 beq t3,t5,read_config
452 nop
454 /* No nvram, pick sone defaults */
456 /* assume DDRM16MX16 if ddr1 */
457 TRACE(0x41530f)
458 bne a3,DM_STAT_DDR1,1f
459 nop
461 beq s4,DMEMC_CORE_ID,init_dmemc
462 li s0,0x283 # Value for dmemc
464 /* Use DDR1M16MX16 if QT and DDR1M32MX16 otherwise */
465 beq s1,HWSIM_PKG_ID,init_dmemc
466 li s0,0x103 # Value for dmems
468 b init_dmemc
469 li s0,0x003 # Value for dmems at 200MHz
471 1: beq a3,DM_STAT_SDR,init_dmemc
472 li s0,0x002 # Value for SDR
474 /* For ddr2, use DDR2M32X16X2 if QT and DDR2M128X16X2 otherwise */
475 beq s1,HWSIM_PKG_ID,init_dmemc
476 li s0,0x104
478 b init_dmemc
479 li s0,0x144
481 read_config:
482 /* sdram_config is a 16bit value 12 bytes inside the nvram hdr.
483 * Currently it is defined as:
484 * 10:8 column_size as per control13
485 * 7 reduc i.e. memory is half the width of the controller
486 * 6 8 banks
487 * 5 bypass
488 * 2:0 cas latency
489 *
490 * sdram_refresh:
491 * 15:8 delay_dqs_0
492 * 7:0 clk_wr_delay, or clk_wr_delay_0 (for corerev >= 2)
493 *
494 * sdram_ncdl: control22
495 * 31:24 clk_dqs_delay, or clk_wr_delay_1 (for corerev >= 2)
496 * 23:16 delay_dqs_3
497 * 15:8 delay_dqs_2
498 * 7:0 delay_dqs_1
499 */
500 TRACE(0x415310)
501 lw s0,12(t4) # Pick up sdram_config & sdram_refresh
503 /* Determine if it is DMEMC or AMEMC */
504 bne s4,AMEMC_CORE_ID,init_dmemc
505 lw s8,16(t4) # Pick up sdram_ncdl
507 /* Initailize AMEMC */
508 la t2,ai_amemcinit
509 add t2,t2,s5
510 jalr t2
511 nop
513 jr t6
514 move v0,zero
516 /* Initialize DMEMC/DMEMS */
517 init_dmemc:
518 /* For DDR2, init pvt controller */
519 bne a3,DM_STAT_DDR2,init_regs
520 nop
522 TRACE(0x415311)
523 li t0,1
524 sw t0,DMEMC_PVTGROUPJ(a1)
525 sw zero,DMEMC_PVTGROUPA(a1)
526 sw t0,DMEMC_PVTGROUPA(a1)
528 /* Init the common regs */
529 init_regs:
530 TRACE(0x415312)
531 la a0,dmemc_init
532 bal dmemc_init_regs # dmemc_init_regs(a0): Inits from the table @ a0
533 nop
535 la a0,sdr_init
536 beq a3,DM_STAT_SDR,1f
537 nop
539 TRACE(0x415313)
540 la a0,ddr1_init
541 beq a3,DM_STAT_DDR1,1f
542 nop
544 TRACE(0x415314)
545 la a0,ddr2_init
546 1: bal dmemc_init_regs
547 nop
549 /* Fixup differences between dmems & dmemc */
550 fixs: bne s4,DMEMS_CORE_ID,fix2
551 nop
553 li t0,0x02020002
554 beq a3,DM_STAT_SDR,1f
555 nop
557 li t0,0x18006400
558 sw t0,DMEMC_CONTROL21(a1)
559 li t0,0x7f000018 # DLL DQS delay for DDR1
560 sw t0,DMEMC_CONTROL22(a1)
561 li t0,0x00500000
562 sw t0,DMEMC_CONTROL23(a1)
563 li t0,0x00320000 # Change MRS data for DDR1
564 sw t0,DMEMC_CONTROL32(a1)
566 li t0,0x02000002
568 1: sw t0,DMEMC_CONTROL52(a1)
569 li t0,0x00000001
570 sw t0,DMEMC_CONTROL53(a1)
572 /* Fixup differences in 47162 */
573 fix2: li t0,CID_ID_MASK
574 and t0,t0,s6
575 bne t0,BCM47162_CHIP_ID,nvover
576 nop
578 li t0,0x16006400
579 sw t0,DMEMC_CONTROL21(a1)
580 li t0,0x00480000
581 sw t0,DMEMC_CONTROL23(a1)
583 /* Presumaby this is for DDR1 only? */
584 li t0,0x61161616
585 sw t0,DMEMC_CONTROL22(a1)
587 /* Override the dll delays from nvram if provided */
588 nvover: beqz s8,chhalf
589 nop
591 # Check for dmems (any rev)
592 beq s4,DMEMS_CORE_ID,old_ncdl
593 nop
595 # Dmemc rev < 2?
596 ble s3,1,old_ncdl
597 nop
599 li t0,0x7f000000
600 and t0,t0,s0 # delay_dqs_0
601 srl t0,t0,15
602 lw t1,DMEMC_CONTROL140(a1)
603 li t2,~0x0000fe00
604 and t1,t1,t2
605 or t0,t0,t1
606 sw t0,DMEMC_CONTROL140(a1)
608 li t0,0x7f
609 and t0,t0,s8 # delay_dqs_1
610 sll t0,t0,9
611 lw t1,DMEMC_CONTROL141(a1)
612 and t1,t1,t2
613 or t0,t0,t1
614 sw t0,DMEMC_CONTROL141(a1)
616 li t0,0x7f0000
617 and t0,t0,s0 # clk_wr_delay_0
618 srl t0,t0,8
619 lw t1,DMEMC_CONTROL142(a1)
620 li t2,~0x00007f00
621 and t1,t1,t2
622 or t0,t0,t1
623 sw t0,DMEMC_CONTROL142(a1)
625 li t0,0x7f000000
626 and t0,t0,s8 # clk_wr_delay_1
627 srl t0,t0,16
628 lw t1,DMEMC_CONTROL143(a1)
629 and t1,t1,t2
630 or t0,t0,t1
631 sw t0,DMEMC_CONTROL143(a1)
633 b chhalf
634 nop
636 old_ncdl:
637 li t0,0x7f000000
638 and t0,t0,s0 # delay_dqs_0
639 or t0,t0,0x6400
640 sw t0,DMEMC_CONTROL21(a1)
641 li t0,0x007f0000
642 and t0,t0,s0 # clk_wr_delay
643 sw t0,DMEMC_CONTROL23(a1)
645 sw s8,DMEMC_CONTROL22(a1)
647 /* Check for half-width */
648 chhalf: li t0,0x80
649 and t0,t0,s0
650 beqz t0,ch8banks
651 nop
653 setreduc:
654 /* Set reduc bit if half-wide */
655 TRACE(0x415315)
656 lw t0,DMEMC_CONTROL08(a1)
657 li t1,0x01000000
658 or t0,t0,t1
659 sw t0,DMEMC_CONTROL08(a1)
661 /* Check for 8-bank DDRs */
662 ch8banks:
663 li t0,0x40
664 and t0,t0,s0
665 beqz t0,docaslat
666 nop
668 /* Change regs for 8-bank DDRs */
669 do8banks:
670 lw t0,DMEMC_CONTROL05(a1)
671 li t1,0x00010000
672 or t0,t0,t1
673 sw t0,DMEMC_CONTROL05(a1)
675 lw t0,DMEMC_CONTROL19(a1)
676 li t1,0x0000000e
677 or t0,t0,t1
678 sw t0,DMEMC_CONTROL19(a1)
680 lw t0,DMEMC_CONTROL24(a1)
681 li t1,~0xff000000
682 li t2,0x22000000
683 and t0,t0,t1
684 or t0,t0,t2
685 sw t0,DMEMC_CONTROL24(a1)
687 lw t0,DMEMC_CONTROL34(a1)
688 li t1,~0x00ff0000
689 li t2,0x00250000
690 and t0,t0,t1
691 or t0,t0,t2
692 sw t0,DMEMC_CONTROL34(a1)
694 /* Set the right value for column size and CAS latency */
695 docaslat:
696 TRACE(0x415316)
697 li t0,0x0707
698 and t0,t0,s0
699 sw t0,DMEMC_CONTROL13(a1)
700 andi t0,s0,7 # Isolate cas
701 beq s4,DMEMS_CORE_ID,setcaslin
702 nop
703 ble s3,1,setcaslin
704 nop
705 /* Additional settings required for dmemc rev >= 2 */
706 sll t1,t0,8
707 and t1,0xf00
708 bne a3,DM_STAT_DDR1,1f
709 nop
710 and t1,0x300
711 1: lw t2,DMEMC_CONTROL128(a1)
712 and t2,~0xf00
713 or t2,t2,t1
714 sw t2,DMEMC_CONTROL128(a1)
715 sll t1,t0,4
716 lw t2,DMEMC_CONTROL137(a1)
717 and t2,~0x70
718 or t2,t2,t1
719 sw t2,DMEMC_CONTROL137(a1)
720 bne a3,DM_STAT_DDR2,setcaslin
721 nop
722 sub t1,t0,1
723 sll t1,8
724 lw t2,DMEMC_CONTROL130(a1)
725 and t2,~0xf00
726 or t2,t2,t1
727 sw t2,DMEMC_CONTROL130(a1)
728 sll t1,8
729 lw t2,DMEMC_CONTROL15(a1)
730 and t2,~0xf0000
731 or t2,t2,t1
732 sw t2,DMEMC_CONTROL15(a1)
733 setcaslin:
734 /* Set caslat_lin and caslat_lin_gate */
735 lw t2,DMEMC_CONTROL16(a1)
736 /* Take care of fractional CAS latencies for DDR1 */
737 li t3,0
738 bne a3,DM_STAT_DDR1,1f
739 nop
740 andi t1,t0,4
741 beqz t1,1f
742 nop
743 andi t0,t0,3 # take off half bit
744 li t3,1
745 1: sll t0,t0,1 # * 2
746 add t0,t0,t3
747 addi t1,t0,1 # + 1 => caslin
748 sll t1,t1,8
749 or t2,t2,t1
750 addi t0,t0,-1 # and -1 => caslin_gate
751 sll t0,t0,16
752 or t2,t0,t2
753 sw t2,DMEMC_CONTROL16(a1)
755 /* Finally set bypass mode if needed, but always for quickturn */
756 ckbyp: beq s1,HWSIM_PKG_ID,dobypass
757 nop
758 li t0,0x20
759 and t0,t0,s0
760 beqz t0,ckvsim
761 nop
763 dobypass:
764 TRACE(0x415317)
766 beq s4,DMEMS_CORE_ID,1f
767 nop
769 bgt s3,1,4f
770 nop
772 1: li t0,0x00170017
773 beq a3,DM_STAT_SDR,2f
774 nop
776 li t0,0x000f000f
777 beq a3,DM_STAT_DDR1,2f
778 nop
780 li t0,0x00200020
782 2: sw t0,DMEMC_CONTROL25(a1)
783 beq s4,DMEMS_CORE_ID,3f
784 nop
785 sw t0,DMEMC_CONTROL26(a1)
787 3: lw t0,DMEMC_CONTROL28(a1)
788 li t1,0x00ff0000
789 or t0,t0,t1
790 sw t0,DMEMC_CONTROL28(a1)
792 4: lw t0,DMEMC_CONTROL29(a1)
793 li t1,~0x000000ff
794 li t2,0x0000005f
795 and t0,t0,t1
796 or t0,t0,t2
797 sw t0,DMEMC_CONTROL29(a1)
799 lw t0,DMEMC_CONTROL05(a1)
800 li t1,0x00000001
801 or t0,t0,t1
802 sw t0,DMEMC_CONTROL05(a1)
804 beq s4,DMEMS_CORE_ID,ckvsim
805 nop
807 ble s3,1,ckvsim
808 nop
810 lw t0,DMEMC_CONTROL140(a1)
811 li t1,0x10000000
812 or t0,t0,t1
813 sw t0,DMEMC_CONTROL140(a1)
815 lw t0,DMEMC_CONTROL141(a1)
816 or t0,t0,t1
817 sw t0,DMEMC_CONTROL141(a1)
819 /* For vsim change tinit so sims run faster */
820 ckvsim: bne s1,HDLSIM_PKG_ID,turnon
821 nop
823 TRACE(0x415318)
824 li t0,0x36
825 sw t0,DMEMC_CONTROL36(a1)
827 turnon:
828 /* We are ready, turn controller on */
829 TRACE(0x415319)
830 lw t0,DMEMC_CONTROL09(a1) # Read current control09 reg
831 or t0,t0,DMC09_START # Add start bit
832 sw t0,DMEMC_CONTROL09(a1) # Start the controller
834 beq s4,DMEMS_CORE_ID,2f
835 nop
837 ble s3,1,2f
838 nop
840 1: lw t0,DMEMC_CONTROL133(a1) # Poll for INT_INIT_DONE (dmemc >=2)
841 and t1,t0,DM_INT_INIT_DONE
842 beqz t1,1b
843 nop
844 /* Bypass mode programming */
845 lw t0,DMEMC_CONTROL05(a1)
846 li t1,0x00000001
847 and t0,t0,t1
848 beqz t0,ack_ints
849 nop
850 lw t1,DMEMC_CONTROL144(a1)
851 srl t1,t1,3
852 lw t2,DMEMC_CONTROL140(a1)
853 li t0,~0x03ff0000
854 and t2,t2,t0
855 sll t0,t1,16
856 or t2,t2,t0
857 sw t2,DMEMC_CONTROL140(a1)
859 lw t2,DMEMC_CONTROL142(a1)
860 li t0,~0x01ff8000
861 and t2,t2,t0
862 sll t0,t1,1
863 add t0,t0,t1
864 li t1,0x3ff
865 and t0,t0,t1
866 sll t0,t0,15
867 or t2,t2,t0
868 sw t2,DMEMC_CONTROL142(a1)
870 lw t1,DMEMC_CONTROL145(a1)
871 srl t1,t1,3
872 lw t2,DMEMC_CONTROL141(a1)
873 li t0,~0x03ff0000
874 and t2,t2,t0
875 sll t0,t1,16
876 or t2,t2,t0
877 sw t2,DMEMC_CONTROL141(a1)
879 lw t2,DMEMC_CONTROL143(a1)
880 li t0,~0x01ff8000
881 and t2,t2,t0
882 sll t0,t1,1
883 add t0,t0,t1
884 li t1,0x3ff
885 and t0,t0,t1
886 sll t0,t0,15
887 or t2,t2,t0
888 sw t2,DMEMC_CONTROL143(a1)
889 ack_ints:
890 /* Clear any pending interrupts from dmemc */
891 li t1,DMC132_INTACK_MASK
892 and t0,t0,t1 # t0 = control133 & mask
893 lw t2,DMEMC_CONTROL132(a1)
894 not t1
895 and t2,t1,t2 # t2 = control132 & ~mask
896 or t0,t0,t2 # Or them and ...
897 sw t0,DMEMC_CONTROL132(a1) # Ack all ints
898 b 3f
899 nop
901 2: lw t0,DMEMC_CONTROL24(a1) # Poll for INT_INIT_DONE (dmems & dmemc<2)
902 and t1,t0,DM_INT_INIT_DONE
903 beqz t1,2b
904 nop
905 /* Clear any pending interrupts from dmemc */
906 li t1,DMC23_INTACK_MASK
907 and t0,t0,t1 # t0 = control24 & mask
908 lw t2,DMEMC_CONTROL23(a1)
909 not t1
910 and t2,t1,t2 # t2 = control23 & ~mask
911 or t0,t0,t2 # Or them and ...
912 sw t0,DMEMC_CONTROL23(a1) # Ack all ints
914 3: jr t6
915 li v0,0
917 /* Reset core using DMP regs at (a2) */
918 ai_core_reset:
919 /* Set reset while enabling the clock */
920 li t9,(SICF_FGC | SICF_CLOCK_EN)
921 li t8,AIRC_RESET
922 sw t9,AI_IOCTRLSET(a2)
923 sw t8,AI_RESETCTRL(a2)
925 /* Read back and delay */
926 lw t8,AI_RESETCTRL(a2)
927 lw t8,AI_RESETCTRL(a2)
928 lw t8,AI_RESETCTRL(a2)
930 /* Clear reset */
931 li t8,0
932 sw t8,AI_RESETCTRL(a2)
934 /* Read back and delay */
935 lw t8,AI_RESETCTRL(a2)
936 lw t8,AI_RESETCTRL(a2)
937 lw t8,AI_RESETCTRL(a2)
939 /* Clear Force Gated Clock */
940 li t9,SICF_FGC
941 sw t9,AI_IOCTRLCLEAR(a2)
943 /* Read back and delay */
944 lw t9,AI_IOCTRL(a2)
945 lw t9,AI_IOCTRL(a2)
946 lw t9,AI_IOCTRL(a2)
948 jr ra
949 nop
951 /* Use table at (a0) to init dmemc regs.
952 * Assumes (a1) points to the regs.
953 */
954 dmemc_init_regs:
955 beq s4,DMEMS_CORE_ID,loop_regs
956 li t3,128
958 ble s3,1,loop_regs
959 nop
961 li t3,256
963 loop_regs:
964 add a0,a0,s5 # Relocate address
965 li t0,DMEMC_TABLE_END
966 1: lw t1,0(a0) # Pick up reg num
967 bge t1,t3,2f # Return if the reg num >= num of supported regs
968 nop
969 beq t1,t0,2f # Return if done
970 nop
972 lw t2,4(a0) # Get reg value
973 sll t1,2 # Reg num * 4 is reg offset
974 addu t1,a1,t1
975 #if defined(IL_BIGENDIAN) && defined(BCMHND74K)
976 xor t1,t1,4
977 #endif
978 sw t2,0(t1) # Write reg
979 b 1b
980 addi a0,8
982 2: jr ra
983 nop
985 END(ai_draminit)
987 #if defined(NFLASH_SUPPORT)
988 LEAF(nfl_size_block)
989 lw t9,CC_NAND_CONFIG(s2)
990 li t8,0x3
991 sll t8,20
992 and t8,t8,t9
993 srl t8,18 # index = (ncf & (0x3 << 20) >> 18)
994 la a0,nfl_pagesz_map
995 add a0,a0,s5 # Relocate address
996 add t8,t8,a0
997 lw v1,0(t8)
999 li t8,0x7
1000 sll t8,28
1001 and t8,t8,t9
1002 srl t8,26 # index = (ncf & (0x7 << 28) >> 26)
1003 la a0,nfl_blksz_map
1004 add a0,a0,s5 # Relocate address
1005 add t8,t8,a0
1006 lw v0,0(t8)
1007 jr ra
1008 nop
1009 END(nfl_size_block)
1012 LEAF(nfl_check_badb)
1013 add t9,a0,zero
1014 move t5,zero
1015 check_spare:
1016 sw t9,CC_NAND_CMD_ADDR(s2)
1017 lw t9,CC_NAND_CMD_ADDR(s2) # read back
1018 li t9,NCMD_SPARE_RD
1019 sw t9,CC_NAND_CMD_START(s2)
1020 lw t9,CC_NAND_CMD_START(s2) # read back
1021 /* Polling */
1022 li t9,NIST_CTRL_READY
1023 li t8,NIST_FLASH_READY
1024 or t9,t9,t8
1025 1: lw t8,CC_NAND_INTFC_STATUS(s2)
1026 and t7,t8,t9
1027 bne t7,t9,1b
1028 nop
1029 /* Check spare valid */
1030 li t9,NIST_SPARE_VALID
1031 and t7,t8,t9
1032 beqz t7,badb
1033 nop
1034 /* Check spare byte */
1035 lw t9,CC_NAND_SPARE_RD_0(s2)
1036 li t8,0xff
1037 and t7,t8,t9
1038 bne t7,t8,badb
1039 nop
1040 /* Read next page */
1041 add t9,a0,a1
1042 add t5,t5,1
1043 beq t5,1,check_spare
1044 nop
1046 jr ra
1047 li v0,0
1048 badb:
1049 jr ra
1050 li v0,1
1051 END(nfl_check_badb)
1052 #endif
1054 /* *********************************************************************
1055 * AI_AMEMCINIT
1056 *
1057 * AI version of DDR / memory controller initialization
1058 *
1059 * This routine deals with DDR23_PHY and PL341 MEMC.
1060 *
1061 ********************************************************************* */
1062 /* Convenient macro for writing registers (use t0 for base) */
1063 #define ddr_write(offset, value) \
1064 li a0, (value); \
1065 sw a0, offset(t0);
1067 LEAF(ai_amemcinit)
1068 .set noreorder
1070 /*
1071 * ddr23_phy_init
1072 */
1074 li t0, KSEG1ADDR(AI_DDRPHY_BASE)
1076 #ifndef CFG_QUICKTURN
1078 li t2, 0x10000000
1079 li t3, 0
1080 li t5, 0
1081 2:
1082 /* Do recalibration */
1083 beq t5, PVT_MAX_RETRY, 9f
1084 lw t7, DDR23PHY_ZQ_PVT_COMP_CTL(t0)
1085 ddr_write(DDR23PHY_ZQ_PVT_COMP_CTL, 0x04000000);
1086 1:
1087 /* Wait until sample_done == 1 */
1088 lw t1, DDR23PHY_ZQ_PVT_COMP_CTL(t0)
1089 and t1, t1, t2;
1090 beq t1, zero, 1b
1091 nop
1093 /* Increase total retry count */
1094 add t5, t5, 1
1096 /* Check if the result is the same as previous one */
1097 lw t1, DDR23PHY_ZQ_PVT_COMP_CTL(t0)
1098 beq t1, t7, 3f
1099 nop
1101 /* If not, clear matched count */
1102 b 2b
1103 li t3, 0
1104 3:
1105 /* If so, increase matched count; continue if matched count == 3 */
1106 add t3, t3, 1
1107 bne t3, PVT_MATCHED_COUNT, 2b
1108 nop
1109 9:
1111 /* setup PLL */
1112 ddr_write(DDR23PHY_PLL_CONFIG, 0x8000000c);
1113 ddr_write(DDR23PHY_PLL_PRE_DIVIDER,
1114 0x00000011 + (PLL_NDIV_INT_VAL << 8));
1115 ddr_write(DDR23PHY_PLL_DIVIDER, 0x02000000);
1116 ddr_write(DDR23PHY_PLL_CONFIG, 0x80000008);
1118 /* Wait for PLL locked */
1119 li t2, 1;
1120 1: /* Wait until lock == 1 */
1121 lw t1, DDR23PHY_PLL_STATUS(t0)
1122 and t1, t1, t2;
1123 beq t1, zero, 1b
1124 nop
1126 /* De-assert PLL reset */
1127 ddr_write(DDR23PHY_PLL_CONFIG, 0x80000000);
1128 ddr_write(DDR23PHY_PLL_CONFIG, 0x00000000);
1130 /*
1131 * Calibrate VDL
1132 */
1134 /* calib_once + calib_fast (for all BL) */
1135 ddr_write(DDR23PHY_BL3_VDL_CALIBRATE, 0x00000003);
1136 ddr_write(DDR23PHY_BL2_VDL_CALIBRATE, 0x00000003);
1137 ddr_write(DDR23PHY_BL1_VDL_CALIBRATE, 0x00000003);
1138 ddr_write(DDR23PHY_BL0_VDL_CALIBRATE, 0x00000003);
1140 li t2, 0x0000003;
1141 li t0, KSEG1ADDR(AI_DDRPHY_BASE)
1142 1: /* Wait until calib_idle == 1 and locked for all BL */
1143 lw t1, DDR23PHY_BL3_VDL_STATUS(t0)
1144 and t1, t1, t2;
1145 beq t1, zero, 1b
1146 nop
1147 lw t1, DDR23PHY_BL2_VDL_STATUS(t0)
1148 and t1, t1, t2;
1149 beq t1, zero, 1b
1150 nop
1151 lw t1, DDR23PHY_BL1_VDL_STATUS(t0)
1152 and t1, t1, t2;
1153 beq t1, zero, 1b
1154 nop
1155 lw t1, DDR23PHY_BL0_VDL_STATUS(t0)
1156 and t1, t1, t2;
1157 beq t1, zero, 1b
1158 nop
1160 /* VDL override */
1161 lw t1, DDR23PHY_BL0_VDL_STATUS(t0)
1162 srl t1, t1, 8
1163 andi t2, t1, 0x3f /* VDL step size */
1164 li t1, 1
1165 sll t1, 16
1166 or t2, t2, t1 /* ovr_en */
1167 li t1, 1
1168 sll t1, 20
1169 or t2, t2, t1 /* ovr_force */
1170 sw t2, DDR23PHY_STATIC_VDL_OVERRIDE(t0)
1172 #endif /* !CFG_QUICKTURN */
1174 /*
1175 * Memory controller PL341 initialization
1176 */
1178 /* De-assert core reset */
1179 move t0, a2 # AMEMC DMP regs
1180 ddr_write(AI_RESETCTRL, 0x00000000)
1182 move t0, a1 # AMEMC regs
1184 #ifdef CFG_DDR_REFRESH_PRD
1185 /* refresh_prd */
1186 ddr_write(PL341_refresh_prd, MEMCYCLES_MIN(CFG_DDR_REFRESH_PRD));
1187 #endif
1189 #ifdef CFG_DDR_T_MRD
1190 /* MRD time [6:0] */
1191 ddr_write(PL341_t_mrd, MEMCYCLES(CFG_DDR_T_MRD));
1192 #endif
1194 #ifdef CFG_DDR_T_RAS
1195 /* ras time [4:0] */
1196 ddr_write(PL341_t_ras, MEMCYCLES(CFG_DDR_T_RAS));
1197 #endif
1199 #ifdef CFG_DDR_T_RC
1200 /* t_rc [4:0] */
1201 ddr_write(PL341_t_rc, MEMCYCLES(CFG_DDR_T_RC));
1202 #endif
1204 #ifdef CFG_DDR_T_RCD
1205 /* t_rcd [4:0] */
1206 ddr_write(PL341_t_rcd, MEMCYCLES(CFG_DDR_T_RCD));
1207 #endif
1209 #ifdef CFG_DDR_T_RFC
1210 /* t_rfc [6:0] schedule_rfc[14:8] */
1211 ddr_write(PL341_t_rfc,
1212 ((MEMCYCLES(CFG_DDR_T_RFC) - 3) << 8) | MEMCYCLES(CFG_DDR_T_RFC));
1213 #endif
1215 #ifdef CFG_DDR_T_RP
1216 /* t_rp [3:0] */
1217 ddr_write(PL341_t_rp,
1218 ((MEMCYCLES(CFG_DDR_T_RP) - 3) << 8) | MEMCYCLES(CFG_DDR_T_RP));
1219 #endif
1221 #ifdef CFG_DDR_T_RRD
1222 /* t_rrd [2:0] */
1223 ddr_write(PL341_t_rrd, MEMCYCLES(CFG_DDR_T_RRD));
1224 #endif
1226 #ifdef CFG_DDR_T_WR
1227 /* t_wr */
1228 ddr_write(PL341_t_wr, MEMCYCLES(CFG_DDR_T_WR));
1229 #endif
1231 #ifdef CFG_DDR_T_WTR
1232 /* t_wtr */
1233 ddr_write(PL341_t_wtr, MEMCYCLES(CFG_DDR_T_WTR));
1234 #endif
1236 #ifdef CFG_DDR_T_XP
1237 /* t_xp[7:0] */
1238 ddr_write(PL341_t_xp, MEMCYCLES(CFG_DDR_T_XP));
1239 #endif
1241 #ifdef CFG_DDR_T_XSR
1242 /* t_xsr[7:0] */
1243 ddr_write(PL341_t_xsr, MEMCYCLES(CFG_DDR_T_XSR));
1244 #endif
1246 #ifdef CFG_DDR_T_ESR
1247 /* t_esr[7:0] */
1248 ddr_write(PL341_t_esr, MEMCYCLES(CFG_DDR_T_ESR));
1249 #endif
1251 #ifdef CFG_DDR_T_FAW
1252 /* t_faw */
1253 ddr_write(PL341_t_faw,
1254 ((MEMCYCLES(CFG_DDR_T_FAW) - 3) << 8) | MEMCYCLES(CFG_DDR_T_FAW));
1255 #endif
1257 /* Check if sdram_config is nonzero */
1258 and t1, s0, 0xffff
1259 bne t1, $0, sdram_mem_cfg
1260 nop
1262 /* sdram_config is 0, configure by code-default values */
1263 /* Figure out if it's a low cost package */
1264 andi t1, s1, 0x03
1266 /* Standard package, assume 1024-column, 32-bit, 8-bank DDR */
1267 beq t1, $0, sdram_mem_cfg
1268 li s0, (0x0140 | CFG_DDR_CAS_LATENCY)
1270 /* Low cost package, assume 1024-column, 16-bit, 8-bank DDR */
1271 li s0, (0x01c0 | CFG_DDR_CAS_LATENCY)
1273 sdram_mem_cfg:
1274 /* CAS Latency:
1275 * sdram_config[2:0]: CAS latency
1276 * PL341_cas_latency[3:1]: CL range from 2 to 6
1277 * PL341_write_latency[2:0]: CL - 1
1278 */
1279 andi t1, s0, 0x07
1280 sll t2, t1, 1
1281 sw t2, PL341_cas_latency(a1)
1282 subu t2, t1, 1
1283 sw t2, PL341_write_latency(a1)
1285 /* PL341_memory_cfg: Rows and Columns */
1286 lw t2, PL341_memory_cfg(a1) # Read PL341_memory_cfg
1288 /* Columns:
1289 * sdram_config[10:8]: 0=2048; 1=1024; 2=512; 3=256 columns
1290 * PL341_memory_cfg[2:0]: 1=9-bit; 2=10-bit; 3=11-bit; Others=Reserved.
1291 */
1292 li t3, ~0x7 # columns(bit2:0)
1293 and t2, t2, t3 # clear column
1294 srl t1, s0, 8 # Column fields from sdram_config s0(bit10:8)
1295 andi t1, t1, 0x07
1296 li t3, 0x3
1297 subu t1, t3, t1
1298 andi t1, t1, 0x07
1299 or t2, t2, t1
1300 sw t2, PL341_memory_cfg(a1)
1302 /* PL341_memory_cfg2: Bus width and Banks */
1303 lw t2, PL341_memory_cfg2(a1) # Read PL341_memory_cfg2
1305 /* Low cost package is 16-bit bus */
1306 andi t1, s1, 0x03
1307 li t3, ~0xc0
1308 bne t1, $0, 2f # nonzero: low cost package with 16-bit bus
1309 and t2, t2, t3 # Clear bit[7:6] to work in 16-bit mode
1311 /* Bus width:
1312 * sdram_config[7]: 0 default bus width, 1: reduced width
1313 * PL341_memory_cfg2[7:6]: 00 for 16bit, 01=32bit, 10=64bit, 11=reserved
1314 */
1315 andi t1, s0, 0x80
1316 bne t1, $0, 2f # Work in 16-bit mode
1317 nop
1318 or t2, t2, 0x40 # Set bit[7:6] to 32-bit mode
1319 2:
1320 /* Banks:
1321 * sdram_config[6]: 0 for 4 banks, 1 for 8 banks
1322 * PL341_memory_cfg2[5:4]: 00 for 4 banks, 11 for 8 banks
1323 */
1324 andi t1, s0, 0x40 # Bank configuration
1325 li t3, ~0x30
1326 beq t1, $0, 1f
1327 and t2, t2, t3 # Clear bit[5:4] to work in 4-bank mode
1328 or t2, t2, 0x30 # Set bit[5:4] to 11 for 8-bank mode
1329 1:
1330 sw t2, PL341_memory_cfg2(a1);
1332 /* chip0 configuration */
1333 ddr_write(PL341_chip_0_cfg, 0x00000000);
1335 /* user_config0 */
1336 ddr_write(PL341_user_config0, 0x00000003);
1338 /*
1339 * DDR2 chip initialization
1340 */
1342 /* Issue NOP */
1343 ddr_write(PL341_direct_cmd, MCHIP_CMD_NOP);
1345 /* issue precharge all */
1346 ddr_write(PL341_direct_cmd, MCHIP_CMD_PRECHARGE_ALL);
1348 /* Set EMR2 */
1349 ddr_write(PL341_direct_cmd, MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(2));
1351 /* Set EMR3 */
1352 ddr_write(PL341_direct_cmd, MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(3));
1354 /* DLL Enable */
1355 ddr_write(PL341_direct_cmd,
1356 MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(1) |
1357 MCHIP_EMR1_DLL_DISABLE(0)
1358 );
1360 /* DLL Reset */
1361 /* Set CAS to external memory devices */
1362 lw t1, PL341_cas_latency(a1) # CAS value in bit3:1
1363 li t2, (MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(0) | \
1364 MCHIP_MR_WRITE_RECOVERY(MEMCYCLES(CFG_DDR_T_WR)) | \
1365 MCHIP_MR_DLL_RESET(1) | MCHIP_MR_BURST_LENGTH)
1366 sll t1, t1, 3 # Shift to bit6:4 for DDR MRS register
1367 or t2, t2, t1
1368 sw t2, PL341_direct_cmd(a1)
1370 /* issue precharge all */
1371 ddr_write(PL341_direct_cmd, MCHIP_CMD_PRECHARGE_ALL);
1373 /* auto-refresh 2 times */
1374 ddr_write(PL341_direct_cmd, MCHIP_CMD_AUTO_REFRESH);
1375 ddr_write(PL341_direct_cmd, MCHIP_CMD_AUTO_REFRESH);
1377 /* DLL Reset=0 (Un-Reset DLL) */
1378 and t2, t2, ~MCHIP_MR_DLL_RESET(1)
1379 sw t2, PL341_direct_cmd(a1)
1381 /* DLL Enable & RTT 75ohm */
1382 ddr_write(PL341_direct_cmd,
1383 MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(1) |
1384 MCHIP_EMR1_DLL_DISABLE(0) | MCHIP_EMR1_RTT_75_OHM |
1385 MCHIP_EMR1_OCD_CALI_EXIT
1386 );
1388 /* OCD Defaults */
1389 ddr_write(PL341_direct_cmd,
1390 MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(1) |
1391 MCHIP_EMR1_DLL_DISABLE(0) | MCHIP_EMR1_RTT_75_OHM |
1392 MCHIP_EMR1_OCD_CALI_DEFAULT
1393 );
1395 /* OCD Exit */
1396 ddr_write(PL341_direct_cmd,
1397 MCHIP_CMD_MODE_REG | MCHIP_MODEREG_SEL(1) |
1398 MCHIP_EMR1_DLL_DISABLE(0) | MCHIP_EMR1_RTT_75_OHM |
1399 MCHIP_EMR1_OCD_CALI_EXIT
1400 );
1402 /* set MEMC to GO */
1403 ddr_write(PL341_memc_cmd, 0);
1404 nop
1405 nop
1407 jr ra
1408 nop
1410 .set reorder
1411 END(ai_amemcinit)