release/src-rt/include/sbusbd.h

   1 /*
   2  * Broadcom SiliconBackplane USB device core support
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
   8  * the contents of this file may not be disclosed to third parties, copied
   9  * or duplicated in any form, in whole or in part, without the prior
  10  * written permission of Broadcom Corporation.
  11  *
  12  * $Id: sbusbd.h,v 13.15 2010-01-13 09:21:06 Exp $
  13  */
  14
  15 #ifndef _usbdev_sb_h_
  16 #define _usbdev_sb_h_
  17
  18 #include <typedefs.h>
  19 #include <sbconfig.h>
  20 #include <sbhnddma.h>
  21
  22 /*
  23  * Control endpoint 0 maps to DMA engine 0
  24  * IN endpoints 1-4 map to transmit side of DMA engines 1-4
  25  * OUT endpoints 5-8 map to receive side DMA engines 1-4
  26  */
  27 #define DMA_MAX 5
  28 #define EP_MAX  9
  29 #define EP2DMA(ep) (((ep) < DMA_MAX) ? (ep) : ((ep) - DMA_MAX + 1))
  30 #define DMA2EP(i, dir) (((i) == 0) ? 0 : ((dir) == EP_DIR_IN ? (i) : ((i) + DMA_MAX - 1)))
  31
  32 /* rev 3 or higher has a dedicated DMA engine for Setup tokens */
  33 #define SETUP_DMA               5
  34 #define SETUP_DMA_DEPTH         4
  35
  36 /* cpp contortions to concatenate w/arg prescan */
  37 #ifndef PAD
  38 #define _PADLINE(line)  pad ## line
  39 #define _XSTR(line)     _PADLINE(line)
  40 #define PAD             _XSTR(__LINE__)
  41 #endif  /* PAD */
  42
  43 /* dma64 corerev >= 7 */
  44 typedef volatile struct {
  45         dma64regs_t     dmaxmt;         /* dma tx */
  46         uint32 PAD[2];
  47         dma64regs_t     dmarcv;         /* dma rx */
  48         uint32 PAD[2];
  49 } dma64_t;
  50
  51 /* Host interface registers */
  52 typedef volatile struct {
  53         /* Device control */
  54         uint32 devcontrol;                      /* DevControl, 0x000, rev 2 */
  55         uint32 devstatus;                       /* DevStatus,  0x004, rev 2 */
  56         uint32 PAD[1];
  57         uint32 biststatus;                      /* BISTStatus, 0x00C, rev 2 */
  58
  59         /* USB control */
  60         uint32 usbsetting;                      /* USBSetting, 0x010, rev 2 */
  61         uint32 usbframe;                        /* USBFrame,   0x014, rev 2 */
  62         uint32 PAD[2];
  63
  64         /* 2nd level DMA int status/mask, IntStatus0-4, IntMask0-4 */
  65         struct {
  66                 uint32 status;
  67                 uint32 mask;
  68         } dmaint[DMA_MAX];                      /* 0x020 - 0x44, rev 2 */
  69
  70         /* Top level interrupt status and mask */
  71         uint32 usbintstatus;                    /* IntStatus, 0x048, rev 2 */
  72         uint32 usbintmask;                      /* IntMask,   0x04C, rev 2 */
  73
  74         /* Endpoint status */
  75         uint32 epstatus;                        /* CtrlOutStatus, 0x050, rev 2 */
  76         uint32 txfifowtermark;                  /* bytes threshold before commit tx, POR=0x100 */
  77
  78         /* Dedicated 2nd level DMA int status/mask for Setup Data, rev 3 */
  79         uint32 sdintstatus;                     /* IntStatus5, 0x58, rev 3 */
  80         uint32 sdintmask;                       /* IntMask5, 0x5C, rev 3 */
  81         uint32 PAD[40];
  82
  83         /* Lazy interrupt control, IntRcv0-4Lazy, 0x100-0x110, rev 2 */
  84         uint32 intrcvlazy[DMA_MAX];
  85         /* Setup token Lazy interrupt control, rev 3 */
  86         uint32 sdintrcvlazy;                    /* IntRcvLazy5 (Setup Data), 0x114, rev 3 */
  87         uint32 PAD[50];
  88
  89         uint32 clkctlstatus;                    /* ClockCtlStatus, 0x1E0, rev 3 */
  90         uint32 PAD[7];
  91
  92         /* DMA engine regs, 0x200-0x29C, rev 2 */
  93         dma32regp_t dmaregs[DMA_MAX];
  94         dma32diag_t dmafifo;                    /* fifo diag regs, 0x2A0-0x2AC */
  95         uint32 PAD[1];
  96
  97         /* Endpoint byte counters, EPByteCount0-8, 0x2B4-0x2D4, rev 2 */
  98         uint32 epbytes[EP_MAX];
  99         uint32 PAD[2];
 100
 101         uint32 hsicphyctrl1;            /* HSICPhyCtrl1 0x2e0, rev 10 */
 102         uint32 PAD[15];
 103
 104         uint32 mdio_ctl;                /* mdio_ctl, 0x320 */
 105         uint32 mdio_data;               /* mdio_data, 0x324 */
 106         uint32 phymiscctl;              /* PhyMiscCtl, 0x328, rev 4 */
 107         uint32 PAD[5];
 108
 109         /* Dedicated Setup Data DMA engine, 0x340-0x35C, rev 3 */
 110         dma32regp_t sddmaregs;
 111         uint32 PAD[40];
 112
 113         /* Core registers */
 114         uint32 commandaddr;                     /* CommmandAddress, 0x400, rev 2 */
 115         /* EndPointConfig0-8, 0x404-0x424, rev 2 */
 116         uint32 epinfo[EP_MAX];
 117         uint32 PAD[54];
 118
 119         /*
 120          * dma64 registers, including Setup Data DMA engine, for corerev >= 7
 121          * 0ffsets 0x500 to 0x674.
 122          */
 123         dma64_t dma64regs[DMA_MAX + 1];
 124         uint32 PAD[544];
 125
 126
 127         /* Sonics SiliconBackplane registers */
 128         sbconfig_t sbconfig;
 129 } usbdev_sb_regs_t;
 130
 131 /* Device control bits */
 132 #define DC_RS                   (1L << 0)       /* Device Reset */
 133 #define DC_PL                   (1L << 1)       /* USB11D: PLL Reset, USB20D PLL Power Down */
 134 #define DC_US                   (1L << 2)       /* USB Ready */
 135 #define DC_ST                   (1L << 3)       /* Stall */
 136 #define DC_RM                   (1L << 4)       /* Resume */
 137 #define DC_SD                   (1L << 5)       /* Set Descriptor */
 138 #define DC_SC                   (1L << 6)       /* Sync Frame */
 139 #define DC_SP                   (1L << 7)       /* Self Power */
 140 #define DC_RW                   (1L << 8)       /* Remote Wakeup */
 141 #define DC_AR                   (1L << 9)       /* App Reset */
 142
 143 /* USB20 device specific bits */
 144 #define DC_UP                   (1L << 10)      /* UTMI Power Down */
 145 #define DC_AP                   (1L << 11)      /* Analog Power Down */
 146 #define DC_PR                   (1L << 12)      /* Phy Reset */
 147 #define DC_SS_MASK              0x6000          /* Speed Select bits */
 148 #define DC_SS_SHIFT             13
 149 #define DC_SS_FS                1               /* Full Speed */
 150 #define DC_SS_HS                0               /* High Speed */
 151 #define DC_PE                   (1L << 15)      /* Phy Error Detect Enable */
 152 #define DC_NZLP_MASK            0x30000         /* Non-zero length Packet Stall */
 153 #define DC_NZLP_SHIFT           16
 154 #define DC_EH                   (1L << 18)      /* Ep0 Halt Command Stall */
 155 #define DC_HSTC_MASK            0x380000        /* HS Timeout Calibration */
 156 #define DC_HSTC_SHIFT           19
 157 #define DC_FSTC_MASK            0x1c00000       /* FS Timeout Calibration */
 158 #define DC_FSTC_SHIFT           22
 159 #define DC_DC                   (1L << 25)      /* Soft Disconnect */
 160 #define DC_UR                   (1L << 26)      /* UTMI Soft Reset */
 161 #define DC_UL                   (1L << 27)      /* App ULPI Select */
 162 #define DC_ULD                  (1L << 28)      /* App ULPI DDR Select */
 163 #define DC_SS(n)                (((uint32)(n) << DC_SS_SHIFT) & DC_SS_MASK)
 164
 165 /* Device status bits */
 166 #define DS_SP                   (1L << 0)       /* Suspend */
 167 #define DS_RS                   (1L << 1)       /* Reset */
 168 #define DS_PE                   (1L << 4)       /* Phy Error (USB20D) */
 169 #define DS_DS_MASK              0xC             /* Device Operating Speed (USB20D) */
 170 #define DS_DS_SHIFT             2
 171 #define DS_DS_HSCAP_HSMODE      0               /* HS cap, operating in HS mode */
 172 #define DS_DS_HSCAP_FSMODE      1               /* HS cap, operating in FS mode */
 173 #define DS_DS_FSCAP_FSMODE      3               /* FS cap, operating in FS mode */
 174 #define DS_DS_HS                (DS_DS_HSCAP_HSMODE << DS_DS_SHIFT)
 175 #define DS_PHYMODE_MASK         0x0300
 176 #define DS_PHYMODE_SHIFT        8
 177 #define DS_PHYMODE_NORMAL       0               /* normal operation */
 178 #define DS_PHYMODE_NONDRIVING   1               /* nob-driving */
 179 #define DS_PHYMODE_NOSTUFF_NZI  2               /* disable bit stuffing and NZI */
 180
 181 /* USB setting bits */
 182 #define USB_CF_MASK             0x00f           /* Configuration */
 183 #define USB_CF_SHIFT            0
 184 #define USB_CF(n)               (((uint32)(n) << USB_CF_SHIFT) & USB_CF_MASK)
 185 #define USB_IF_MASK             0x0f0           /* Interface */
 186 #define USB_IF_SHIFT            4
 187 #define USB_IF(n)               (((uint32)(n) << USB_IF_SHIFT) & USB_IF_MASK)
 188 #define USB_AI_MASK             0xf00           /* Alternate Interface */
 189 #define USB_AI_SHIFT            8
 190 #define USB_AI(n)               (((uint32)(n) << USB_AI_SHIFT) & USB_AI_MASK)
 191
 192 /* DMA interrupt bits */
 193 #define I_PC                    (1L << 10)      /* descriptor error */
 194 #define I_PD                    (1L << 11)      /* data error */
 195 #define I_DE                    (1L << 12)      /* Descriptor protocol Error */
 196 #define I_RU                    (1L << 13)      /* Receive descriptor Underflow */
 197 #define I_RO                    (1L << 14)      /* Receive fifo Overflow */
 198 #define I_XU                    (1L << 15)      /* Transmit fifo Underflow */
 199 #define I_RI                    (1L << 16)      /* Receive Interrupt */
 200 #define I_XI                    (1L << 24)      /* Transmit Interrupt */
 201 #define I_ERRORS                (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
 202
 203 /* USB interrupt status and mask bits */
 204 #define I_SETUP_MASK            0x0000003f      /* Endpoint Setup interrupt (4:0) + Ctrl Req */
 205 #define I_SETUP_SHIFT           0
 206 #define I_SETUP(n)              (1L << ((n) + I_SETUP_SHIFT))
 207 #define I_DEV_REQ               (1L << 5)       /* SetupDataPresent on Setup DMA engine, rev 3 */
 208 #define I_DATAERR_MASK          0x0003fe00      /* Endpoint Data Error (17:9) */
 209 #define I_DATAERR_SHIFT         9
 210 #define I_DATAERR(n)            (1L << ((n) + I_DATAERR_SHIFT))
 211 #define I_SUS_RES               (1L << 18)      /* Suspend/Resume interrupt */
 212 #define I_RESET                 (1L << 19)      /* USB Reset interrupt */
 213 #define I_SOF                   (1L << 20)      /* USB Start of Frame interrupt */
 214 #define I_CFG                   (1L << 21)      /* Set Configuration interrupt */
 215 #define I_DMA_MASK              0x07c00000      /* DMA interrupt pending (26:22) */
 216 #define I_DMA_SHIFT             22
 217 #define I_DMA(n)                (1L << ((n) + I_DMA_SHIFT))
 218 #define I_TXDONE_MASK           0xf8000000      /* Transmit complete (31:27) */
 219 #define I_TXDONE_SHIFT          27
 220 #define I_TXDONE(n)             (1L << ((n) + I_TXDONE_SHIFT))
 221
 222 /* Interrupt receive lazy */
 223 #define IRL_TO_MASK             0x00ffffff      /* TimeOut (23:0) */
 224 #define IRL_FC_MASK             0xff000000      /* Frame Count (31:24) */
 225 #define IRL_FC_SHIFT            24
 226 #define IRL_FC(n)               (((uint32)(n) << IRL_FC_SHIFT) & IRL_FC_MASK)
 227
 228 /* ClkCtlStatus bits defined in sbconfig.h */
 229
 230 /* hsicphyctrl1 "PLL lock count" and "PLL reset count" bits */
 231 #define PLL_LOCK_CT_MASK        0x0f000000
 232 #define PLL_LOCK_CT_SHIFT       24
 233 #define PLL_RESET_CT_MASK       0x30000000
 234 #define PLL_RESET_CT_SHIFT      28
 235
 236 /* phymiscctrl */
 237 #define PMC_PLL_SUSP_EN         (1 << 0)
 238 #define PMC_PLL_CAL_EN          (1 << 1)
 239
 240 /* Endpoint status bits */
 241 #define EPS_STALL_MASK          0x0000001f      /* Stall on Status IN (4:0) */
 242 #define EPS_STALL_SHIFT         0
 243 #define EPS_STALL(n)            (1L << ((n) + EPS_STALL_SHIFT))
 244 #define EPS_HALT_MASK           0x00003fe0      /* Stall on Data IN (13:5) */
 245 #define EPS_HALT_SHIFT          5
 246 #define EPS_HALT(n)             (1L << ((n) + EPS_HALT_SHIFT))
 247 #define EPS_SETUP_LOST_MASK     0x0007c000      /* Setup Lost (18:14) */
 248 #define EPS_SETUP_LOST_SHIFT    14
 249 #define EPS_SETUP_LOST(n)       (1L << ((n) + EPS_SETUP_LOST_SHIFT))
 250 #define EPS_DONE_MASK           0x00f80000      /* Stop NAKing Status IN (23:19) */
 251 #define EPS_DONE_SHIFT          19
 252 #define EPS_DONE(n)             (1L << ((n) + EPS_DONE_SHIFT))
 253
 254 /* Endpoint info bits */
 255 #define EP_EN_MASK              0x0000000f      /* Endpoint Number (logical) */
 256 #define EP_EN_SHIFT             0
 257 #define EP_EN(n)                (((uint32)(n) << EP_EN_SHIFT) & EP_EN_MASK)
 258 #define EP_DIR_MASK             0x00000010      /* Endpoint Direction (4) */
 259 #define EP_DIR_OUT              0x00000000      /* OUT Endpoint */
 260 #define EP_DIR_IN               0x00000010      /* IN Endpoint */
 261 #define EP_TYPE_MASK            0x00000060      /* Endpoint Type (6:5) */
 262 #define EP_CONTROL              0x00000000      /* Control Endpoint */
 263 #define EP_ISO                  0x00000020      /* Isochronous Endpoint */
 264 #define EP_BULK                 0x00000040      /* Bulk Endpoint */
 265 #define EP_INTR                 0x00000060      /* Interrupt Endpoint */
 266 #define EP_CF_MASK              0x00000780      /* Configuration Number (10:7) */
 267 #define EP_CF_SHIFT             7
 268 #define EP_CF(n)                (((uint32)(n) << EP_CF_SHIFT) & EP_CF_MASK)
 269 #define EP_IF_MASK              0x00007800      /* Interface Number (14:11) */
 270 #define EP_IF_SHIFT             11
 271 #define EP_IF(n)                (((uint32)(n) << EP_IF_SHIFT) & EP_IF_MASK)
 272 #define EP_AI_MASK              0x00078000      /* Alternate Interface Number (18:15) */
 273 #define EP_AI_SHIFT             15
 274 #define EP_AI(n)                (((uint32)(n) << EP_AI_SHIFT) & EP_AI_MASK)
 275 #define EP_MPS_MASK             0x1ff80000      /* Maximum Packet Size (28:19) */
 276 #define EP_MPS_SHIFT            19
 277 #define EP_MPS(n)               (((uint32)(n) << EP_MPS_SHIFT) & EP_MPS_MASK)
 278
 279 /* rx header */
 280 typedef volatile struct {
 281         uint16 len;
 282         uint16 flags;
 283 } usbdev_sb_rxh_t;
 284
 285 /* rx header flags */
 286 #define RXF_SETUP               0x0001          /* rev 2 */
 287 #define RXF_BAD                 0x0002          /* rev 2 */
 288 #define SETUP_TAG_SHIFT         2               /* rev 3 */
 289 #define SETUP_TAG_MASK          0x000c          /* rev 3 */
 290 #define EP_ID_SHIFT             4               /* rev 3 */
 291 #define EP_ID_MASK              0x00f0          /* rev 3 */
 292
 293 #define USB20DREV_IS(var, val)  ((var) == (val))
 294 #define USB20DREV_GE(var, val)  ((var) >= (val))
 295 #define USB20DREV_GT(var, val)  ((var) > (val))
 296 #define USB20DREV_LT(var, val)  ((var) < (val))
 297 #define USB20DREV_LE(var, val)  ((var) <= (val))
 298
 299 #define USB20DDMAREG(ch, direction, fifonum)    (USB20DREV_LT(ch->rev, 7) ? \
 300         ((direction == DMA_TX) ? \
 301                 (void*)(uintptr)&(ch->regs->dmaregs[fifonum].xmt) : \
 302                 (void*)(uintptr)&(ch->regs->dmaregs[fifonum].rcv)) : \
 303         ((direction == DMA_TX) ? \
 304                 (void*)(uintptr)&(ch->regs->dma64regs[fifonum].dmaxmt) : \
 305                 (void*)(uintptr)&(ch->regs->dma64regs[fifonum].dmarcv)))
 306
 307 #endif  /* _usbdev_sb_h_ */