release/src-rt/include/sbsdram.h

   1 /*
   2  * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: sbsdram.h,v 13.18 2006-03-29 02:14:24 Exp $
  19  */
  20
  21 #ifndef _SBSDRAM_H
  22 #define _SBSDRAM_H
  23
  24 #ifndef _LANGUAGE_ASSEMBLY
  25
  26 /* Sonics side: SDRAM core registers */
  27 typedef volatile struct sbsdramregs {
  28         uint32  initcontrol;    /* Generates external SDRAM initialization sequence */
  29         uint32  config;         /* Initializes external SDRAM mode register */
  30         uint32  refresh;        /* Controls external SDRAM refresh rate */
  31         uint32  pad1;
  32         uint32  pad2;
  33 } sbsdramregs_t;
  34
  35 #endif /* !_LANGUAGE_ASSEMBLY */
  36
  37 /* SDRAM initialization control (initcontrol) register bits */
  38 #define SDRAM_CBR       0x0001  /* Writing 1 generates refresh cycle and toggles bit */
  39 #define SDRAM_PRE       0x0002  /* Writing 1 generates precharge cycle and toggles bit */
  40 #define SDRAM_MRS       0x0004  /* Writing 1 generates mode register select cycle and toggles bit */
  41 #define SDRAM_EN        0x0008  /* When set, enables access to SDRAM */
  42 #define SDRAM_16Mb      0x0000  /* Use 16 Megabit SDRAM */
  43 #define SDRAM_64Mb      0x0010  /* Use 64 Megabit SDRAM */
  44 #define SDRAM_128Mb     0x0020  /* Use 128 Megabit SDRAM */
  45 #define SDRAM_RSVMb     0x0030  /* Use special SDRAM */
  46 #define SDRAM_RST       0x0080  /* Writing 1 causes soft reset of controller */
  47 #define SDRAM_SELFREF   0x0100  /* Writing 1 enables self refresh mode */
  48 #define SDRAM_PWRDOWN   0x0200  /* Writing 1 causes controller to power down */
  49 #define SDRAM_32BIT     0x0400  /* When set, indicates 32 bit SDRAM interface */
  50 #define SDRAM_9BITCOL   0x0800  /* When set, indicates 9 bit column */
  51
  52 /* SDRAM configuration (config) register bits */
  53 #define SDRAM_BURSTFULL 0x0000  /* Use full page bursts */
  54 #define SDRAM_BURST8    0x0001  /* Use burst of 8 */
  55 #define SDRAM_BURST4    0x0002  /* Use burst of 4 */
  56 #define SDRAM_BURST2    0x0003  /* Use burst of 2 */
  57 #define SDRAM_CAS3      0x0000  /* Use CAS latency of 3 */
  58 #define SDRAM_CAS2      0x0004  /* Use CAS latency of 2 */
  59
  60 /* SDRAM refresh control (refresh) register bits */
  61 #define SDRAM_REF(p)    (((p)&0xff) | SDRAM_REF_EN)     /* Refresh period */
  62 #define SDRAM_REF_EN    0x8000          /* Writing 1 enables periodic refresh */
  63
  64 /* SDRAM Core default Init values (OCP ID 0x803) */
  65 #define SDRAM_INIT      MEM4MX16X2
  66 #define SDRAM_CONFIG    SDRAM_BURSTFULL
  67 #define SDRAM_REFRESH   SDRAM_REF(0x40)
  68
  69 #define MEM1MX16        0x009   /* 2 MB */
  70 #define MEM1MX16X2      0x409   /* 4 MB */
  71 #define MEM2MX8X2       0x809   /* 4 MB */
  72 #define MEM2MX8X4       0xc09   /* 8 MB */
  73 #define MEM2MX32        0x439   /* 8 MB */
  74 #define MEM4MX16        0x019   /* 8 MB */
  75 #define MEM4MX16X2      0x419   /* 16 MB */
  76 #define MEM8MX8X2       0x819   /* 16 MB */
  77 #define MEM8MX16        0x829   /* 16 MB */
  78 #define MEM4MX32        0x429   /* 16 MB */
  79 #define MEM8MX8X4       0xc19   /* 32 MB */
  80 #define MEM8MX16X2      0xc29   /* 32 MB */
  81
  82 #endif  /* _SBSDRAM_H */