release/src-rt/include/pcie_core.h

   1 /*
   2  * BCM43XX PCIE core hardware definitions.
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: pcie_core.h,v 13.7.108.2 2010-05-24 06:41:20 Exp $
  19  */
  20 #ifndef _PCIE_CORE_H
  21 #define _PCIE_CORE_H
  22
  23 /* cpp contortions to concatenate w/arg prescan */
  24 #ifndef PAD
  25 #define _PADLINE(line)  pad ## line
  26 #define _XSTR(line)     _PADLINE(line)
  27 #define PAD             _XSTR(__LINE__)
  28 #endif
  29
  30 /* PCIE Enumeration space offsets */
  31 #define  PCIE_CORE_CONFIG_OFFSET        0x0
  32 #define  PCIE_FUNC0_CONFIG_OFFSET       0x400
  33 #define  PCIE_FUNC1_CONFIG_OFFSET       0x500
  34 #define  PCIE_FUNC2_CONFIG_OFFSET       0x600
  35 #define  PCIE_FUNC3_CONFIG_OFFSET       0x700
  36 #define  PCIE_SPROM_SHADOW_OFFSET       0x800
  37 #define  PCIE_SBCONFIG_OFFSET           0xE00
  38
  39 /* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
  40 #define PCIE_DEV_BAR0_SIZE              0x4000
  41 #define PCIE_BAR0_WINMAPCORE_OFFSET     0x0
  42 #define PCIE_BAR0_EXTSPROM_OFFSET       0x1000
  43 #define PCIE_BAR0_PCIECORE_OFFSET       0x2000
  44 #define PCIE_BAR0_CCCOREREG_OFFSET      0x3000
  45
  46 /* different register spaces to access thr'u pcie indirect access */
  47 #define PCIE_CONFIGREGS         1               /* Access to config space */
  48 #define PCIE_PCIEREGS           2               /* Access to pcie registers */
  49
  50 /* SB side: PCIE core and host control registers */
  51 typedef struct sbpcieregs {
  52         uint32 control;         /* host mode only */
  53         uint32 PAD[2];
  54         uint32 biststatus;      /* bist Status: 0x00C */
  55         uint32 gpiosel;         /* PCIE gpio sel: 0x010 */
  56         uint32 gpioouten;       /* PCIE gpio outen: 0x14 */
  57         uint32 PAD[2];
  58         uint32 intstatus;       /* Interrupt status: 0x20 */
  59         uint32 intmask;         /* Interrupt mask: 0x24 */
  60         uint32 sbtopcimailbox;  /* sb to pcie mailbox: 0x028 */
  61         uint32 PAD[53];
  62         uint32 sbtopcie0;       /* sb to pcie translation 0: 0x100 */
  63         uint32 sbtopcie1;       /* sb to pcie translation 1: 0x104 */
  64         uint32 sbtopcie2;       /* sb to pcie translation 2: 0x108 */
  65         uint32 PAD[5];
  66
  67         /* pcie core supports in direct access to config space */
  68         uint32 configaddr;      /* pcie config space access: Address field: 0x120 */
  69         uint32 configdata;      /* pcie config space access: Data field: 0x124 */
  70
  71         /* mdio access to serdes */
  72         uint32 mdiocontrol;     /* controls the mdio access: 0x128 */
  73         uint32 mdiodata;        /* Data to the mdio access: 0x12c */
  74
  75         /* pcie protocol phy/dllp/tlp register indirect access mechanism */
  76         uint32 pcieindaddr;     /* indirect access to the internal register: 0x130 */
  77         uint32 pcieinddata;     /* Data to/from the internal regsiter: 0x134 */
  78
  79         uint32 clkreqenctrl;    /* >= rev 6, Clkreq rdma control : 0x138 */
  80         uint32 PAD[177];
  81         uint32 pciecfg[4][64];  /* 0x400 - 0x7FF, PCIE Cfg Space */
  82         uint16 sprom[64];       /* SPROM shadow Area */
  83 } sbpcieregs_t;
  84
  85 /* PCI control */
  86 #define PCIE_RST_OE     0x01    /* When set, drives PCI_RESET out to pin */
  87 #define PCIE_RST        0x02    /* Value driven out to pin */
  88
  89 #define PCIE_CFGADDR    0x120   /* offsetof(configaddr) */
  90 #define PCIE_CFGDATA    0x124   /* offsetof(configdata) */
  91
  92 /* Interrupt status/mask */
  93 #define PCIE_INTA       0x01    /* PCIE INTA message is received */
  94 #define PCIE_INTB       0x02    /* PCIE INTB message is received */
  95 #define PCIE_INTFATAL   0x04    /* PCIE INTFATAL message is received */
  96 #define PCIE_INTNFATAL  0x08    /* PCIE INTNONFATAL message is received */
  97 #define PCIE_INTCORR    0x10    /* PCIE INTCORR message is received */
  98 #define PCIE_INTPME     0x20    /* PCIE INTPME message is received */
  99
 100 /* SB to PCIE translation masks */
 101 #define SBTOPCIE0_MASK  0xfc000000
 102 #define SBTOPCIE1_MASK  0xfc000000
 103 #define SBTOPCIE2_MASK  0xc0000000
 104
 105 /* Access type bits (0:1) */
 106 #define SBTOPCIE_MEM    0
 107 #define SBTOPCIE_IO     1
 108 #define SBTOPCIE_CFG0   2
 109 #define SBTOPCIE_CFG1   3
 110
 111 /* Prefetch enable bit 2 */
 112 #define SBTOPCIE_PF             4
 113
 114 /* Write Burst enable for memory write bit 3 */
 115 #define SBTOPCIE_WR_BURST       8
 116
 117 /* config access */
 118 #define CONFIGADDR_FUNC_MASK    0x7000
 119 #define CONFIGADDR_FUNC_SHF     12
 120 #define CONFIGADDR_REG_MASK     0x0FFF
 121 #define CONFIGADDR_REG_SHF      0
 122
 123 #define PCIE_CONFIG_INDADDR(f, r)       ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \
 124                                          (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF))
 125
 126 /* PCIE protocol regs Indirect Address */
 127 #define PCIEADDR_PROT_MASK      0x300
 128 #define PCIEADDR_PROT_SHF       8
 129 #define PCIEADDR_PL_TLP         0
 130 #define PCIEADDR_PL_DLLP        1
 131 #define PCIEADDR_PL_PLP         2
 132
 133 /* PCIE protocol PHY diagnostic registers */
 134 #define PCIE_PLP_MODEREG                0x200 /* Mode */
 135 #define PCIE_PLP_STATUSREG              0x204 /* Status */
 136 #define PCIE_PLP_LTSSMCTRLREG           0x208 /* LTSSM control */
 137 #define PCIE_PLP_LTLINKNUMREG           0x20c /* Link Training Link number */
 138 #define PCIE_PLP_LTLANENUMREG           0x210 /* Link Training Lane number */
 139 #define PCIE_PLP_LTNFTSREG              0x214 /* Link Training N_FTS */
 140 #define PCIE_PLP_ATTNREG                0x218 /* Attention */
 141 #define PCIE_PLP_ATTNMASKREG            0x21C /* Attention Mask */
 142 #define PCIE_PLP_RXERRCTR               0x220 /* Rx Error */
 143 #define PCIE_PLP_RXFRMERRCTR            0x224 /* Rx Framing Error */
 144 #define PCIE_PLP_RXERRTHRESHREG         0x228 /* Rx Error threshold */
 145 #define PCIE_PLP_TESTCTRLREG            0x22C /* Test Control reg */
 146 #define PCIE_PLP_SERDESCTRLOVRDREG      0x230 /* SERDES Control Override */
 147 #define PCIE_PLP_TIMINGOVRDREG          0x234 /* Timing param override */
 148 #define PCIE_PLP_RXTXSMDIAGREG          0x238 /* RXTX State Machine Diag */
 149 #define PCIE_PLP_LTSSMDIAGREG           0x23C /* LTSSM State Machine Diag */
 150
 151 /* PCIE protocol DLLP diagnostic registers */
 152 #define PCIE_DLLP_LCREG                 0x100 /* Link Control */
 153 #define PCIE_DLLP_LSREG                 0x104 /* Link Status */
 154 #define PCIE_DLLP_LAREG                 0x108 /* Link Attention */
 155 #define PCIE_DLLP_LAMASKREG             0x10C /* Link Attention Mask */
 156 #define PCIE_DLLP_NEXTTXSEQNUMREG       0x110 /* Next Tx Seq Num */
 157 #define PCIE_DLLP_ACKEDTXSEQNUMREG      0x114 /* Acked Tx Seq Num */
 158 #define PCIE_DLLP_PURGEDTXSEQNUMREG     0x118 /* Purged Tx Seq Num */
 159 #define PCIE_DLLP_RXSEQNUMREG           0x11C /* Rx Sequence Number */
 160 #define PCIE_DLLP_LRREG                 0x120 /* Link Replay */
 161 #define PCIE_DLLP_LACKTOREG             0x124 /* Link Ack Timeout */
 162 #define PCIE_DLLP_PMTHRESHREG           0x128 /* Power Management Threshold */
 163 #define PCIE_DLLP_RTRYWPREG             0x12C /* Retry buffer write ptr */
 164 #define PCIE_DLLP_RTRYRPREG             0x130 /* Retry buffer Read ptr */
 165 #define PCIE_DLLP_RTRYPPREG             0x134 /* Retry buffer Purged ptr */
 166 #define PCIE_DLLP_RTRRWREG              0x138 /* Retry buffer Read/Write */
 167 #define PCIE_DLLP_ECTHRESHREG           0x13C /* Error Count Threshold */
 168 #define PCIE_DLLP_TLPERRCTRREG          0x140 /* TLP Error Counter */
 169 #define PCIE_DLLP_ERRCTRREG             0x144 /* Error Counter */
 170 #define PCIE_DLLP_NAKRXCTRREG           0x148 /* NAK Received Counter */
 171 #define PCIE_DLLP_TESTREG               0x14C /* Test */
 172 #define PCIE_DLLP_PKTBIST               0x150 /* Packet BIST */
 173 #define PCIE_DLLP_PCIE11                0x154 /* DLLP PCIE 1.1 reg */
 174
 175 #define PCIE_DLLP_LSREG_LINKUP          (1 << 16)
 176
 177 /* PCIE protocol TLP diagnostic registers */
 178 #define PCIE_TLP_CONFIGREG              0x000 /* Configuration */
 179 #define PCIE_TLP_WORKAROUNDSREG         0x004 /* TLP Workarounds */
 180 #define PCIE_TLP_WRDMAUPPER             0x010 /* Write DMA Upper Address */
 181 #define PCIE_TLP_WRDMALOWER             0x014 /* Write DMA Lower Address */
 182 #define PCIE_TLP_WRDMAREQ_LBEREG        0x018 /* Write DMA Len/ByteEn Req */
 183 #define PCIE_TLP_RDDMAUPPER             0x01C /* Read DMA Upper Address */
 184 #define PCIE_TLP_RDDMALOWER             0x020 /* Read DMA Lower Address */
 185 #define PCIE_TLP_RDDMALENREG            0x024 /* Read DMA Len Req */
 186 #define PCIE_TLP_MSIDMAUPPER            0x028 /* MSI DMA Upper Address */
 187 #define PCIE_TLP_MSIDMALOWER            0x02C /* MSI DMA Lower Address */
 188 #define PCIE_TLP_MSIDMALENREG           0x030 /* MSI DMA Len Req */
 189 #define PCIE_TLP_SLVREQLENREG           0x034 /* Slave Request Len */
 190 #define PCIE_TLP_FCINPUTSREQ            0x038 /* Flow Control Inputs */
 191 #define PCIE_TLP_TXSMGRSREQ             0x03C /* Tx StateMachine and Gated Req */
 192 #define PCIE_TLP_ADRACKCNTARBLEN        0x040 /* Address Ack XferCnt and ARB Len */
 193 #define PCIE_TLP_DMACPLHDR0             0x044 /* DMA Completion Hdr 0 */
 194 #define PCIE_TLP_DMACPLHDR1             0x048 /* DMA Completion Hdr 1 */
 195 #define PCIE_TLP_DMACPLHDR2             0x04C /* DMA Completion Hdr 2 */
 196 #define PCIE_TLP_DMACPLMISC0            0x050 /* DMA Completion Misc0 */
 197 #define PCIE_TLP_DMACPLMISC1            0x054 /* DMA Completion Misc1 */
 198 #define PCIE_TLP_DMACPLMISC2            0x058 /* DMA Completion Misc2 */
 199 #define PCIE_TLP_SPTCTRLLEN             0x05C /* Split Controller Req len */
 200 #define PCIE_TLP_SPTCTRLMSIC0           0x060 /* Split Controller Misc 0 */
 201 #define PCIE_TLP_SPTCTRLMSIC1           0x064 /* Split Controller Misc 1 */
 202 #define PCIE_TLP_BUSDEVFUNC             0x068 /* Bus/Device/Func */
 203 #define PCIE_TLP_RESETCTR               0x06C /* Reset Counter */
 204 #define PCIE_TLP_RTRYBUF                0x070 /* Retry Buffer value */
 205 #define PCIE_TLP_TGTDEBUG1              0x074 /* Target Debug Reg1 */
 206 #define PCIE_TLP_TGTDEBUG2              0x078 /* Target Debug Reg2 */
 207 #define PCIE_TLP_TGTDEBUG3              0x07C /* Target Debug Reg3 */
 208 #define PCIE_TLP_TGTDEBUG4              0x080 /* Target Debug Reg4 */
 209
 210 /* MDIO control */
 211 #define MDIOCTL_DIVISOR_MASK            0x7f    /* clock to be used on MDIO */
 212 #define MDIOCTL_DIVISOR_VAL             0x2
 213 #define MDIOCTL_PREAM_EN                0x80    /* Enable preamble sequnce */
 214 #define MDIOCTL_ACCESS_DONE             0x100   /* Tranaction complete */
 215
 216 /* MDIO Data */
 217 #define MDIODATA_MASK                   0x0000ffff      /* data 2 bytes */
 218 #define MDIODATA_TA                     0x00020000      /* Turnaround */
 219 #define MDIODATA_REGADDR_SHF_OLD        18              /* Regaddr shift (rev < 10) */
 220 #define MDIODATA_REGADDR_MASK_OLD       0x003c0000      /* Regaddr Mask (rev < 10) */
 221 #define MDIODATA_DEVADDR_SHF_OLD        22              /* Physmedia devaddr shift (rev < 10) */
 222 #define MDIODATA_DEVADDR_MASK_OLD       0x0fc00000      /* Physmedia devaddr Mask (rev < 10) */
 223 #define MDIODATA_REGADDR_SHF            18              /* Regaddr shift */
 224 #define MDIODATA_REGADDR_MASK           0x007c0000      /* Regaddr Mask */
 225 #define MDIODATA_DEVADDR_SHF            23              /* Physmedia devaddr shift */
 226 #define MDIODATA_DEVADDR_MASK           0x0f800000      /* Physmedia devaddr Mask */
 227 #define MDIODATA_WRITE                  0x10000000      /* write Transaction */
 228 #define MDIODATA_READ                   0x20000000      /* Read Transaction */
 229 #define MDIODATA_START                  0x40000000      /* start of Transaction */
 230
 231 #define MDIODATA_DEV_ADDR               0x0             /* dev address for serdes */
 232 #define MDIODATA_BLK_ADDR               0x1F            /* blk address for serdes */
 233
 234
 235 /* MDIO devices (SERDES modules)
 236  *  unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks.
 237  *  two layers mapping (blockidx, register offset) is required
 238  */
 239 #define MDIO_DEV_IEEE0          0x000
 240 #define MDIO_DEV_IEEE1          0x001
 241 #define MDIO_DEV_BLK0           0x800
 242 #define MDIO_DEV_BLK1           0x801
 243 #define MDIO_DEV_BLK2           0x802
 244 #define MDIO_DEV_BLK3           0x803
 245 #define MDIO_DEV_BLK4           0x804
 246 #define MDIO_DEV_TXPLL          0x808   /* TXPLL register block idx */
 247 #define MDIO_DEV_TXCTRL0        0x820
 248 #define MDIO_DEV_SERDESID       0x831
 249 #define MDIO_DEV_RXCTRL0        0x840
 250
 251
 252 /* XgxsBlk1_A Register Offsets */
 253 #define BLK1_PWR_MGMT0          0x16
 254 #define BLK1_PWR_MGMT1          0x17
 255 #define BLK1_PWR_MGMT2          0x18
 256 #define BLK1_PWR_MGMT3          0x19
 257 #define BLK1_PWR_MGMT4          0x1A
 258
 259 /* serdes regs (rev < 10) */
 260 #define MDIODATA_DEV_PLL                0x1d    /* SERDES PLL Dev */
 261 #define MDIODATA_DEV_TX                 0x1e    /* SERDES TX Dev */
 262 #define MDIODATA_DEV_RX                 0x1f    /* SERDES RX Dev */
 263         /* SERDES RX registers */
 264 #define SERDES_RX_CTRL                  1       /* Rx cntrl */
 265 #define SERDES_RX_TIMER1                2       /* Rx Timer1 */
 266 #define SERDES_RX_CDR                   6       /* CDR */
 267 #define SERDES_RX_CDRBW                 7       /* CDR BW */
 268
 269         /* SERDES RX control register */
 270 #define SERDES_RX_CTRL_FORCE            0x80    /* rxpolarity_force */
 271 #define SERDES_RX_CTRL_POLARITY         0x40    /* rxpolarity_value */
 272
 273         /* SERDES PLL registers */
 274 #define SERDES_PLL_CTRL                 1       /* PLL control reg */
 275 #define PLL_CTRL_FREQDET_EN             0x4000  /* bit 14 is FREQDET on */
 276
 277 /* Power management threshold */
 278 #define PCIE_L0THRESHOLDTIME_MASK       0xFF00  /* bits 0 - 7 */
 279 #define PCIE_L1THRESHOLDTIME_MASK       0xFF00  /* bits 8 - 15 */
 280 #define PCIE_L1THRESHOLDTIME_SHIFT      8       /* PCIE_L1THRESHOLDTIME_SHIFT */
 281 #define PCIE_L1THRESHOLD_WARVAL         0x72    /* WAR value */
 282 #define PCIE_ASPMTIMER_EXTEND           0x01000000      /* > rev7: enable extend ASPM timer */
 283
 284 /* SPROM offsets */
 285 #define SRSH_ASPM_OFFSET                4       /* word 4 */
 286 #define SRSH_ASPM_ENB                   0x18    /* bit 3, 4 */
 287 #define SRSH_ASPM_L1_ENB                0x10    /* bit 4 */
 288 #define SRSH_ASPM_L0s_ENB               0x8     /* bit 3 */
 289 #define SRSH_PCIE_MISC_CONFIG           5       /* word 5 */
 290 #define SRSH_L23READY_EXIT_NOPERST      0x8000  /* bit 15 */
 291 #define SRSH_CLKREQ_OFFSET_REV5         20      /* word 20 for srom rev <= 5 */
 292 #define SRSH_CLKREQ_OFFSET_REV8         52      /* word 52 for srom rev 8 */
 293 #define SRSH_CLKREQ_ENB                 0x0800  /* bit 11 */
 294 #define SRSH_BD_OFFSET                  6       /* word 6 */
 295 #define SRSH_AUTOINIT_OFFSET            18      /* auto initialization enable */
 296
 297 /* Linkcontrol reg offset in PCIE Cap */
 298 #define PCIE_CAP_LINKCTRL_OFFSET        16      /* linkctrl offset in pcie cap */
 299 #define PCIE_CAP_LCREG_ASPML0s          0x01    /* ASPM L0s in linkctrl */
 300 #define PCIE_CAP_LCREG_ASPML1           0x02    /* ASPM L1 in linkctrl */
 301 #define PCIE_CLKREQ_ENAB                0x100   /* CLKREQ Enab in linkctrl */
 302
 303 /* Devcontrol reg offset in PCIE Cap */
 304 #define PCIE_CAP_DEVCTRL_OFFSET         8       /* devctrl offset in pcie cap */
 305 #define PCIE_CAP_DEVCTRL_MRRS_MASK      0x7000  /* Max read request size mask */
 306 #define PCIE_CAP_DEVCTRL_MRRS_SHIFT     12      /* Max read request size shift */
 307 #define PCIE_CAP_DEVCTRL_MRRS_128B      0       /* 128 Byte */
 308 #define PCIE_CAP_DEVCTRL_MRRS_256B      1       /* 256 Byte */
 309 #define PCIE_CAP_DEVCTRL_MRRS_512B      2       /* 512 Byte */
 310
 311 #define PCIE_ASPM_ENAB                  3       /* ASPM L0s & L1 in linkctrl */
 312 #define PCIE_ASPM_L1_ENAB               2       /* ASPM L0s & L1 in linkctrl */
 313 #define PCIE_ASPM_L0s_ENAB              1       /* ASPM L0s & L1 in linkctrl */
 314 #define PCIE_ASPM_DISAB                 0       /* ASPM L0s & L1 in linkctrl */
 315
 316 /* Status reg PCIE_PLP_STATUSREG */
 317 #define PCIE_PLP_POLARITYINV_STAT       0x10
 318 #endif  /* _PCIE_CORE_H */