release/src-rt/include/pcicfg.h

   1 /*
   2  * pcicfg.h: PCI configuration constants and structures.
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: pcicfg.h,v 1.50 2009-12-07 21:56:06 Exp $
  19  */
  20
  21 #ifndef _h_pcicfg_
  22 #define _h_pcicfg_
  23
  24 #ifndef LINUX_POSTMOGRIFY_REMOVAL
  25 /* The following inside ifndef's so we don't collide with NTDDK.H */
  26 #ifndef PCI_MAX_BUS
  27 #define PCI_MAX_BUS             0x100
  28 #endif
  29 #ifndef PCI_MAX_DEVICES
  30 #define PCI_MAX_DEVICES         0x20
  31 #endif
  32 #ifndef PCI_MAX_FUNCTION
  33 #define PCI_MAX_FUNCTION        0x8
  34 #endif
  35
  36 #ifndef PCI_INVALID_VENDORID
  37 #define PCI_INVALID_VENDORID    0xffff
  38 #endif
  39 #ifndef PCI_INVALID_DEVICEID
  40 #define PCI_INVALID_DEVICEID    0xffff
  41 #endif
  42
  43
  44 /* Convert between bus-slot-function-register and config addresses */
  45
  46 #define PCICFG_BUS_SHIFT        16      /* Bus shift */
  47 #define PCICFG_SLOT_SHIFT       11      /* Slot shift */
  48 #define PCICFG_FUN_SHIFT        8       /* Function shift */
  49 #define PCICFG_OFF_SHIFT        0       /* Register shift */
  50
  51 #define PCICFG_BUS_MASK         0xff    /* Bus mask */
  52 #define PCICFG_SLOT_MASK        0x1f    /* Slot mask */
  53 #define PCICFG_FUN_MASK         7       /* Function mask */
  54 #define PCICFG_OFF_MASK         0xff    /* Bus mask */
  55
  56 #define PCI_CONFIG_ADDR(b, s, f, o)                                     \
  57                 ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT)          \
  58                  | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT)      \
  59                  | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT)        \
  60                  | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
  61
  62 #define PCI_CONFIG_BUS(a)       (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
  63 #define PCI_CONFIG_SLOT(a)      (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
  64 #define PCI_CONFIG_FUN(a)       (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
  65 #define PCI_CONFIG_OFF(a)       (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
  66
  67 /* PCIE Config space accessing MACROS */
  68
  69 #define PCIECFG_BUS_SHIFT       24      /* Bus shift */
  70 #define PCIECFG_SLOT_SHIFT      19      /* Slot/Device shift */
  71 #define PCIECFG_FUN_SHIFT       16      /* Function shift */
  72 #define PCIECFG_OFF_SHIFT       0       /* Register shift */
  73
  74 #define PCIECFG_BUS_MASK        0xff    /* Bus mask */
  75 #define PCIECFG_SLOT_MASK       0x1f    /* Slot/Device mask */
  76 #define PCIECFG_FUN_MASK        7       /* Function mask */
  77 #define PCIECFG_OFF_MASK        0xfff   /* Register mask */
  78
  79 #define PCIE_CONFIG_ADDR(b, s, f, o)                                    \
  80                 ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT)                \
  81                  | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT)    \
  82                  | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT)      \
  83                  | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
  84
  85 #define PCIE_CONFIG_BUS(a)      (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
  86 #define PCIE_CONFIG_SLOT(a)     (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
  87 #define PCIE_CONFIG_FUN(a)      (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
  88 #define PCIE_CONFIG_OFF(a)      (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
  89
  90 /* The actual config space */
  91
  92 #define PCI_BAR_MAX             6
  93
  94 #define PCI_ROM_BAR             8
  95
  96 #define PCR_RSVDA_MAX           2
  97
  98 /* Bits in PCI bars' flags */
  99
 100 #define PCIBAR_FLAGS            0xf
 101 #define PCIBAR_IO               0x1
 102 #define PCIBAR_MEM1M            0x2
 103 #define PCIBAR_MEM64            0x4
 104 #define PCIBAR_PREFETCH         0x8
 105 #define PCIBAR_MEM32_MASK       0xFFFFFF80
 106
 107 /* pci config status reg has a bit to indicate that capability ptr is present */
 108
 109 #define PCI_CAPPTR_PRESENT      0x0010
 110
 111 typedef struct _pci_config_regs {
 112         uint16  vendor;
 113         uint16  device;
 114         uint16  command;
 115         uint16  status;
 116         uint8   rev_id;
 117         uint8   prog_if;
 118         uint8   sub_class;
 119         uint8   base_class;
 120         uint8   cache_line_size;
 121         uint8   latency_timer;
 122         uint8   header_type;
 123         uint8   bist;
 124         uint32  base[PCI_BAR_MAX];
 125         uint32  cardbus_cis;
 126         uint16  subsys_vendor;
 127         uint16  subsys_id;
 128         uint32  baserom;
 129         uint32  rsvd_a[PCR_RSVDA_MAX];
 130         uint8   int_line;
 131         uint8   int_pin;
 132         uint8   min_gnt;
 133         uint8   max_lat;
 134         uint8   dev_dep[192];
 135 } pci_config_regs;
 136
 137 #define SZPCR           (sizeof (pci_config_regs))
 138 #define MINSZPCR        64              /* offsetof (dev_dep[0] */
 139
 140 /* A structure for the config registers is nice, but in most
 141  * systems the config space is not memory mapped, so we need
 142  * field offsetts. :-(
 143  */
 144 #define PCI_CFG_VID             0
 145 #define PCI_CFG_DID             2
 146 #define PCI_CFG_CMD             4
 147 #define PCI_CFG_STAT            6
 148 #define PCI_CFG_REV             8
 149 #define PCI_CFG_PROGIF          9
 150 #define PCI_CFG_SUBCL           0xa
 151 #define PCI_CFG_BASECL          0xb
 152 #define PCI_CFG_CLSZ            0xc
 153 #define PCI_CFG_LATTIM          0xd
 154 #define PCI_CFG_HDR             0xe
 155 #define PCI_CFG_BIST            0xf
 156 #define PCI_CFG_BAR0            0x10
 157 #define PCI_CFG_BAR1            0x14
 158 #define PCI_CFG_BAR2            0x18
 159 #define PCI_CFG_BAR3            0x1c
 160 #define PCI_CFG_BAR4            0x20
 161 #define PCI_CFG_BAR5            0x24
 162 #define PCI_CFG_CIS             0x28
 163 #define PCI_CFG_SVID            0x2c
 164 #define PCI_CFG_SSID            0x2e
 165 #define PCI_CFG_ROMBAR          0x30
 166 #define PCI_CFG_CAPPTR          0x34
 167 #define PCI_CFG_INT             0x3c
 168 #define PCI_CFG_PIN             0x3d
 169 #define PCI_CFG_MINGNT          0x3e
 170 #define PCI_CFG_MAXLAT          0x3f
 171
 172 #ifdef __NetBSD__
 173 #undef  PCI_CLASS_DISPLAY
 174 #undef  PCI_CLASS_MEMORY
 175 #undef  PCI_CLASS_BRIDGE
 176 #undef  PCI_CLASS_INPUT
 177 #undef  PCI_CLASS_DOCK
 178 #endif  /* __NetBSD__ */
 179
 180 #ifdef EFI
 181 #undef PCI_CLASS_BRIDGE
 182 #undef PCI_CLASS_OLD
 183 #undef PCI_CLASS_DISPLAY
 184 #undef PCI_CLASS_SERIAL
 185 #undef PCI_CLASS_SATELLITE
 186 #endif /* EFI */
 187
 188 /* Classes and subclasses */
 189
 190 typedef enum {
 191         PCI_CLASS_OLD = 0,
 192         PCI_CLASS_DASDI,
 193         PCI_CLASS_NET,
 194         PCI_CLASS_DISPLAY,
 195         PCI_CLASS_MMEDIA,
 196         PCI_CLASS_MEMORY,
 197         PCI_CLASS_BRIDGE,
 198         PCI_CLASS_COMM,
 199         PCI_CLASS_BASE,
 200         PCI_CLASS_INPUT,
 201         PCI_CLASS_DOCK,
 202         PCI_CLASS_CPU,
 203         PCI_CLASS_SERIAL,
 204         PCI_CLASS_INTELLIGENT = 0xe,
 205         PCI_CLASS_SATELLITE,
 206         PCI_CLASS_CRYPT,
 207         PCI_CLASS_DSP,
 208         PCI_CLASS_XOR = 0xfe
 209 } pci_classes;
 210
 211 typedef enum {
 212         PCI_DASDI_SCSI,
 213         PCI_DASDI_IDE,
 214         PCI_DASDI_FLOPPY,
 215         PCI_DASDI_IPI,
 216         PCI_DASDI_RAID,
 217         PCI_DASDI_OTHER = 0x80
 218 } pci_dasdi_subclasses;
 219
 220 typedef enum {
 221         PCI_NET_ETHER,
 222         PCI_NET_TOKEN,
 223         PCI_NET_FDDI,
 224         PCI_NET_ATM,
 225         PCI_NET_OTHER = 0x80
 226 } pci_net_subclasses;
 227
 228 typedef enum {
 229         PCI_DISPLAY_VGA,
 230         PCI_DISPLAY_XGA,
 231         PCI_DISPLAY_3D,
 232         PCI_DISPLAY_OTHER = 0x80
 233 } pci_display_subclasses;
 234
 235 typedef enum {
 236         PCI_MMEDIA_VIDEO,
 237         PCI_MMEDIA_AUDIO,
 238         PCI_MMEDIA_PHONE,
 239         PCI_MEDIA_OTHER = 0x80
 240 } pci_mmedia_subclasses;
 241
 242 typedef enum {
 243         PCI_MEMORY_RAM,
 244         PCI_MEMORY_FLASH,
 245         PCI_MEMORY_OTHER = 0x80
 246 } pci_memory_subclasses;
 247
 248 typedef enum {
 249         PCI_BRIDGE_HOST,
 250         PCI_BRIDGE_ISA,
 251         PCI_BRIDGE_EISA,
 252         PCI_BRIDGE_MC,
 253         PCI_BRIDGE_PCI,
 254         PCI_BRIDGE_PCMCIA,
 255         PCI_BRIDGE_NUBUS,
 256         PCI_BRIDGE_CARDBUS,
 257         PCI_BRIDGE_RACEWAY,
 258         PCI_BRIDGE_OTHER = 0x80
 259 } pci_bridge_subclasses;
 260
 261 typedef enum {
 262         PCI_COMM_UART,
 263         PCI_COMM_PARALLEL,
 264         PCI_COMM_MULTIUART,
 265         PCI_COMM_MODEM,
 266         PCI_COMM_OTHER = 0x80
 267 } pci_comm_subclasses;
 268
 269 typedef enum {
 270         PCI_BASE_PIC,
 271         PCI_BASE_DMA,
 272         PCI_BASE_TIMER,
 273         PCI_BASE_RTC,
 274         PCI_BASE_PCI_HOTPLUG,
 275         PCI_BASE_OTHER = 0x80
 276 } pci_base_subclasses;
 277
 278 typedef enum {
 279         PCI_INPUT_KBD,
 280         PCI_INPUT_PEN,
 281         PCI_INPUT_MOUSE,
 282         PCI_INPUT_SCANNER,
 283         PCI_INPUT_GAMEPORT,
 284         PCI_INPUT_OTHER = 0x80
 285 } pci_input_subclasses;
 286
 287 typedef enum {
 288         PCI_DOCK_GENERIC,
 289         PCI_DOCK_OTHER = 0x80
 290 } pci_dock_subclasses;
 291
 292 typedef enum {
 293         PCI_CPU_386,
 294         PCI_CPU_486,
 295         PCI_CPU_PENTIUM,
 296         PCI_CPU_ALPHA = 0x10,
 297         PCI_CPU_POWERPC = 0x20,
 298         PCI_CPU_MIPS = 0x30,
 299         PCI_CPU_COPROC = 0x40,
 300         PCI_CPU_OTHER = 0x80
 301 } pci_cpu_subclasses;
 302
 303 typedef enum {
 304         PCI_SERIAL_IEEE1394,
 305         PCI_SERIAL_ACCESS,
 306         PCI_SERIAL_SSA,
 307         PCI_SERIAL_USB,
 308         PCI_SERIAL_FIBER,
 309         PCI_SERIAL_SMBUS,
 310         PCI_SERIAL_OTHER = 0x80
 311 } pci_serial_subclasses;
 312
 313 typedef enum {
 314         PCI_INTELLIGENT_I2O
 315 } pci_intelligent_subclasses;
 316
 317 typedef enum {
 318         PCI_SATELLITE_TV,
 319         PCI_SATELLITE_AUDIO,
 320         PCI_SATELLITE_VOICE,
 321         PCI_SATELLITE_DATA,
 322         PCI_SATELLITE_OTHER = 0x80
 323 } pci_satellite_subclasses;
 324
 325 typedef enum {
 326         PCI_CRYPT_NETWORK,
 327         PCI_CRYPT_ENTERTAINMENT,
 328         PCI_CRYPT_OTHER = 0x80
 329 } pci_crypt_subclasses;
 330
 331 typedef enum {
 332         PCI_DSP_DPIO,
 333         PCI_DSP_OTHER = 0x80
 334 } pci_dsp_subclasses;
 335
 336 typedef enum {
 337         PCI_XOR_QDMA,
 338         PCI_XOR_OTHER = 0x80
 339 } pci_xor_subclasses;
 340
 341 /* Header types */
 342 #define PCI_HEADER_MULTI        0x80
 343 #define PCI_HEADER_MASK         0x7f
 344 typedef enum {
 345         PCI_HEADER_NORMAL,
 346         PCI_HEADER_BRIDGE,
 347         PCI_HEADER_CARDBUS
 348 } pci_header_types;
 349
 350
 351 /* Overlay for a PCI-to-PCI bridge */
 352
 353 #define PPB_RSVDA_MAX           2
 354 #define PPB_RSVDD_MAX           8
 355
 356 typedef struct _ppb_config_regs {
 357         uint16  vendor;
 358         uint16  device;
 359         uint16  command;
 360         uint16  status;
 361         uint8   rev_id;
 362         uint8   prog_if;
 363         uint8   sub_class;
 364         uint8   base_class;
 365         uint8   cache_line_size;
 366         uint8   latency_timer;
 367         uint8   header_type;
 368         uint8   bist;
 369         uint32  rsvd_a[PPB_RSVDA_MAX];
 370         uint8   prim_bus;
 371         uint8   sec_bus;
 372         uint8   sub_bus;
 373         uint8   sec_lat;
 374         uint8   io_base;
 375         uint8   io_lim;
 376         uint16  sec_status;
 377         uint16  mem_base;
 378         uint16  mem_lim;
 379         uint16  pf_mem_base;
 380         uint16  pf_mem_lim;
 381         uint32  pf_mem_base_hi;
 382         uint32  pf_mem_lim_hi;
 383         uint16  io_base_hi;
 384         uint16  io_lim_hi;
 385         uint16  subsys_vendor;
 386         uint16  subsys_id;
 387         uint32  rsvd_b;
 388         uint8   rsvd_c;
 389         uint8   int_pin;
 390         uint16  bridge_ctrl;
 391         uint8   chip_ctrl;
 392         uint8   diag_ctrl;
 393         uint16  arb_ctrl;
 394         uint32  rsvd_d[PPB_RSVDD_MAX];
 395         uint8   dev_dep[192];
 396 } ppb_config_regs;
 397
 398
 399 /* PCI CAPABILITY DEFINES */
 400 #define PCI_CAP_POWERMGMTCAP_ID         0x01
 401 #define PCI_CAP_MSICAP_ID               0x05
 402 #define PCI_CAP_VENDSPEC_ID             0x09
 403 #define PCI_CAP_PCIECAP_ID              0x10
 404
 405 /* Data structure to define the Message Signalled Interrupt facility
 406  * Valid for PCI and PCIE configurations
 407  */
 408 typedef struct _pciconfig_cap_msi {
 409         uint8   capID;
 410         uint8   nextptr;
 411         uint16  msgctrl;
 412         uint32  msgaddr;
 413 } pciconfig_cap_msi;
 414
 415 /* Data structure to define the Power managment facility
 416  * Valid for PCI and PCIE configurations
 417  */
 418 typedef struct _pciconfig_cap_pwrmgmt {
 419         uint8   capID;
 420         uint8   nextptr;
 421         uint16  pme_cap;
 422         uint16  pme_sts_ctrl;
 423         uint8   pme_bridge_ext;
 424         uint8   data;
 425 } pciconfig_cap_pwrmgmt;
 426
 427 #define PME_CAP_PM_STATES (0x1f << 27)  /* Bits 31:27 states that can generate PME */
 428 #define PME_CSR_OFFSET      0x4         /* 4-bytes offset */
 429 #define PME_CSR_PME_EN    (1 << 8)      /* Bit 8 Enable generating of PME */
 430 #define PME_CSR_PME_STAT  (1 << 15)     /* Bit 15 PME got asserted */
 431
 432 /* Data structure to define the PCIE capability */
 433 typedef struct _pciconfig_cap_pcie {
 434         uint8   capID;
 435         uint8   nextptr;
 436         uint16  pcie_cap;
 437         uint32  dev_cap;
 438         uint16  dev_ctrl;
 439         uint16  dev_status;
 440         uint32  link_cap;
 441         uint16  link_ctrl;
 442         uint16  link_status;
 443         uint32  slot_cap;
 444         uint16  slot_ctrl;
 445         uint16  slot_status;
 446         uint16  root_ctrl;
 447         uint16  root_cap;
 448         uint32  root_status;
 449 } pciconfig_cap_pcie;
 450
 451 /* PCIE Enhanced CAPABILITY DEFINES */
 452 #define PCIE_EXTCFG_OFFSET      0x100
 453 #define PCIE_ADVERRREP_CAPID    0x0001
 454 #define PCIE_VC_CAPID           0x0002
 455 #define PCIE_DEVSNUM_CAPID      0x0003
 456 #define PCIE_PWRBUDGET_CAPID    0x0004
 457
 458 /* PCIE Extended configuration */
 459 #define PCIE_ADV_CORR_ERR_MASK  0x114
 460 #define CORR_ERR_RE     (1 << 0) /* Receiver  */
 461 #define CORR_ERR_BT     (1 << 6) /* Bad TLP  */
 462 #define CORR_ERR_BD     (1 << 7) /* Bad DLLP */
 463 #define CORR_ERR_RR     (1 << 8) /* REPLAY_NUM rollover */
 464 #define CORR_ERR_RT     (1 << 12) /* Reply timer timeout */
 465 #define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
 466                          CORR_ERR_RR | CORR_ERR_RT)
 467
 468 /* PCIE Root Control Register bits (Host mode only) */
 469 #define PCIE_RC_CORR_SERR_EN            0x0001
 470 #define PCIE_RC_NONFATAL_SERR_EN        0x0002
 471 #define PCIE_RC_FATAL_SERR_EN           0x0004
 472 #define PCIE_RC_PME_INT_EN              0x0008
 473 #define PCIE_RC_CRS_EN                  0x0010
 474
 475 /* PCIE Root Capability Register bits (Host mode only) */
 476 #define PCIE_RC_CRS_VISIBILITY          0x0001
 477
 478 /* Header to define the PCIE specific capabilities in the extended config space */
 479 typedef struct _pcie_enhanced_caphdr {
 480         uint16  capID;
 481         uint16  cap_ver : 4;
 482         uint16  next_ptr : 12;
 483 } pcie_enhanced_caphdr;
 484
 485
 486 /* Everything below is BRCM HND proprietary */
 487
 488
 489 /* Brcm PCI configuration registers */
 490 #define cap_list        rsvd_a[0]
 491 #define bar0_window     dev_dep[0x80 - 0x40]
 492 #define bar1_window     dev_dep[0x84 - 0x40]
 493 #define sprom_control   dev_dep[0x88 - 0x40]
 494 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
 495 #define PCI_BAR0_WIN            0x80    /* backplane addres space accessed by BAR0 */
 496 #ifndef LINUX_POSTMOGRIFY_REMOVAL
 497 #define PCI_BAR1_WIN            0x84    /* backplane addres space accessed by BAR1 */
 498 #define PCI_SPROM_CONTROL       0x88    /* sprom property control */
 499 #define PCI_BAR1_CONTROL        0x8c    /* BAR1 region burst control */
 500 #define PCI_INT_STATUS          0x90    /* PCI and other cores interrupts */
 501 #define PCI_INT_MASK            0x94    /* mask of PCI and other cores interrupts */
 502 #define PCI_TO_SB_MB            0x98    /* signal backplane interrupts */
 503 #define PCI_BACKPLANE_ADDR      0xa0    /* address an arbitrary location on the system backplane */
 504 #define PCI_BACKPLANE_DATA      0xa4    /* data at the location specified by above address */
 505 #define PCI_CLK_CTL_ST          0xa8    /* pci config space clock control/status (>=rev14) */
 506 #define PCI_BAR0_WIN2           0xac    /* backplane addres space accessed by second 4KB of BAR0 */
 507 #define PCI_GPIO_IN             0xb0    /* pci config space gpio input (>=rev3) */
 508 #define PCI_GPIO_OUT            0xb4    /* pci config space gpio output (>=rev3) */
 509 #define PCI_GPIO_OUTEN          0xb8    /* pci config space gpio output enable (>=rev3) */
 510
 511 #define PCI_BAR0_SHADOW_OFFSET  (2 * 1024)      /* bar0 + 2K accesses sprom shadow (in pci core) */
 512 #define PCI_BAR0_SPROM_OFFSET   (4 * 1024)      /* bar0 + 4K accesses external sprom */
 513 #define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)      /* bar0 + 6K accesses pci core registers */
 514 #define PCI_BAR0_PCISBR_OFFSET  (4 * 1024)      /* pci core SB registers are at the end of the
 515                                                  * 8KB window, so their address is the "regular"
 516                                                  * address plus 4K
 517                                                  */
 518 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
 519 #define PCI_BAR0_WINSZ          (16 * 1024)     /* bar0 window size Match with corerev 13 */
 520 #ifndef LINUX_POSTMOGRIFY_REMOVAL
 521 /* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
 522 #define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)     /* bar0 + 8K accesses pci/pcie core registers */
 523 #define PCI_16KB0_CCREGS_OFFSET (12 * 1024)     /* bar0 + 12K accesses chipc core registers */
 524 #define PCI_16KBB0_WINSZ        (16 * 1024)     /* bar0 window size */
 525
 526 /* On AI chips we have a second window to map DMP regs are mapped: */
 527 #define PCI_16KB0_WIN2_OFFSET   (4 * 1024)      /* bar0 + 4K is "Window 2" */
 528
 529 /* PCI_INT_STATUS */
 530 #define PCI_SBIM_STATUS_SERR    0x4     /* backplane SBErr interrupt status */
 531
 532 /* PCI_INT_MASK */
 533 #define PCI_SBIM_SHIFT          8       /* backplane core interrupt mask bits offset */
 534 #define PCI_SBIM_MASK           0xff00  /* backplane core interrupt mask */
 535 #define PCI_SBIM_MASK_SERR      0x4     /* backplane SBErr interrupt mask */
 536
 537 /* PCI_SPROM_CONTROL */
 538 #define SPROM_SZ_MSK            0x02    /* SPROM Size Mask */
 539 #define SPROM_LOCKED            0x08    /* SPROM Locked */
 540 #define SPROM_BLANK             0x04    /* indicating a blank SPROM */
 541 #define SPROM_WRITEEN           0x10    /* SPROM write enable */
 542 #define SPROM_BOOTROM_WE        0x20    /* external bootrom write enable */
 543 #define SPROM_BACKPLANE_EN      0x40    /* Enable indirect backplane access */
 544 #define SPROM_OTPIN_USE         0x80    /* device OTP In use */
 545
 546 /* Bits in PCI command and status regs */
 547 #define PCI_CMD_IO              0x00000001      /* I/O enable */
 548 #define PCI_CMD_MEMORY          0x00000002      /* Memory enable */
 549 #define PCI_CMD_MASTER          0x00000004      /* Master enable */
 550 #define PCI_CMD_SPECIAL         0x00000008      /* Special cycles enable */
 551 #define PCI_CMD_INVALIDATE      0x00000010      /* Invalidate? */
 552 #define PCI_CMD_VGA_PAL         0x00000040      /* VGA Palate */
 553 #define PCI_STAT_TA             0x08000000      /* target abort status */
 554 #endif /* LINUX_POSTMOGRIFY_REMOVAL */
 555 #endif  /* _h_pcicfg_ */