2 * BCM43XX PCI core hardware definitions.
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: pci_core.h,v 13.1 2007-12-04 07:22:41 Exp $
24 #ifndef _LANGUAGE_ASSEMBLY
26 /* cpp contortions to concatenate w/arg prescan */
28 #define _PADLINE(line) pad ## line
29 #define _XSTR(line) _PADLINE(line)
30 #define PAD _XSTR(__LINE__)
33 /* Sonics side: PCI core and host control registers */
34 typedef struct sbpciregs
{
35 uint32 control
; /* PCI control */
37 uint32 arbcontrol
; /* PCI arbiter control */
38 uint32 clkrun
; /* Clkrun Control (>=rev11) */
40 uint32 intstatus
; /* Interrupt status */
41 uint32 intmask
; /* Interrupt mask */
42 uint32 sbtopcimailbox
; /* Sonics to PCI mailbox */
44 uint32 bcastaddr
; /* Sonics broadcast address */
45 uint32 bcastdata
; /* Sonics broadcast data */
47 uint32 gpioin
; /* ro: gpio input (>=rev2) */
48 uint32 gpioout
; /* rw: gpio output (>=rev2) */
49 uint32 gpioouten
; /* rw: gpio output enable (>= rev2) */
50 uint32 gpiocontrol
; /* rw: gpio control (>= rev2) */
52 uint32 sbtopci0
; /* Sonics to PCI translation 0 */
53 uint32 sbtopci1
; /* Sonics to PCI translation 1 */
54 uint32 sbtopci2
; /* Sonics to PCI translation 2 */
56 uint32 pcicfg
[4][64]; /* 0x400 - 0x7FF, PCI Cfg Space (>=rev8) */
57 uint16 sprom
[36]; /* SPROM shadow Area */
61 #endif /* _LANGUAGE_ASSEMBLY */
64 #define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
65 #define PCI_RST 0x02 /* Value driven out to pin */
66 #define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
67 #define PCI_CLK 0x08 /* Gate for clock driven out to pin */
69 /* PCI arbiter control */
70 #define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
71 #define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
72 /* ParkID - for PCI corerev >= 8 */
73 #define PCI_PARKID_MASK 0x1c /* Selects which agent is parked on an idle bus */
74 #define PCI_PARKID_SHIFT 2
75 #define PCI_PARKID_EXT0 0 /* External master 0 */
76 #define PCI_PARKID_EXT1 1 /* External master 1 */
77 #define PCI_PARKID_EXT2 2 /* External master 2 */
78 #define PCI_PARKID_EXT3 3 /* External master 3 (rev >= 11) */
79 #define PCI_PARKID_INT 3 /* Internal master (rev < 11) */
80 #define PCI11_PARKID_INT 4 /* Internal master (rev >= 11) */
81 #define PCI_PARKID_LAST 4 /* Last active master (rev < 11) */
82 #define PCI11_PARKID_LAST 5 /* Last active master (rev >= 11) */
84 #define PCI_CLKRUN_DSBL 0x8000 /* Bit 15 forceClkrun */
86 /* Interrupt status/mask */
87 #define PCI_INTA 0x01 /* PCI INTA# is asserted */
88 #define PCI_INTB 0x02 /* PCI INTB# is asserted */
89 #define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
90 #define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
91 #define PCI_PME 0x10 /* PCI PME# is asserted */
93 /* (General) PCI/SB mailbox interrupts, two bits per pci function */
94 #define MAILBOX_F0_0 0x100 /* function 0, int 0 */
95 #define MAILBOX_F0_1 0x200 /* function 0, int 1 */
96 #define MAILBOX_F1_0 0x400 /* function 1, int 0 */
97 #define MAILBOX_F1_1 0x800 /* function 1, int 1 */
98 #define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
99 #define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
100 #define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
101 #define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
103 /* Sonics broadcast address */
104 #define BCAST_ADDR_MASK 0xff /* Broadcast register address */
106 /* Sonics to PCI translation types */
107 #define SBTOPCI0_MASK 0xfc000000
108 #define SBTOPCI1_MASK 0xfc000000
109 #define SBTOPCI2_MASK 0xc0000000
110 #define SBTOPCI_MEM 0
112 #define SBTOPCI_CFG0 2
113 #define SBTOPCI_CFG1 3
114 #define SBTOPCI_PREF 0x4 /* prefetch enable */
115 #define SBTOPCI_BURST 0x8 /* burst enable */
116 #define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
117 #define SBTOPCI_RC_READ 0x00 /* memory read */
118 #define SBTOPCI_RC_READLINE 0x10 /* memory read line */
119 #define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
121 /* PCI core index in SROM shadow area */
122 #define SRSH_PI_OFFSET 0 /* first word */
123 #define SRSH_PI_MASK 0xf000 /* bit 15:12 */
124 #define SRSH_PI_SHIFT 12 /* bit 15:12 */
126 #endif /* _PCI_CORE_H_ */