2 * BCM43XX PCI/E core sw API definitions.
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: nicpci.h,v 13.10.12.3 2011-01-27 19:03:20 Exp $
24 #if defined(BCMDHDUSB) || (defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS))
25 #define pcicore_find_pci_capability(a, b, c, d) (0)
26 #define pcie_readreg(a, b, c, d) (0)
27 #define pcie_writereg(a, b, c, d, e) (0)
29 #define pcie_clkreq(a, b, c) (0)
30 #define pcie_lcreg(a, b, c) (0)
32 #define pcicore_init(a, b, c) (0x0dadbeef)
33 #define pcicore_deinit(a) do { } while (0)
34 #define pcicore_attach(a, b, c) do { } while (0)
35 #define pcicore_hwup(a) do { } while (0)
36 #define pcicore_up(a, b) do { } while (0)
37 #define pcicore_sleep(a) do { } while (0)
38 #define pcicore_down(a, b) do { } while (0)
40 #define pcie_war_ovr_aspm_update(a, b) do { } while (0)
41 #define pcie_power_save_enable(a, b) do { } while (0)
43 #define pcicore_pcieserdesreg(a, b, c, d, e) (0)
44 #define pcicore_pciereg(a, b, c, d, e) (0)
45 #if defined(BCMDBG_DUMP)
46 #define pcicore_dump_pcieregs(a, b) (0)
49 #define pcie_lcreg(a, b, c) (0)
50 #define pcicore_dump(a, b) do { } while (0)
53 #define pcicore_pmecap_fast(a) (FALSE)
54 #define pcicore_pmeen(a) do { } while (0)
55 #define pcicore_pmeclr(a) do { } while (0)
56 #define pcicore_pmestat(a) (FALSE)
57 #define pcie_set_request_size(pch, size) do { } while (0)
58 #define pcie_get_request_size(pch) (0)
62 extern uint8
pcicore_find_pci_capability(osl_t
*osh
, uint8 req_cap_id
,
63 uchar
*buf
, uint32
*buflen
);
64 extern uint
pcie_readreg(osl_t
*osh
, struct sbpcieregs
*pcieregs
, uint addrtype
, uint offset
);
65 extern uint
pcie_writereg(osl_t
*osh
, struct sbpcieregs
*pcieregs
, uint addrtype
, uint offset
,
68 extern uint8
pcie_clkreq(void *pch
, uint32 mask
, uint32 val
);
69 extern uint32
pcie_lcreg(void *pch
, uint32 mask
, uint32 val
);
71 extern void *pcicore_init(si_t
*sih
, osl_t
*osh
, void *regs
);
72 extern void pcicore_deinit(void *pch
);
73 extern void pcicore_attach(void *pch
, char *pvars
, int state
);
74 extern void pcicore_hwup(void *pch
);
75 extern void pcicore_up(void *pch
, int state
);
76 extern void pcicore_sleep(void *pch
);
77 extern void pcicore_down(void *pch
, int state
);
79 extern void pcie_war_ovr_aspm_update(void *pch
, uint8 aspm
);
80 extern void pcie_power_save_enable(void *pch
, bool enable
);
82 extern uint32
pcicore_pcieserdesreg(void *pch
, uint32 mdioslave
, uint32 offset
,
83 uint32 mask
, uint32 val
);
85 extern uint32
pcicore_pciereg(void *pch
, uint32 offset
, uint32 mask
, uint32 val
, uint type
);
87 #if defined(BCMDBG_DUMP)
88 extern int pcicore_dump_pcieregs(void *pch
, struct bcmstrbuf
*b
);
92 extern void pcicore_dump(void *pch
, struct bcmstrbuf
*b
);
95 extern bool pcicore_pmecap_fast(osl_t
*osh
);
96 extern void pcicore_pmeen(void *pch
);
97 extern void pcicore_pmeclr(void *pch
);
98 extern bool pcicore_pmestat(void *pch
);
99 extern void pcie_set_request_size(void *pch
, uint16 size
);
100 extern uint16
pcie_get_request_size(void *pch
);
103 #endif /* _NICPCI_H */