Resync with broadcom drivers 5.100.138.20 and utilities.
[tomato.git] / release / src-rt / include / min_osl.h
blobc7baf4635d3d1999e759f24cda922cdc2024fb7e
1 /*
2 * HND Minimal OS Abstraction Layer.
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: min_osl.h,v 13.31.18.1 2010-05-23 18:21:38 Exp $
21 #ifndef _min_osl_h_
22 #define _min_osl_h_
24 #include <typedefs.h>
25 #include <hndsoc.h>
26 #include <mipsinc.h>
27 #include <bcmstdlib.h>
29 #ifdef mips
30 /* Cache support */
31 extern void caches_on(void);
32 extern void blast_dcache(void);
33 extern void blast_icache(void);
34 #else /* !mips */
35 /* Cache support (or lack thereof) */
36 static inline void caches_on(void) { return; };
37 static inline void blast_dcache(void) { return; };
38 static inline void blast_icache(void) { return; };
39 #endif /* mips */
41 /* assert & debugging */
42 #if defined(BCMDBG)
43 extern void assfail(char *exp, char *file, int line);
44 #define ASSERT(exp) \
45 do { if (!(exp)) assfail(#exp, __FILE__, __LINE__); } while (0)
46 #define TRACE_LOC OSL_UNCACHED(0x180000d0) /* BP access address reg in chipc */
47 #define BCMDBG_TRACE(val) do {*((uint32 *)TRACE_LOC) = val;} while (0)
48 #else
49 #define ASSERT(exp) do {} while (0)
50 #define BCMDBG_TRACE(val) do {} while (0)
51 #endif
53 /* PCMCIA attribute space access macros */
54 #define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
55 ASSERT(0)
56 #define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
57 ASSERT(0)
59 /* PCI configuration space access macros */
60 #define OSL_PCI_READ_CONFIG(loc, offset, size) \
61 (offset == 8 ? 0 : 0xffffffff)
62 #define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
63 do {} while (0)
65 /* PCI device bus # and slot # */
66 #define OSL_PCI_BUS(osh) (0)
67 #define OSL_PCI_SLOT(osh) (0)
69 /* register access macros */
70 #ifdef IL_BIGENDIAN
71 #ifdef BCMHND74K
73 #define wreg32(r, v) (*(volatile uint32 *)((uint32)(r) ^ 4) = (uint32)(v))
74 #define rreg32(r) (*(volatile uint32 *)((uint32)(r) ^ 4))
75 #define wreg16(r, v) (*(volatile uint16 *)((uint32)(r) ^ 6) = (uint16)(v))
76 #define rreg16(r) (*(volatile uint16 *)((uint32)(r) ^ 6))
77 #define wreg8(r, v) (*(volatile uint8 *)((uint32)(r) ^ 7) = (uint8)(v))
78 #define rreg8(r) (*(volatile uint8 *)((uint32)(r) ^ 7))
80 #else /* !BCMHND74K */
82 #define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
83 #define rreg32(r) (*(volatile uint32*)(r))
84 #define wreg16(r, v) (*(volatile uint16 *)((uint32)(r) ^ 2) = (uint16)(v))
85 #define rreg16(r) (*(volatile uint16 *)((uint32)(r) ^ 2))
86 #define wreg8(r, v) (*(volatile uint8 *)((uint32)(r) ^ 3) = (uint8)(v))
87 #define rreg8(r) (*(volatile uint8 *)((uint32)(r) ^ 3))
89 #endif /* BCMHND74K */
91 #else /* !IL_BIGENDIAN */
93 #define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
94 #define rreg32(r) (*(volatile uint32*)(r))
95 #define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
96 #define rreg16(r) (*(volatile uint16*)(r))
97 #define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
98 #define rreg8(r) (*(volatile uint8*)(r))
100 #endif /* IL_BIGENDIAN */
102 #define R_REG(osh, r) ({ \
103 __typeof(*(r)) __osl_v; \
104 switch (sizeof(*(r))) { \
105 case sizeof(uint8): __osl_v = rreg8((void *)(r)); break; \
106 case sizeof(uint16): __osl_v = rreg16((void *)(r)); break; \
107 case sizeof(uint32): __osl_v = rreg32((void *)(r)); break; \
109 __osl_v; \
111 #define W_REG(osh, r, v) do { \
112 switch (sizeof(*(r))) { \
113 case sizeof(uint8): wreg8((void *)(r), (v)); break; \
114 case sizeof(uint16): wreg16((void *)(r), (v)); break; \
115 case sizeof(uint32): wreg32((void *)(r), (v)); break; \
117 } while (0)
118 #define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
119 #define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
121 /* general purpose memory allocation */
122 #define MALLOC(osh, size) malloc(size)
123 #define MFREE(osh, addr, size) free(addr)
124 #define MALLOCED(osh) 0
125 #define MALLOC_FAILED(osh) 0
126 #define MALLOC_DUMP(osh, b)
127 extern int free(void *ptr);
128 extern void *malloc(uint size);
130 /* uncached virtual address */
131 #ifdef __mips__
132 #define OSL_UNCACHED(va) ((void *)KSEG1ADDR((ulong)(va)))
133 #define OSL_CACHED(va) ((void *)KSEG0ADDR((ulong)(va)))
134 #else
135 #define OSL_UNCACHED(va) ((void *)(va))
136 #define OSL_CACHED(va) ((void *)(va))
137 #endif
139 #ifdef __mips__
140 #define OSL_PREF_RANGE_LD(va, sz) prefetch_range_PREF_LOAD_RETAINED(va, sz)
141 #define OSL_PREF_RANGE_ST(va, sz) prefetch_range_PREF_STORE_RETAINED(va, sz)
142 #else /* __mips__ */
143 #define OSL_PREF_RANGE_LD(va, sz)
144 #define OSL_PREF_RANGE_ST(va, sz)
145 #endif /* __mips__ */
147 /* host/bus architecture-specific address byte swap */
148 #define BUS_SWAP32(v) (v)
150 /* microsecond delay */
151 #define OSL_DELAY(usec) udelay(usec)
152 extern void udelay(uint32 usec);
154 /* get processor cycle count */
155 #define OSL_GETCYCLES(x) ((x) = osl_getcycles())
156 extern uint32 osl_getcycles(void);
158 /* map/unmap physical to virtual I/O */
159 #define REG_MAP(pa, size) (OSL_UNCACHED(pa))
160 #define REG_UNMAP(va) do {} while (0)
162 /* dereference an address that may cause a bus exception */
163 #define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
165 /* Misc stubs */
166 #define osl_attach(pdev) ((osl_t*)pdev)
167 #define osl_detach(osh)
169 #define PKTFREESETCB(osh, _tx_fn, _tx_ctx)
171 extern void *osl_init(void);
172 #define OSL_ERROR(bcmerror) osl_error(bcmerror)
173 extern int osl_error(int);
175 /* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
176 #define PKTBUFSZ (MAXPKTBUFSZ - LBUFSZ)
178 /* packet primitives */
179 #define PKTGET(osh, len, send) ((void *)NULL)
180 #define PKTFREE(osh, p, send)
181 #define PKTDATA(osh, lb) ((void *)NULL)
182 #define PKTLEN(osh, lb) 0
183 #define PKTHEADROOM(osh, lb) 0
184 #define PKTTAILROOM(osh, lb) 0
185 #define PKTNEXT(osh, lb) ((void *)NULL)
186 #define PKTSETNEXT(osh, lb, x)
187 #define PKTSETLEN(osh, lb, len)
188 #define PKTPUSH(osh, lb, bytes)
189 #define PKTPULL(osh, lb, bytes)
190 #define PKTDUP(osh, p)
191 #define PKTTAG(lb) ((void *)NULL)
192 #define PKTLINK(lb) ((void *)NULL)
193 #define PKTSETLINK(lb, x)
194 #define PKTPRIO(lb) 0
195 #define PKTSETPRIO(lb, x)
196 #define PKTSHARED(lb) 1
197 #define PKTALLOCED(osh) 0
198 #define PKTLIST_DUMP(osh, buf)
199 #define PKTFRMNATIVE(osh, lb) ((void *)NULL)
200 #define PKTTONATIVE(osh, p) ((struct lbuf *)NULL)
201 #define PKTSETPOOL(osh, lb, x, y) do {} while (0)
202 #define PKTPOOL(osh, lb) FALSE
204 /* Global ASSERT type */
205 extern uint32 g_assert_type;
207 /* Kernel: File Operations: start */
208 #define osl_os_open_image(filename) NULL
209 #define osl_os_get_image_block(buf, len, image) 0
210 #define osl_os_close_image(image) do {} while (0)
211 /* Kernel: File Operations: end */
213 #endif /* _min_osl_h_ */