release/src-rt/include/hndrte_arm.h

   1 /*
   2  * HND Run Time Environment ARM7TDMIs specific.
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
   8  * the contents of this file may not be disclosed to third parties, copied
   9  * or duplicated in any form, in whole or in part, without the prior
  10  * written permission of Broadcom Corporation.
  11  *
  12  * $Id: hndrte_arm.h,v 13.20 2009-01-07 12:54:17 Exp $
  13  */
  14
  15 #ifndef _hndrte_arm_h_
  16 #define _hndrte_arm_h_
  17
  18 #include <sbhndarm.h>
  19 #include <hndarm.h>
  20
  21 /* register access macros */
  22 #define wreg32(r, v)            (*(volatile uint32 *)(r) = (uint32)(v))
  23 #define rreg32(r)               (*(volatile uint32 *)(r))
  24 #ifdef IL_BIGENDIAN
  25 #define wreg16(r, v)            (*(volatile uint16 *)((uintptr)(r) ^ 2) = (uint16)(v))
  26 #define rreg16(r)               (*(volatile uint16 *)((uintptr)(r) ^ 2))
  27 #define wreg8(r, v)             (*(volatile uint8 *)((uintptr)(r) ^ 3) = (uint8)(v))
  28 #define rreg8(r)                (*(volatile uint8 *)((uintptr)(r) ^ 3))
  29 #else
  30 #define wreg16(r, v)            (*(volatile uint16 *)(r) = (uint16)(v))
  31 #define rreg16(r)               (*(volatile uint16 *)(r))
  32 #define wreg8(r, v)             (*(volatile uint8 *)(r) = (uint8)(v))
  33 #define rreg8(r)                (*(volatile uint8 *)(r))
  34 #endif
  35
  36 /* uncached/cached virtual address */
  37 #define hndrte_uncached(va)     ((void *)(va))
  38 #define hndrte_cached(va)       ((void *)(va))
  39
  40 /* host/bus architecture-specific address byte swap */
  41 #define BUS_SWAP32(v)           (v)
  42
  43 /* get cycle counter */
  44 #define osl_getcycles           get_arm_cyclecount
  45
  46 /* map/unmap physical to virtual I/O */
  47 #define hndrte_reg_map(pa, size)        ((void *)(pa))
  48 #define hndrte_reg_unmap(va)            do {} while (0)
  49
  50 /* map/unmap shared (dma-able) memory */
  51 #ifdef CONFIG_XIP
  52
  53 #define MEMORY_REMAP    (SI_ARM_SRAM2)
  54
  55 /*
  56  * arm bootloader memory is remapped but backplane addressing is 0-based
  57  *
  58  * Background: since the mask rom bootloader code executes in a
  59  * read-only memory space apart from SoC RAM, data addresses
  60  * specified by bootloader code must be decoded differently from
  61  * text addresses. Consequently, the processor must run in a
  62  * "memory remap" mode whereby data addresses containing the
  63  * MEMORY_REMAP bit are decoded as residing in SoC RAM. However,
  64  * backplane agents, e.g., the dma engines, always use 0-based
  65  * addresses for SoC RAM, regardless of processor mode.
  66  * Consequently it is necessary to strip the MEMORY_REMAP bit
  67  * from addresses programmed into backplane agents.
  68  */
  69 #define hndrte_dma_map(va, size)        ((uint32)va & ~MEMORY_REMAP)
  70 #else
  71 #define hndrte_dma_map(va, size)        (va)
  72 #endif /* CONFIG_XIP */
  73 #define hndrte_dma_unmap(pa, size)      do {} while (0)
  74
  75 /* Cache support (or lack thereof) */
  76 static inline void caches_on(void) { return; }
  77 static inline void blast_dcache(void) { return; }
  78 static inline void blast_icache(void) { return; }
  79 static inline void flush_dcache(uint32 base, uint size) { return; }
  80 static inline void flush_icache(uint32 base, uint size) { return; }
  81
  82 #endif  /* _hndrte_mips_h_ */