release/src-rt/include/gmac_common.h

   1 /*
   2  * gmacdefs - Broadcom gmac (Unimac) specific definitions
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
   8  * the contents of this file may not be disclosed to third parties, copied
   9  * or duplicated in any form, in whole or in part, without the prior
  10  * written permission of Broadcom Corporation.
  11  * $Id: gmac_common.h,v 13.1.2.1 2010-11-16 21:07:54 Exp $
  12  */
  13
  14 #ifndef _gmac_common_core_h_
  15 #define _gmac_common_core_h_
  16
  17 #ifndef PAD
  18 #define     _PADLINE(line)    pad ## line
  19 #define     _XSTR(line)     _PADLINE(line)
  20 #define     PAD     XSTR(__LINE__)
  21 #endif
  22
  23 typedef volatile struct _gmac_commonregs {
  24     uint32      stag0;
  25     uint32      stag1;
  26     uint32      stag2;
  27     uint32      stag3;
  28     uint32      PAD[4];
  29     uint32      parsercontrol;
  30     uint32      mib_max_len;
  31     uint32      PAD[54];
  32     uint32      phyaccess;
  33     uint32      phycontrol;
  34     uint32      PAD[2];
  35     uint32      gmac0_rgmii_cntl;
  36     uint32      PAD[59];
  37     uint32      cfp_access;
  38     uint32      PAD[3];
  39     uint32      cfp_tcam_data0;
  40     uint32      cfp_tcam_data1;
  41     uint32      cfp_tcam_data2;
  42     uint32      cfp_tcam_data3;
  43     uint32      cfp_tcam_data4;
  44     uint32      cfp_tcam_data5;
  45     uint32      cfp_tcam_data6;
  46     uint32      cfp_tcam_data7;
  47     uint32      cfp_tcam_mask0;
  48     uint32      cfp_tcam_mask1;
  49     uint32      cfp_tcam_mask2;
  50     uint32      cfp_tcam_mask3;
  51     uint32      cfp_tcam_mask4;
  52     uint32      cfp_tcam_mask5;
  53     uint32      cfp_tcam_mask6;
  54     uint32      cfp_tcam_mask7;
  55     uint32      cfp_action_data;
  56     uint32      PAD[19];
  57     uint32      tcam_bist_cntl;
  58     uint32      tcam_bist_status;
  59     uint32      tcam_cmp_status;
  60     uint32      tcam_disable;
  61     uint32      PAD[16];
  62     uint32      tcam_test_cntl;
  63     uint32      PAD[3];
  64     uint32      udf_0_a3_a0;
  65     uint32      udf_0_a7_a4;
  66     uint32      udf_0_a8;
  67     uint32      PAD[1];
  68     uint32      udf_1_a3_a0;
  69     uint32      udf_1_a7_a4;
  70     uint32      udf_1_a8;
  71     uint32      PAD[1];
  72     uint32      udf_2_a3_a0;
  73     uint32      udf_2_a7_a4;
  74     uint32      udf_2_a8;
  75     uint32      PAD[1];
  76     uint32      udf_0_b3_b0;
  77     uint32      udf_0_b7_b4;
  78     uint32      udf_0_b8;
  79     uint32      PAD[1];
  80     uint32      udf_1_b3_b0;
  81     uint32      udf_1_b7_b4;
  82     uint32      udf_1_b8;
  83     uint32      PAD[1];
  84     uint32      udf_2_b3_b0;
  85     uint32      udf_2_b7_b4;
  86     uint32      udf_2_b8;
  87     uint32      PAD[1];
  88     uint32      udf_0_c3_c0;
  89     uint32      udf_0_c7_c4;
  90     uint32      udf_0_c8;
  91     uint32      PAD[1];
  92     uint32      udf_1_c3_c0;
  93     uint32      udf_1_c7_c4;
  94     uint32      udf_1_c8;
  95     uint32      PAD[1];
  96     uint32      udf_2_c3_c0;
  97     uint32      udf_2_c7_c4;
  98     uint32      udf_2_c8;
  99     uint32      PAD[1];
 100     uint32      udf_0_d3_d0;
 101     uint32      udf_0_d7_d4;
 102     uint32      udf_0_d11_d8;
 103 } gmac_commonregs_t;
 104
 105 /*  stag0 offset0x0  */
 106 #define         STAG0_TPID_SHIFT        0
 107 #define         STAG0_TPID_MASK 0xffff
 108
 109 /*  stag1 offset0x4  */
 110 #define         STAG1_TPID_SHIFT        0
 111 #define         STAG1_TPID_MASK 0xffff
 112
 113 /*  stag2 offset0x8  */
 114 #define         STAG2_TPID_SHIFT        0
 115 #define         STAG2_TPID_MASK 0xffff
 116
 117 /*  stag3 offset0xc  */
 118 #define         STAG3_TPID_SHIFT        0
 119 #define         STAG3_TPID_MASK 0xffff
 120
 121 /*  parsercontrol offset0x20  */
 122 #define         PARSERCONTROL_MAX_PARSER_LEN_TH_SHIFT   0
 123 #define         PARSERCONTROL_MAX_PARSER_LEN_TH_MASK    0x3fff
 124
 125 /*  mib_max_len offset0x24  */
 126 #define         MIB_MAX_LEN_MIB_MAX_LEN_SHIFT   0
 127 #define         MIB_MAX_LEN_MIB_MAX_LEN_MASK    0x3fff
 128
 129 /*  phyaccess offset0x100  */
 130 #define         PHYACCESS_TRIGGER_SHIFT 30
 131 #define         PHYACCESS_TRIGGER_MASK  0x40000000
 132 #define         PHYACCESS_WR_CMD_SHIFT  29
 133 #define         PHYACCESS_WR_CMD_MASK   0x20000000
 134 #define         PHYACCESS_CPU_REG_ADDR_SHIFT    24
 135 #define         PHYACCESS_CPU_REG_ADDR_MASK     0x1f000000
 136 #define         PHYACCESS_CPU_PHY_ADDR_SHIFT    16
 137 #define         PHYACCESS_CPU_PHY_ADDR_MASK     0x1f0000
 138 #define         PHYACCESS_ACC_DATA_SHIFT        0
 139 #define         PHYACCESS_ACC_DATA_MASK 0xffff
 140
 141 /*  phycontrol offset0x104  */
 142 #define         PHYCONTROL_SD_ACCESS_EN_SHIFT   25
 143 #define         PHYCONTROL_SD_ACCESS_EN_MASK    0x2000000
 144 #define         PHYCONTROL_NWAY_AUTO_POLLING_EN_SHIFT   24
 145 #define         PHYCONTROL_NWAY_AUTO_POLLING_EN_MASK    0x1000000
 146 #define         PHYCONTROL_MDC_TRANSITION_EN_SHIFT      23
 147 #define         PHYCONTROL_MDC_TRANSITION_EN_MASK       0x800000
 148 #define         PHYCONTROL_MDC_CYCLE_TH_SHIFT   16
 149 #define         PHYCONTROL_MDC_CYCLE_TH_MASK    0x7f0000
 150 #define         PHYCONTROL_EXT_PHY_ADDR_SHIFT   0
 151 #define         PHYCONTROL_EXT_PHY_ADDR_MASK    0x1f
 152
 153 /*  gmac0_rgmii_cntl offset0x110  */
 154 #define         GMAC0_RGMII_CNTL_TIMING_SEL_SHIFT       0
 155 #define         GMAC0_RGMII_CNTL_TIMING_SEL_MASK        0x1
 156 #define         GMAC0_RGMII_CNTL_RGMII_DLL_RXC_BYPASS_SHIFT     1
 157 #define         GMAC0_RGMII_CNTL_RGMII_DLL_RXC_BYPASS_MASK      0x2
 158 #define         GMAC0_RGMII_CNTL_BYPASS_2NS_DEL_SHIFT   2
 159 #define         GMAC0_RGMII_CNTL_BYPASS_2NS_DEL_MASK    0x4
 160 #define         GMAC0_RGMII_CNTL_DEL_STRB_SHIFT 3
 161 #define         GMAC0_RGMII_CNTL_DEL_STRB_MASK  0x8
 162 #define         GMAC0_RGMII_CNTL_DEL_VALUE_SHIFT        4
 163 #define         GMAC0_RGMII_CNTL_DEL_VALUE_MASK 0x70
 164 #define         GMAC0_RGMII_CNTL_DEL_ADDR_SHIFT 7
 165 #define         GMAC0_RGMII_CNTL_DEL_ADDR_MASK  0x780
 166
 167 /*  cfp_access offset0x200  */
 168 #define         CFP_ACCESS_OP_START_DONE_SHIFT  0
 169 #define         CFP_ACCESS_OP_START_DONE_MASK   0x1
 170 #define         CFP_ACCESS_OP_SEL_SHIFT 1
 171 #define         CFP_ACCESS_OP_SEL_MASK  0xe
 172 #define         CFP_ACCESS_CFP_RAM_CLEAR_SHIFT  4
 173 #define         CFP_ACCESS_CFP_RAM_CLEAR_MASK   0x10
 174 #define         CFP_ACCESS_RESERVED1_SHIFT      5
 175 #define         CFP_ACCESS_RESERVED1_MASK       0x3e0
 176 #define         CFP_ACCESS_RAM_SEL_SHIFT        10
 177 #define         CFP_ACCESS_RAM_SEL_MASK 0x7c00
 178 #define         CFP_ACCESS_TCAM_RESET_SHIFT     15
 179 #define         CFP_ACCESS_TCAM_RESET_MASK      0x8000
 180 #define         CFP_ACCESS_XCESS_ADDR_SHIFT     16
 181 #define         CFP_ACCESS_XCESS_ADDR_MASK      0x1ff0000
 182 #define         CFP_ACCESS_RESERVED0_SHIFT      25
 183 #define         CFP_ACCESS_RESERVED0_MASK       0xe000000
 184 #define         CFP_ACCESS_RD_STATUS_SHIFT      28
 185 #define         CFP_ACCESS_RD_STATUS_MASK       0xf0000000
 186
 187 /*  cfp_tcam_data0 offset0x210  */
 188 #define         CFP_TCAM_DATA0_DATA_SHIFT       0
 189 #define         CFP_TCAM_DATA0_DATA_MASK        0xffffffff
 190
 191 /*  cfp_tcam_data1 offset0x214  */
 192 #define         CFP_TCAM_DATA1_DATA_SHIFT       0
 193 #define         CFP_TCAM_DATA1_DATA_MASK        0xffffffff
 194
 195 /*  cfp_tcam_data2 offset0x218  */
 196 #define         CFP_TCAM_DATA2_DATA_SHIFT       0
 197 #define         CFP_TCAM_DATA2_DATA_MASK        0xffffffff
 198
 199 /*  cfp_tcam_data3 offset0x21c  */
 200 #define         CFP_TCAM_DATA3_DATA_SHIFT       0
 201 #define         CFP_TCAM_DATA3_DATA_MASK        0xffffffff
 202
 203 /*  cfp_tcam_data4 offset0x220  */
 204 #define         CFP_TCAM_DATA4_DATA_SHIFT       0
 205 #define         CFP_TCAM_DATA4_DATA_MASK        0xffffffff
 206
 207 /*  cfp_tcam_data5 offset0x224  */
 208 #define         CFP_TCAM_DATA5_DATA_SHIFT       0
 209 #define         CFP_TCAM_DATA5_DATA_MASK        0xffffffff
 210
 211 /*  cfp_tcam_data6 offset0x228  */
 212 #define         CFP_TCAM_DATA6_DATA_SHIFT       0
 213 #define         CFP_TCAM_DATA6_DATA_MASK        0xffffffff
 214
 215 /*  cfp_tcam_data7 offset0x22c  */
 216 #define         CFP_TCAM_DATA7_DATA_SHIFT       0
 217 #define         CFP_TCAM_DATA7_DATA_MASK        0xffffffff
 218
 219 /*  cfp_tcam_mask0 offset0x230  */
 220 #define         CFP_TCAM_MASK0_DATA_SHIFT       0
 221 #define         CFP_TCAM_MASK0_DATA_MASK        0xffffffff
 222
 223 /*  cfp_tcam_mask1 offset0x234  */
 224 #define         CFP_TCAM_MASK1_DATA_SHIFT       0
 225 #define         CFP_TCAM_MASK1_DATA_MASK        0xffffffff
 226
 227 /*  cfp_tcam_mask2 offset0x238  */
 228 #define         CFP_TCAM_MASK2_DATA_SHIFT       0
 229 #define         CFP_TCAM_MASK2_DATA_MASK        0xffffffff
 230
 231 /*  cfp_tcam_mask3 offset0x23c  */
 232 #define         CFP_TCAM_MASK3_DATA_SHIFT       0
 233 #define         CFP_TCAM_MASK3_DATA_MASK        0xffffffff
 234
 235 /*  cfp_tcam_mask4 offset0x240  */
 236 #define         CFP_TCAM_MASK4_DATA_SHIFT       0
 237 #define         CFP_TCAM_MASK4_DATA_MASK        0xffffffff
 238
 239 /*  cfp_tcam_mask5 offset0x244  */
 240 #define         CFP_TCAM_MASK5_DATA_SHIFT       0
 241 #define         CFP_TCAM_MASK5_DATA_MASK        0xffffffff
 242
 243 /*  cfp_tcam_mask6 offset0x248  */
 244 #define         CFP_TCAM_MASK6_DATA_SHIFT       0
 245 #define         CFP_TCAM_MASK6_DATA_MASK        0xffffffff
 246
 247 /*  cfp_tcam_mask7 offset0x24c  */
 248 #define         CFP_TCAM_MASK7_DATA_SHIFT       0
 249 #define         CFP_TCAM_MASK7_DATA_MASK        0xffffffff
 250
 251 /*  cfp_action_data offset0x250  */
 252 #define         CFP_ACTION_DATA_CHAINID_SHIFT   0
 253 #define         CFP_ACTION_DATA_CHAINID_MASK    0xff
 254 #define         CFP_ACTION_DATA_CHANNELID_SHIFT 8
 255 #define         CFP_ACTION_DATA_CHANNELID_MASK  0xf00
 256 #define         CFP_ACTION_DATA_DROP_SHIFT      12
 257 #define         CFP_ACTION_DATA_DROP_MASK       0x1000
 258 #define         CFP_ACTION_DATA_RESERVED_SHIFT  13
 259 #define         CFP_ACTION_DATA_RESERVED_MASK   0xffffe000
 260
 261 /*  tcam_bist_cntl offset0x2a0  */
 262 #define         TCAM_BIST_CNTL_TCAM_BIST_EN_SHIFT       0
 263 #define         TCAM_BIST_CNTL_TCAM_BIST_EN_MASK        0x1
 264 #define         TCAM_BIST_CNTL_TCAM_BIST_TCAM_SEL_SHIFT 1
 265 #define         TCAM_BIST_CNTL_TCAM_BIST_TCAM_SEL_MASK  0x6
 266 #define         TCAM_BIST_CNTL_RESERVED1_SHIFT  3
 267 #define         TCAM_BIST_CNTL_RESERVED1_MASK   0x8
 268 #define         TCAM_BIST_CNTL_TCAM_BIST_STATUS_SEL_SHIFT       4
 269 #define         TCAM_BIST_CNTL_TCAM_BIST_STATUS_SEL_MASK        0xf0
 270 #define         TCAM_BIST_CNTL_TCAM_BIST_SKIP_ERR_CNT_SHIFT     8
 271 #define         TCAM_BIST_CNTL_TCAM_BIST_SKIP_ERR_CNT_MASK      0xff00
 272 #define         TCAM_BIST_CNTL_TCAM_TEST_COMPARE_SHIFT  16
 273 #define         TCAM_BIST_CNTL_TCAM_TEST_COMPARE_MASK   0x10000
 274 #define         TCAM_BIST_CNTL_RESERVED_SHIFT   17
 275 #define         TCAM_BIST_CNTL_RESERVED_MASK    0x7ffe0000
 276 #define         TCAM_BIST_CNTL_TCAM_BIST_DONE_SHIFT     31
 277 #define         TCAM_BIST_CNTL_TCAM_BIST_DONE_MASK      0x80000000
 278
 279 /*  tcam_bist_status offset0x2a4  */
 280 #define         TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT 0
 281 #define         TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK  0xffff
 282 #define         TCAM_BIST_STATUS_RESERVED_SHIFT 16
 283 #define         TCAM_BIST_STATUS_RESERVED_MASK  0xffff0000
 284
 285 /*  tcam_cmp_status offset0x2a8  */
 286 #define         TCAM_CMP_STATUS_TCAM_HIT_ADDR_SHIFT     0
 287 #define         TCAM_CMP_STATUS_TCAM_HIT_ADDR_MASK      0x1ff
 288 #define         TCAM_CMP_STATUS_RESERVED2_SHIFT 9
 289 #define         TCAM_CMP_STATUS_RESERVED2_MASK  0x7e00
 290 #define         TCAM_CMP_STATUS_TCAM_HIT_SHIFT  15
 291 #define         TCAM_CMP_STATUS_TCAM_HIT_MASK   0x8000
 292 #define         TCAM_CMP_STATUS_RESERVED1_SHIFT 16
 293 #define         TCAM_CMP_STATUS_RESERVED1_MASK  0xffff0000
 294
 295 /*  tcam_disable offset0x2ac  */
 296 #define         TCAM_DISABLE_TCAM_DISABLE_SHIFT 0
 297 #define         TCAM_DISABLE_TCAM_DISABLE_MASK  0xf
 298 #define         TCAM_DISABLE_RESERVED_SHIFT     4
 299 #define         TCAM_DISABLE_RESERVED_MASK      0xfffffff0
 300
 301 /*  tcam_test_cntl offset0x2f0  */
 302 #define         TCAM_TEST_CNTL_TCAM_TEST_CNTL_SHIFT     0
 303 #define         TCAM_TEST_CNTL_TCAM_TEST_CNTL_MASK      0x7ff
 304 #define         TCAM_TEST_CNTL_RESERVED_SHIFT   11
 305 #define         TCAM_TEST_CNTL_RESERVED_MASK    0xfffff800
 306
 307 /*  udf_0_a3_a0 offset0x300  */
 308 #define         UDF_0_A3_A0_CFG_UDF_0_A0_SHIFT  0
 309 #define         UDF_0_A3_A0_CFG_UDF_0_A0_MASK   0xff
 310 #define         UDF_0_A3_A0_CFG_UDF_0_A1_SHIFT  8
 311 #define         UDF_0_A3_A0_CFG_UDF_0_A1_MASK   0xff00
 312 #define         UDF_0_A3_A0_CFG_UDF_0_A2_SHIFT  16
 313 #define         UDF_0_A3_A0_CFG_UDF_0_A2_MASK   0xff0000
 314 #define         UDF_0_A3_A0_CFG_UDF_0_A3_SHIFT  24
 315 #define         UDF_0_A3_A0_CFG_UDF_0_A3_MASK   0xff000000
 316
 317 /*  udf_0_a7_a4 offset0x304  */
 318 #define         UDF_0_A7_A4_CFG_UDF_0_A4_SHIFT  0
 319 #define         UDF_0_A7_A4_CFG_UDF_0_A4_MASK   0xff
 320 #define         UDF_0_A7_A4_CFG_UDF_0_A5_SHIFT  8
 321 #define         UDF_0_A7_A4_CFG_UDF_0_A5_MASK   0xff00
 322 #define         UDF_0_A7_A4_CFG_UDF_0_A6_SHIFT  16
 323 #define         UDF_0_A7_A4_CFG_UDF_0_A6_MASK   0xff0000
 324 #define         UDF_0_A7_A4_CFG_UDF_0_A7_SHIFT  24
 325 #define         UDF_0_A7_A4_CFG_UDF_0_A7_MASK   0xff000000
 326
 327 /*  udf_0_a8 offset0x308  */
 328 #define         UDF_0_A8_CFG_UDF_0_A8_SHIFT     0
 329 #define         UDF_0_A8_CFG_UDF_0_A8_MASK      0xff
 330
 331 /*  udf_1_a3_a0 offset0x310  */
 332 #define         UDF_1_A3_A0_CFG_UDF_1_A0_SHIFT  0
 333 #define         UDF_1_A3_A0_CFG_UDF_1_A0_MASK   0xff
 334 #define         UDF_1_A3_A0_CFG_UDF_1_A1_SHIFT  8
 335 #define         UDF_1_A3_A0_CFG_UDF_1_A1_MASK   0xff00
 336 #define         UDF_1_A3_A0_CFG_UDF_1_A2_SHIFT  16
 337 #define         UDF_1_A3_A0_CFG_UDF_1_A2_MASK   0xff0000
 338 #define         UDF_1_A3_A0_CFG_UDF_1_A3_SHIFT  24
 339 #define         UDF_1_A3_A0_CFG_UDF_1_A3_MASK   0xff000000
 340
 341 /*  udf_1_a7_a4 offset0x314  */
 342 #define         UDF_1_A7_A4_CFG_UDF_1_A4_SHIFT  0
 343 #define         UDF_1_A7_A4_CFG_UDF_1_A4_MASK   0xff
 344 #define         UDF_1_A7_A4_CFG_UDF_1_A5_SHIFT  8
 345 #define         UDF_1_A7_A4_CFG_UDF_1_A5_MASK   0xff00
 346 #define         UDF_1_A7_A4_CFG_UDF_1_A6_SHIFT  16
 347 #define         UDF_1_A7_A4_CFG_UDF_1_A6_MASK   0xff0000
 348 #define         UDF_1_A7_A4_CFG_UDF_1_A7_SHIFT  24
 349 #define         UDF_1_A7_A4_CFG_UDF_1_A7_MASK   0xff000000
 350
 351 /*  udf_1_a8 offset0x318  */
 352 #define         UDF_1_A8_CFG_UDF_1_A8_SHIFT     0
 353 #define         UDF_1_A8_CFG_UDF_1_A8_MASK      0xff
 354
 355 /*  udf_2_a3_a0 offset0x320  */
 356 #define         UDF_2_A3_A0_CFG_UDF_2_A0_SHIFT  0
 357 #define         UDF_2_A3_A0_CFG_UDF_2_A0_MASK   0xff
 358 #define         UDF_2_A3_A0_CFG_UDF_2_A1_SHIFT  8
 359 #define         UDF_2_A3_A0_CFG_UDF_2_A1_MASK   0xff00
 360 #define         UDF_2_A3_A0_CFG_UDF_2_A2_SHIFT  16
 361 #define         UDF_2_A3_A0_CFG_UDF_2_A2_MASK   0xff0000
 362 #define         UDF_2_A3_A0_CFG_UDF_2_A3_SHIFT  24
 363 #define         UDF_2_A3_A0_CFG_UDF_2_A3_MASK   0xff000000
 364
 365 /*  udf_2_a7_a4 offset0x324  */
 366 #define         UDF_2_A7_A4_CFG_UDF_2_A4_SHIFT  0
 367 #define         UDF_2_A7_A4_CFG_UDF_2_A4_MASK   0xff
 368 #define         UDF_2_A7_A4_CFG_UDF_2_A5_SHIFT  8
 369 #define         UDF_2_A7_A4_CFG_UDF_2_A5_MASK   0xff00
 370 #define         UDF_2_A7_A4_CFG_UDF_2_A6_SHIFT  16
 371 #define         UDF_2_A7_A4_CFG_UDF_2_A6_MASK   0xff0000
 372 #define         UDF_2_A7_A4_CFG_UDF_2_A7_SHIFT  24
 373 #define         UDF_2_A7_A4_CFG_UDF_2_A7_MASK   0xff000000
 374
 375 /*  udf_2_a8 offset0x328  */
 376 #define         UDF_2_A8_CFG_UDF_2_A8_SHIFT     0
 377 #define         UDF_2_A8_CFG_UDF_2_A8_MASK      0xff
 378
 379 /*  udf_0_b3_b0 offset0x330  */
 380 #define         UDF_0_B3_B0_CFG_UDF_0_B0_SHIFT  0
 381 #define         UDF_0_B3_B0_CFG_UDF_0_B0_MASK   0xff
 382 #define         UDF_0_B3_B0_CFG_UDF_0_B1_SHIFT  8
 383 #define         UDF_0_B3_B0_CFG_UDF_0_B1_MASK   0xff00
 384 #define         UDF_0_B3_B0_CFG_UDF_0_B2_SHIFT  16
 385 #define         UDF_0_B3_B0_CFG_UDF_0_B2_MASK   0xff0000
 386 #define         UDF_0_B3_B0_CFG_UDF_0_B3_SHIFT  24
 387 #define         UDF_0_B3_B0_CFG_UDF_0_B3_MASK   0xff000000
 388
 389 /*  udf_0_b7_b4 offset0x334  */
 390 #define         UDF_0_B7_B4_CFG_UDF_0_B4_SHIFT  0
 391 #define         UDF_0_B7_B4_CFG_UDF_0_B4_MASK   0xff
 392 #define         UDF_0_B7_B4_CFG_UDF_0_B5_SHIFT  8
 393 #define         UDF_0_B7_B4_CFG_UDF_0_B5_MASK   0xff00
 394 #define         UDF_0_B7_B4_CFG_UDF_0_B6_SHIFT  16
 395 #define         UDF_0_B7_B4_CFG_UDF_0_B6_MASK   0xff0000
 396 #define         UDF_0_B7_B4_CFG_UDF_0_B7_SHIFT  24
 397 #define         UDF_0_B7_B4_CFG_UDF_0_B7_MASK   0xff000000
 398
 399 /*  udf_0_b8 offset0x338  */
 400 #define         UDF_0_B8_CFG_UDF_0_B8_SHIFT     0
 401 #define         UDF_0_B8_CFG_UDF_0_B8_MASK      0xff
 402
 403 /*  udf_1_b3_b0 offset0x340  */
 404 #define         UDF_1_B3_B0_CFG_UDF_1_B0_SHIFT  0
 405 #define         UDF_1_B3_B0_CFG_UDF_1_B0_MASK   0xff
 406 #define         UDF_1_B3_B0_CFG_UDF_1_B1_SHIFT  8
 407 #define         UDF_1_B3_B0_CFG_UDF_1_B1_MASK   0xff00
 408 #define         UDF_1_B3_B0_CFG_UDF_1_B2_SHIFT  16
 409 #define         UDF_1_B3_B0_CFG_UDF_1_B2_MASK   0xff0000
 410 #define         UDF_1_B3_B0_CFG_UDF_1_B3_SHIFT  24
 411 #define         UDF_1_B3_B0_CFG_UDF_1_B3_MASK   0xff000000
 412
 413 /*  udf_1_b7_b4 offset0x344  */
 414 #define         UDF_1_B7_B4_CFG_UDF_1_B4_SHIFT  0
 415 #define         UDF_1_B7_B4_CFG_UDF_1_B4_MASK   0xff
 416 #define         UDF_1_B7_B4_CFG_UDF_1_B5_SHIFT  8
 417 #define         UDF_1_B7_B4_CFG_UDF_1_B5_MASK   0xff00
 418 #define         UDF_1_B7_B4_CFG_UDF_1_B6_SHIFT  16
 419 #define         UDF_1_B7_B4_CFG_UDF_1_B6_MASK   0xff0000
 420 #define         UDF_1_B7_B4_CFG_UDF_1_B7_SHIFT  24
 421 #define         UDF_1_B7_B4_CFG_UDF_1_B7_MASK   0xff000000
 422
 423 /*  udf_1_b8 offset0x348  */
 424 #define         UDF_1_B8_CFG_UDF_1_B8_SHIFT     0
 425 #define         UDF_1_B8_CFG_UDF_1_B8_MASK      0xff
 426
 427 /*  udf_2_b3_b0 offset0x350  */
 428 #define         UDF_2_B3_B0_CFG_UDF_2_B0_SHIFT  0
 429 #define         UDF_2_B3_B0_CFG_UDF_2_B0_MASK   0xff
 430 #define         UDF_2_B3_B0_CFG_UDF_2_B1_SHIFT  8
 431 #define         UDF_2_B3_B0_CFG_UDF_2_B1_MASK   0xff00
 432 #define         UDF_2_B3_B0_CFG_UDF_2_B2_SHIFT  16
 433 #define         UDF_2_B3_B0_CFG_UDF_2_B2_MASK   0xff0000
 434 #define         UDF_2_B3_B0_CFG_UDF_2_B3_SHIFT  24
 435 #define         UDF_2_B3_B0_CFG_UDF_2_B3_MASK   0xff000000
 436
 437 /*  udf_2_b7_b4 offset0x354  */
 438 #define         UDF_2_B7_B4_CFG_UDF_2_B4_SHIFT  0
 439 #define         UDF_2_B7_B4_CFG_UDF_2_B4_MASK   0xff
 440 #define         UDF_2_B7_B4_CFG_UDF_2_B5_SHIFT  8
 441 #define         UDF_2_B7_B4_CFG_UDF_2_B5_MASK   0xff00
 442 #define         UDF_2_B7_B4_CFG_UDF_2_B6_SHIFT  16
 443 #define         UDF_2_B7_B4_CFG_UDF_2_B6_MASK   0xff0000
 444 #define         UDF_2_B7_B4_CFG_UDF_2_B7_SHIFT  24
 445 #define         UDF_2_B7_B4_CFG_UDF_2_B7_MASK   0xff000000
 446
 447 /*  udf_2_b8 offset0x358  */
 448 #define         UDF_2_B8_CFG_UDF_2_B8_SHIFT     0
 449 #define         UDF_2_B8_CFG_UDF_2_B8_MASK      0xff
 450
 451 /*  udf_0_c3_c0 offset0x360  */
 452 #define         UDF_0_C3_C0_CFG_UDF_0_C0_SHIFT  0
 453 #define         UDF_0_C3_C0_CFG_UDF_0_C0_MASK   0xff
 454 #define         UDF_0_C3_C0_CFG_UDF_0_C1_SHIFT  8
 455 #define         UDF_0_C3_C0_CFG_UDF_0_C1_MASK   0xff00
 456 #define         UDF_0_C3_C0_CFG_UDF_0_C2_SHIFT  16
 457 #define         UDF_0_C3_C0_CFG_UDF_0_C2_MASK   0xff0000
 458 #define         UDF_0_C3_C0_CFG_UDF_0_C3_SHIFT  24
 459 #define         UDF_0_C3_C0_CFG_UDF_0_C3_MASK   0xff000000
 460
 461 /*  udf_0_c7_c4 offset0x364  */
 462 #define         UDF_0_C7_C4_CFG_UDF_0_C4_SHIFT  0
 463 #define         UDF_0_C7_C4_CFG_UDF_0_C4_MASK   0xff
 464 #define         UDF_0_C7_C4_CFG_UDF_0_C5_SHIFT  8
 465 #define         UDF_0_C7_C4_CFG_UDF_0_C5_MASK   0xff00
 466 #define         UDF_0_C7_C4_CFG_UDF_0_C6_SHIFT  16
 467 #define         UDF_0_C7_C4_CFG_UDF_0_C6_MASK   0xff0000
 468 #define         UDF_0_C7_C4_CFG_UDF_0_C7_SHIFT  24
 469 #define         UDF_0_C7_C4_CFG_UDF_0_C7_MASK   0xff000000
 470
 471 /*  udf_0_c8 offset0x368  */
 472 #define         UDF_0_C8_CFG_UDF_0_C8_SHIFT     0
 473 #define         UDF_0_C8_CFG_UDF_0_C8_MASK      0xff
 474
 475 /*  udf_1_c3_c0 offset0x370  */
 476 #define         UDF_1_C3_C0_CFG_UDF_1_C0_SHIFT  0
 477 #define         UDF_1_C3_C0_CFG_UDF_1_C0_MASK   0xff
 478 #define         UDF_1_C3_C0_CFG_UDF_1_C1_SHIFT  8
 479 #define         UDF_1_C3_C0_CFG_UDF_1_C1_MASK   0xff00
 480 #define         UDF_1_C3_C0_CFG_UDF_1_C2_SHIFT  16
 481 #define         UDF_1_C3_C0_CFG_UDF_1_C2_MASK   0xff0000
 482 #define         UDF_1_C3_C0_CFG_UDF_1_C3_SHIFT  24
 483 #define         UDF_1_C3_C0_CFG_UDF_1_C3_MASK   0xff000000
 484
 485 /*  udf_1_c7_c4 offset0x374  */
 486 #define         UDF_1_C7_C4_CFG_UDF_1_C4_SHIFT  0
 487 #define         UDF_1_C7_C4_CFG_UDF_1_C4_MASK   0xff
 488 #define         UDF_1_C7_C4_CFG_UDF_1_C5_SHIFT  8
 489 #define         UDF_1_C7_C4_CFG_UDF_1_C5_MASK   0xff00
 490 #define         UDF_1_C7_C4_CFG_UDF_1_C6_SHIFT  16
 491 #define         UDF_1_C7_C4_CFG_UDF_1_C6_MASK   0xff0000
 492 #define         UDF_1_C7_C4_CFG_UDF_1_C7_SHIFT  24
 493 #define         UDF_1_C7_C4_CFG_UDF_1_C7_MASK   0xff000000
 494
 495 /*  udf_1_c8 offset0x378  */
 496 #define         UDF_1_C8_CFG_UDF_1_C8_SHIFT     0
 497 #define         UDF_1_C8_CFG_UDF_1_C8_MASK      0xff
 498
 499 /*  udf_2_c3_c0 offset0x380  */
 500 #define         UDF_2_C3_C0_CFG_UDF_2_C0_SHIFT  0
 501 #define         UDF_2_C3_C0_CFG_UDF_2_C0_MASK   0xff
 502 #define         UDF_2_C3_C0_CFG_UDF_2_C1_SHIFT  8
 503 #define         UDF_2_C3_C0_CFG_UDF_2_C1_MASK   0xff00
 504 #define         UDF_2_C3_C0_CFG_UDF_2_C2_SHIFT  16
 505 #define         UDF_2_C3_C0_CFG_UDF_2_C2_MASK   0xff0000
 506 #define         UDF_2_C3_C0_CFG_UDF_2_C3_SHIFT  24
 507 #define         UDF_2_C3_C0_CFG_UDF_2_C3_MASK   0xff000000
 508
 509 /*  udf_2_c7_c4 offset0x384  */
 510 #define         UDF_2_C7_C4_CFG_UDF_2_C4_SHIFT  0
 511 #define         UDF_2_C7_C4_CFG_UDF_2_C4_MASK   0xff
 512 #define         UDF_2_C7_C4_CFG_UDF_2_C5_SHIFT  8
 513 #define         UDF_2_C7_C4_CFG_UDF_2_C5_MASK   0xff00
 514 #define         UDF_2_C7_C4_CFG_UDF_2_C6_SHIFT  16
 515 #define         UDF_2_C7_C4_CFG_UDF_2_C6_MASK   0xff0000
 516 #define         UDF_2_C7_C4_CFG_UDF_2_C7_SHIFT  24
 517 #define         UDF_2_C7_C4_CFG_UDF_2_C7_MASK   0xff000000
 518
 519 /*  udf_2_c8 offset0x388  */
 520 #define         UDF_2_C8_CFG_UDF_2_C8_SHIFT     0
 521 #define         UDF_2_C8_CFG_UDF_2_C8_MASK      0xff
 522
 523 /*  udf_0_d3_d0 offset0x390  */
 524 #define         UDF_0_D3_D0_CFG_UDF_0_D0_SHIFT  0
 525 #define         UDF_0_D3_D0_CFG_UDF_0_D0_MASK   0xff
 526 #define         UDF_0_D3_D0_CFG_UDF_0_D1_SHIFT  8
 527 #define         UDF_0_D3_D0_CFG_UDF_0_D1_MASK   0xff00
 528 #define         UDF_0_D3_D0_CFG_UDF_0_D2_SHIFT  16
 529 #define         UDF_0_D3_D0_CFG_UDF_0_D2_MASK   0xff0000
 530 #define         UDF_0_D3_D0_CFG_UDF_0_D3_SHIFT  24
 531 #define         UDF_0_D3_D0_CFG_UDF_0_D3_MASK   0xff000000
 532
 533 /*  udf_0_d7_d4 offset0x394  */
 534 #define         UDF_0_D7_D4_CFG_UDF_0_D4_SHIFT  0
 535 #define         UDF_0_D7_D4_CFG_UDF_0_D4_MASK   0xff
 536 #define         UDF_0_D7_D4_CFG_UDF_0_D5_SHIFT  8
 537 #define         UDF_0_D7_D4_CFG_UDF_0_D5_MASK   0xff00
 538 #define         UDF_0_D7_D4_CFG_UDF_0_D6_SHIFT  16
 539 #define         UDF_0_D7_D4_CFG_UDF_0_D6_MASK   0xff0000
 540 #define         UDF_0_D7_D4_CFG_UDF_0_D7_SHIFT  24
 541 #define         UDF_0_D7_D4_CFG_UDF_0_D7_MASK   0xff000000
 542
 543 /*  udf_0_d11_d8 offset0x398  */
 544 #define         UDF_0_D11_D8_CFG_UDF_0_D8_SHIFT 0
 545 #define         UDF_0_D11_D8_CFG_UDF_0_D8_MASK  0xff
 546 #define         UDF_0_D11_D8_CFG_UDF_0_D9_SHIFT 8
 547 #define         UDF_0_D11_D8_CFG_UDF_0_D9_MASK  0xff00
 548 #define         UDF_0_D11_D8_CFG_UDF_0_D10_SHIFT        16
 549 #define         UDF_0_D11_D8_CFG_UDF_0_D10_MASK 0xff0000
 550 #define         UDF_0_D11_D8_CFG_UDF_0_D11_SHIFT        24
 551 #define         UDF_0_D11_D8_CFG_UDF_0_D11_MASK 0xff000000
 552
 553 #endif /* _gmac_common_core_h_ */