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Resync with broadcom drivers 5.100.138.20 and utilities.
[tomato.git] / release / src-rt / include / d11.h
blob00f5725cf75832cdb8360856fef2843884bf6cf7
1 /*
2 * Chip-specific hardware definitions for
3 * Broadcom 802.11abg Networking Device Driver
4 *
5 * Copyright (C) 2010, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
9 * the contents of this file may not be disclosed to third parties, copied
10 * or duplicated in any form, in whole or in part, without the prior
11 * written permission of Broadcom Corporation.
12 *
13 * $Id: d11.h,v 13.549.2.55 2011-02-03 02:22:07 Exp $
14 */
15
16 #ifndef _D11_H
17 #define _D11_H
18
19 #include <typedefs.h>
20 #include <bcmdevs.h>
21 #include <hndsoc.h>
22 #include <sbhndpio.h>
23 #include <sbhnddma.h>
24 #include <proto/802.11.h>
25
26 #ifndef _TYPEDEFS_H_
27 #include <typedefs.h>
28 #endif
29
30 /* This marks the start of a packed structure section. */
31 #include <packed_section_start.h>
32
33
34 #ifndef WL_RSSI_ANT_MAX
35 #define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
36 #elif WL_RSSI_ANT_MAX != 4
37 #error "WL_RSSI_ANT_MAX does not match"
38 #endif
39
40 /* cpp contortions to concatenate w/arg prescan */
41 #ifndef PAD
42 #define _PADLINE(line) pad ## line
43 #define _XSTR(line) _PADLINE(line)
44 #define PAD _XSTR(__LINE__)
45 #endif
46
47 #define BCN_TMPL_LEN 512 /* length of the BCN template area */
48 #define LPRS_TMPL_LEN 512 /* length of the legacy PRS template area */
49
50 /* RX FIFO numbers */
51 #define RX_FIFO 0 /* data and ctl frames */
52 #define RX_TXSTATUS_FIFO 3 /* RX fifo for tx status packages */
53
54 /* TX FIFO numbers using WME Access Classes */
55 #define TX_AC_BK_FIFO 0 /* Access Category Background TX FIFO */
56 #define TX_AC_BE_FIFO 1 /* Access Category Best-Effort TX FIFO */
57 #define TX_AC_VI_FIFO 2 /* Access Class Video TX FIFO */
58 #define TX_AC_VO_FIFO 3 /* Access Class Voice TX FIFO */
59 #define TX_BCMC_FIFO 4 /* Broadcast/Multicast TX FIFO */
60 #define TX_ATIM_FIFO 5 /* TX fifo for ATIM window info */
61
62 /* Addr is byte address used by SW; offset is word offset used by uCode */
63
64 /* Per AC TX limit settings */
65 #define M_AC_TXLMT_BASE_ADDR (0x180 * 2)
66 #define M_AC_TXLMT_ADDR(_ac) (M_AC_TXLMT_BASE_ADDR + (2 * (_ac)))
67
68 /* Legacy TX FIFO numbers */
69 #define TX_DATA_FIFO TX_AC_BE_FIFO
70 #define TX_CTL_FIFO TX_AC_VO_FIFO
71
72
73 /* delay from end of PLCP reception to RxTSFTime */
74 #define M_APHY_PLCPRX_DLY 3
75 #define M_BPHY_PLCPRX_DLY 4
76
77 typedef volatile struct {
78 uint32 intstatus;
79 uint32 intmask;
80 } intctrlregs_t;
81
82 /* read: 32-bit register that can be read as 32-bit or as 2 16-bit
83 * write: only low 16b-it half can be written
84 */
85 typedef volatile union {
86 uint32 pmqhostdata; /* read only! */
87 struct {
88 uint16 pmqctrlstatus; /* read/write */
89 uint16 PAD;
90 } w;
91 } pmqreg_t;
92
93 /* pio register set 2/4 bytes union for d11 fifo */
94 typedef volatile union {
95 pio2regp_t b2; /* < corerev 8 */
96 pio4regp_t b4; /* >= corerev 8 */
97 } u_pioreg_t;
98
99 /* dma/pio corerev < 11 */
100 typedef volatile struct {
101 dma32regp_t dmaregs[8]; /* 0x200 - 0x2fc */
102 u_pioreg_t pioregs[8]; /* 0x300 */
103 } fifo32_t;
104
105 /* dma/pio corerev >= 11 */
106 typedef volatile struct {
107 dma64regs_t dmaxmt; /* dma tx */
108 pio4regs_t piotx; /* pio tx */
109 dma64regs_t dmarcv; /* dma rx */
110 pio4regs_t piorx; /* pio rx */
111 } fifo64_t;
112
113 /*
114 * Host Interface Registers
115 * - primed from hnd_cores/dot11mac/systemC/registers/ihr.h
116 * - but definitely not complete
117 */
118 typedef volatile struct _d11regs {
119 /* Device Control ("semi-standard host registers") */
120 uint32 PAD[3]; /* 0x0 - 0x8 */
121 uint32 biststatus; /* 0xC */
122 uint32 biststatus2; /* 0x10 */
123 uint32 PAD; /* 0x14 */
124 uint32 gptimer; /* 0x18 */ /* for corerev >= 3 */
125 uint32 usectimer; /* 0x1c */ /* for corerev >= 26 */
126
127 /* Interrupt Control */ /* 0x20 */
128 intctrlregs_t intctrlregs[8];
129
130 uint32 PAD[40]; /* 0x60 - 0xFC */
131
132 /* tx fifos 6-7 and rx fifos 1-3 removed in corerev 5 */
133 uint32 intrcvlazy[4]; /* 0x100 - 0x10C */
134
135 uint32 PAD[4]; /* 0x110 - 0x11c */
136
137 uint32 maccontrol; /* 0x120 */
138 uint32 maccommand; /* 0x124 */
139 uint32 macintstatus; /* 0x128 */
140 uint32 macintmask; /* 0x12C */
141
142 /* Transmit Template Access */
143 uint32 tplatewrptr; /* 0x130 */
144 uint32 tplatewrdata; /* 0x134 */
145 uint32 PAD[2]; /* 0x138 - 0x13C */
146
147 /* PMQ registers */
148 pmqreg_t pmqreg; /* 0x140 */
149 uint32 pmqpatl; /* 0x144 */
150 uint32 pmqpath; /* 0x148 */
151 uint32 PAD; /* 0x14C */
152
153 uint32 chnstatus; /* 0x150 */
154 uint32 psmdebug; /* 0x154 */ /* for corerev >= 3 */
155 uint32 phydebug; /* 0x158 */ /* for corerev >= 3 */
156 uint32 machwcap; /* 0x15C */ /* Corerev >= 13 */
157
158 /* Extended Internal Objects */
159 uint32 objaddr; /* 0x160 */
160 uint32 objdata; /* 0x164 */
161 uint32 PAD[2]; /* 0x168 - 0x16c */
162
163 /* New txstatus registers on corerev >= 5 */
164 uint32 frmtxstatus; /* 0x170 */
165 uint32 frmtxstatus2; /* 0x174 */
166 uint32 PAD[2]; /* 0x178 - 0x17c */
167
168 /* New TSF host access on corerev >= 3 */
169
170 uint32 tsf_timerlow; /* 0x180 */
171 uint32 tsf_timerhigh; /* 0x184 */
172 uint32 tsf_cfprep; /* 0x188 */
173 uint32 tsf_cfpstart; /* 0x18c */
174 uint32 tsf_cfpmaxdur32; /* 0x190 */
175 uint32 PAD[3]; /* 0x194 - 0x19c */
176
177 uint32 maccontrol1; /* 0x1a0 */
178 uint32 machwcap1; /* 0x1a4 */
179 uint32 PAD[14]; /* 0x1a8 - 0x1dc */
180
181 /* Clock control and hardware workarounds (corerev >= 13) */
182 uint32 clk_ctl_st; /* 0x1e0 */
183 uint32 hw_war;
184 uint32 d11_phypllctl; /* 0x1e8 (corerev == 16), the phypll request/avail bits are
185 * moved to clk_ctl_st for corerev >= 17
186 */
187 uint32 PAD[5]; /* 0x1ec - 0x1fc */
188
189 /* 0x200-0x37F dma/pio registers */
190 volatile union {
191 fifo32_t f32regs; /* tx fifos 6-7 and rx fifos 1-3 (corerev < 5) */
192 fifo64_t f64regs[6]; /* on corerev >= 11 */
193 } fifo;
194
195 /* FIFO diagnostic port access */
196 dma32diag_t dmafifo; /* 0x380 - 0x38C */
197
198 uint32 aggfifocnt; /* 0x390 */
199 uint32 aggfifodata; /* 0x394 */
200 uint32 PAD[16]; /* 0x398 - 0x3d4 */
201 uint16 radioregaddr; /* 0x3d8 */
202 uint16 radioregdata; /* 0x3da */
203
204 /* time delay between the change on rf disable input and radio shutdown corerev 10 */
205 uint32 rfdisabledly; /* 0x3DC */
206
207 /* PHY register access */
208 uint16 phyversion; /* 0x3e0 - 0x0 */
209 uint16 phybbconfig; /* 0x3e2 - 0x1 */
210 uint16 phyadcbias; /* 0x3e4 - 0x2 Bphy only */
211 uint16 phyanacore; /* 0x3e6 - 0x3 pwwrdwn on aphy */
212 uint16 phyrxstatus0; /* 0x3e8 - 0x4 */
213 uint16 phyrxstatus1; /* 0x3ea - 0x5 */
214 uint16 phycrsth; /* 0x3ec - 0x6 */
215 uint16 phytxerror; /* 0x3ee - 0x7 */
216 uint16 phychannel; /* 0x3f0 - 0x8 */
217 uint16 PAD[1]; /* 0x3f2 - 0x9 */
218 uint16 phytest; /* 0x3f4 - 0xa */
219 uint16 phy4waddr; /* 0x3f6 - 0xb */
220 uint16 phy4wdatahi; /* 0x3f8 - 0xc */
221 uint16 phy4wdatalo; /* 0x3fa - 0xd */
222 uint16 phyregaddr; /* 0x3fc - 0xe */
223 uint16 phyregdata; /* 0x3fe - 0xf */
224
225 /* IHR */ /* 0x400 - 0x7FE */
226
227 /* RXE Block */
228 uint16 PAD[3]; /* 0x400 - 0x406 */
229 uint16 rcv_fifo_ctl; /* 0x406 */
230 uint16 PAD; /* 0x408 - 0x40a */
231 uint16 rcv_frm_cnt; /* 0x40a */
232 uint16 PAD[4]; /* 0x40a - 0x414 */
233 uint16 rssi; /* 0x414 */
234 uint16 PAD[5]; /* 0x414 - 0x420 */
235 uint16 rcm_ctl; /* 0x420 */
236 uint16 rcm_mat_data; /* 0x422 */
237 uint16 rcm_mat_mask; /* 0x424 */
238 uint16 rcm_mat_dly; /* 0x426 */
239 uint16 rcm_cond_mask_l; /* 0x428 */
240 uint16 rcm_cond_mask_h; /* 0x42A */
241 uint16 rcm_cond_dly; /* 0x42C */
242 uint16 PAD[1]; /* 0x42E */
243 uint16 ext_ihr_addr; /* 0x430 */
244 uint16 ext_ihr_data; /* 0x432 */
245 uint16 rxe_phyrs_2; /* 0x434 */
246 uint16 rxe_phyrs_3; /* 0x436 */
247 uint16 phy_mode; /* 0x438 */
248 uint16 rcmta_ctl; /* 0x43a */
249 uint16 rcmta_size; /* 0x43c */
250 uint16 rcmta_addr0; /* 0x43e */
251 uint16 rcmta_addr1; /* 0x440 */
252 uint16 rcmta_addr2; /* 0x442 */
253 uint16 PAD[30]; /* 0x444 - 0x480 */
254
255 /* PSM Block */ /* 0x480 - 0x500 */
256
257 uint16 PAD; /* 0x480 */
258 uint16 psm_maccontrol_h; /* 0x482 */
259 uint16 psm_macintstatus_l; /* 0x484 */
260 uint16 psm_macintstatus_h; /* 0x486 */
261 uint16 psm_macintmask_l; /* 0x488 */
262 uint16 psm_macintmask_h; /* 0x48A */
263 uint16 PAD; /* 0x48C */
264 uint16 psm_maccommand; /* 0x48E */
265 uint16 psm_brc; /* 0x490 */
266 uint16 psm_phy_hdr_param; /* 0x492 */
267 uint16 psm_postcard; /* 0x494 */
268 uint16 psm_pcard_loc_l; /* 0x496 */
269 uint16 psm_pcard_loc_h; /* 0x498 */
270 uint16 psm_gpio_in; /* 0x49A */
271 uint16 psm_gpio_out; /* 0x49C */
272 uint16 psm_gpio_oe; /* 0x49E */
273
274 uint16 psm_bred_0; /* 0x4A0 */
275 uint16 psm_bred_1; /* 0x4A2 */
276 uint16 psm_bred_2; /* 0x4A4 */
277 uint16 psm_bred_3; /* 0x4A6 */
278 uint16 psm_brcl_0; /* 0x4A8 */
279 uint16 psm_brcl_1; /* 0x4AA */
280 uint16 psm_brcl_2; /* 0x4AC */
281 uint16 psm_brcl_3; /* 0x4AE */
282 uint16 psm_brpo_0; /* 0x4B0 */
283 uint16 psm_brpo_1; /* 0x4B2 */
284 uint16 psm_brpo_2; /* 0x4B4 */
285 uint16 psm_brpo_3; /* 0x4B6 */
286 uint16 psm_brwk_0; /* 0x4B8 */
287 uint16 psm_brwk_1; /* 0x4BA */
288 uint16 psm_brwk_2; /* 0x4BC */
289 uint16 psm_brwk_3; /* 0x4BE */
290
291 uint16 psm_base_0; /* 0x4C0 */
292 uint16 psm_base_1; /* 0x4C2 */
293 uint16 psm_base_2; /* 0x4C4 */
294 uint16 psm_base_3; /* 0x4C6 */
295 uint16 psm_base_4; /* 0x4C8 */
296 uint16 psm_base_5; /* 0x4CA */
297 uint16 psm_base_6; /* 0x4CC */
298 uint16 psm_pc_reg_0; /* 0x4CE */
299 uint16 psm_pc_reg_1; /* 0x4D0 */
300 uint16 psm_pc_reg_2; /* 0x4D2 */
301 uint16 psm_pc_reg_3; /* 0x4D4 */
302 uint16 PAD[0xD]; /* 0x4D6 - 0x4DE */
303 uint16 psm_corectlsts; /* 0x4f0 */ /* Corerev >= 13 */
304 uint16 PAD[0x7]; /* 0x4f2 - 0x4fE */
305
306 /* TXE0 Block */ /* 0x500 - 0x580 */
307 uint16 txe_ctl; /* 0x500 */
308 uint16 txe_aux; /* 0x502 */
309 uint16 txe_ts_loc; /* 0x504 */
310 uint16 txe_time_out; /* 0x506 */
311 uint16 txe_wm_0; /* 0x508 */
312 uint16 txe_wm_1; /* 0x50A */
313 uint16 txe_phyctl; /* 0x50C */
314 uint16 txe_status; /* 0x50E */
315 uint16 txe_mmplcp0; /* 0x510 */
316 uint16 txe_mmplcp1; /* 0x512 */
317 uint16 txe_phyctl1; /* 0x514 */
318
319 uint16 PAD[0x05]; /* 0x510 - 0x51E */
320
321 /* Transmit control */
322 uint16 xmtfifodef; /* 0x520 */
323 uint16 xmtfifo_frame_cnt; /* 0x522 */ /* Corerev >= 16 */
324 uint16 xmtfifo_byte_cnt; /* 0x524 */ /* Corerev >= 16 */
325 uint16 xmtfifo_head; /* 0x526 */ /* Corerev >= 16 */
326 uint16 xmtfifo_rd_ptr; /* 0x528 */ /* Corerev >= 16 */
327 uint16 xmtfifo_wr_ptr; /* 0x52A */ /* Corerev >= 16 */
328 uint16 xmtfifodef1; /* 0x52C */ /* Corerev >= 16 */
329
330 /* AggFifo */
331 uint16 aggfifo_cmd; /* 0x52e */
332 uint16 aggfifo_stat; /* 0x530 */
333 uint16 aggfifo_cfgctl; /* 0x532 */
334 uint16 aggfifo_cfgdata; /* 0x534 */
335 uint16 aggfifo_mpdunum; /* 0x536 */
336 uint16 aggfifo_len; /* 0x538 */
337 uint16 aggfifo_bmp; /* 0x53A */
338 uint16 aggfifo_ackedcnt; /* 0x53C */
339 uint16 aggfifo_sel; /* 0x53E */
340
341 uint16 xmtfifocmd; /* 0x540 */
342 uint16 xmtfifoflush; /* 0x542 */
343 uint16 xmtfifothresh; /* 0x544 */
344 uint16 xmtfifordy; /* 0x546 */
345 uint16 xmtfifoprirdy; /* 0x548 */
346 uint16 xmtfiforqpri; /* 0x54A */
347 uint16 xmttplatetxptr; /* 0x54C */
348 uint16 PAD; /* 0x54E */
349 uint16 xmttplateptr; /* 0x550 */
350 uint16 smpl_clct_strptr; /* 0x552 */ /* Corerev >= 22 */
351 uint16 smpl_clct_stpptr; /* 0x554 */ /* Corerev >= 22 */
352 uint16 smpl_clct_curptr; /* 0x556 */ /* Corerev >= 22 */
353 uint16 aggfifo_data; /* 0x558 */
354 uint16 PAD[0x03]; /* 0x55A - 0x55E */
355 uint16 xmttplatedatalo; /* 0x560 */
356 uint16 xmttplatedatahi; /* 0x562 */
357
358 uint16 PAD[2]; /* 0x564 - 0x566 */
359
360 uint16 xmtsel; /* 0x568 */
361 uint16 xmttxcnt; /* 0x56A */
362 uint16 xmttxshmaddr; /* 0x56C */
363
364 uint16 PAD[0x09]; /* 0x56E - 0x57E */
365
366 /* TXE1 Block */
367 uint16 PAD[0x40]; /* 0x580 - 0x5FE */
368
369 /* TSF Block */
370 uint16 PAD[0X02]; /* 0x600 - 0x602 */
371 uint16 tsf_cfpstrt_l; /* 0x604 */
372 uint16 tsf_cfpstrt_h; /* 0x606 */
373 uint16 PAD[0X05]; /* 0x608 - 0x610 */
374 uint16 tsf_cfppretbtt; /* 0x612 */
375 uint16 PAD[0XD]; /* 0x614 - 0x62C */
376 uint16 tsf_clk_frac_l; /* 0x62E */
377 uint16 tsf_clk_frac_h; /* 0x630 */
378 uint16 PAD[0X14]; /* 0x632 - 0x658 */
379 uint16 tsf_random; /* 0x65A */
380 uint16 PAD[0x05]; /* 0x65C - 0x664 */
381 /* GPTimer 2 registers are corerev >= 3 */
382 uint16 tsf_gpt2_stat; /* 0x666 */
383 uint16 tsf_gpt2_ctr_l; /* 0x668 */
384 uint16 tsf_gpt2_ctr_h; /* 0x66A */
385 uint16 tsf_gpt2_val_l; /* 0x66C */
386 uint16 tsf_gpt2_val_h; /* 0x66E */
387 uint16 tsf_gptall_stat; /* 0x670 */
388 uint16 PAD[0x07]; /* 0x672 - 0x67E */
389
390 /* IFS Block */
391 uint16 ifs_sifs_rx_tx_tx; /* 0x680 */
392 uint16 ifs_sifs_nav_tx; /* 0x682 */
393 uint16 ifs_slot; /* 0x684 */
394 uint16 PAD; /* 0x686 */
395 uint16 ifs_ctl; /* 0x688 */
396 uint16 PAD[0x3]; /* 0x68a - 0x68F */
397 uint16 ifsstat; /* 0x690 */
398 uint16 ifsmedbusyctl; /* 0x692 */
399 uint16 iftxdur; /* 0x694 */
400 uint16 PAD[0x3]; /* 0x696 - 0x69b */
401 /* EDCF support in dot11macs with corerevs >= 16 */
402 uint16 ifs_aifsn; /* 0x69c */
403 uint16 ifs_ctl1; /* 0x69e */
404
405 /* New slow clock registers on corerev >= 5 */
406 uint16 scc_ctl; /* 0x6a0 */
407 uint16 scc_timer_l; /* 0x6a2 */
408 uint16 scc_timer_h; /* 0x6a4 */
409 uint16 scc_frac; /* 0x6a6 */
410 uint16 scc_fastpwrup_dly; /* 0x6a8 */
411 uint16 scc_per; /* 0x6aa */
412 uint16 scc_per_frac; /* 0x6ac */
413 uint16 scc_cal_timer_l; /* 0x6ae */
414 uint16 scc_cal_timer_h; /* 0x6b0 */
415 uint16 PAD; /* 0x6b2 */
416
417 /* BTCX block on corerev >=13 */
418 uint16 btcx_ctrl; /* 0x6b4 */
419 uint16 btcx_stat; /* 0x6b6 */
420 uint16 btcx_trans_ctrl; /* 0x6b8 */
421 uint16 btcx_pri_win; /* 0x6ba */
422 uint16 btcx_tx_conf_timer; /* 0x6bc */
423 uint16 btcx_ant_sw_timer; /* 0x6be */
424
425 uint16 btcx_prv_rfact_timer; /* 0x6c0 */
426 uint16 btcx_cur_rfact_timer; /* 0x6c2 */
427 uint16 btcx_rfact_dur_timer; /* 0x6c4 */
428
429 uint16 PAD[21]; /* 0x6c6 - 0x6ee */
430
431 /* ECI regs on corerev >=14 */
432 uint16 btcx_eci_addr; /* 0x6f0 */
433 uint16 btcx_eci_data; /* 0x6f2 */
434
435 uint16 PAD[6];
436
437 /* NAV Block */
438 uint16 nav_ctl; /* 0x700 */
439 uint16 navstat; /* 0x702 */
440 uint16 PAD[0x3e]; /* 0x702 - 0x77E */
441
442 /* WEP/PMQ Block */ /* 0x780 - 0x7FE */
443 uint16 PAD[0x20]; /* 0x780 - 0x7BE */
444
445 uint16 wepctl; /* 0x7C0 */
446 uint16 wepivloc; /* 0x7C2 */
447 uint16 wepivkey; /* 0x7C4 */
448 uint16 wepwkey; /* 0x7C6 */
449
450 uint16 PAD[4]; /* 0x7C8 - 0x7CE */
451 uint16 pcmctl; /* 0X7D0 */
452 uint16 pcmstat; /* 0X7D2 */
453 uint16 PAD[6]; /* 0x7D4 - 0x7DE */
454
455 uint16 pmqctl; /* 0x7E0 */
456 uint16 pmqstatus; /* 0x7E2 */
457 uint16 pmqpat0; /* 0x7E4 */
458 uint16 pmqpat1; /* 0x7E6 */
459 uint16 pmqpat2; /* 0x7E8 */
460
461 uint16 pmqdat; /* 0x7EA */
462 uint16 pmqdator; /* 0x7EC */
463 uint16 pmqhst; /* 0x7EE */
464 uint16 pmqpath0; /* 0x7F0 */
465 uint16 pmqpath1; /* 0x7F2 */
466 uint16 pmqpath2; /* 0x7F4 */
467 uint16 pmqdath; /* 0x7F6 */
468
469 uint16 PAD[0x04]; /* 0x7F8 - 0x7FE */
470
471 /* SHM */ /* 0x800 - 0xEFE */
472 uint16 PAD[0x380]; /* 0x800 - 0xEFE */
473
474 /* SB configuration registers: 0xF00 */
475 sbconfig_t sbconfig; /* sb config regs occupy top 256 bytes */
476 } d11regs_t;
477
478 #define PIHR_BASE 0x0400 /* byte address of packed IHR region */
479
480 /* biststatus */
481 #define BT_DONE (1U << 31) /* bist done */
482 #define BT_B2S (1 << 30) /* bist2 ram summary bit */
483
484 /* intstatus and intmask */
485 #define I_PC (1 << 10) /* pci descriptor error */
486 #define I_PD (1 << 11) /* pci data error */
487 #define I_DE (1 << 12) /* descriptor protocol error */
488 #define I_RU (1 << 13) /* receive descriptor underflow */
489 #define I_RO (1 << 14) /* receive fifo overflow */
490 #define I_XU (1 << 15) /* transmit fifo underflow */
491 #define I_RI (1 << 16) /* receive interrupt */
492 #define I_XI (1 << 24) /* transmit interrupt */
493
494 /* interrupt receive lazy */
495 #define IRL_TO_MASK 0x00ffffff /* timeout */
496 #define IRL_FC_MASK 0xff000000 /* frame count */
497 #define IRL_FC_SHIFT 24 /* frame count */
498
499 /* maccontrol register */
500 #define MCTL_GMODE (1U << 31)
501 #define MCTL_DISCARD_PMQ (1 << 30)
502 #define MCTL_DISCARD_TXSTATUS (1 << 29)
503 #define MCTL_TBTT_HOLD (1 << 28)
504 #define MCTL_CLOSED_NETWORK (1 << 27)
505 #define MCTL_WAKE (1 << 26)
506 #define MCTL_HPS (1 << 25)
507 #define MCTL_PROMISC (1 << 24)
508 #define MCTL_KEEPBADFCS (1 << 23)
509 #define MCTL_KEEPCONTROL (1 << 22)
510 #define MCTL_PHYLOCK (1 << 21)
511 #define MCTL_BCNS_PROMISC (1 << 20)
512 #define MCTL_LOCK_RADIO (1 << 19)
513 #define MCTL_AP (1 << 18)
514 #define MCTL_INFRA (1 << 17)
515 #define MCTL_BIGEND (1 << 16)
516 #define MCTL_GPOUT_SEL_MASK (3 << 14)
517 #define MCTL_GPOUT_SEL_SHIFT 14
518 #define MCTL_EN_PSMDBG (1 << 13)
519 #define MCTL_IHR_EN (1 << 10)
520 #define MCTL_SHM_UPPER (1 << 9)
521 #define MCTL_SHM_EN (1 << 8)
522 #define MCTL_PSM_JMP_0 (1 << 2)
523 #define MCTL_PSM_RUN (1 << 1)
524 #define MCTL_EN_MAC (1 << 0)
525
526 /* maccontrol1 register */
527 #define MCTL1_GCPS 0x00000001
528 #define MCTL1_EGS_MASK 0x0000c000
529 #define MCTL1_EGS_SHIFT 14
530 #define MCTL1_EGS_MASK_REV26 0x00001f00
531 #define MCTL1_EGS_SHIFT_REV26 8
532
533 /* maccommand register */
534 #define MCMD_BCN0VLD (1 << 0)
535 #define MCMD_BCN1VLD (1 << 1)
536 #define MCMD_DIRFRMQVAL (1 << 2)
537 #define MCMD_CCA (1 << 3)
538 #define MCMD_BG_NOISE (1 << 4)
539 #define MCMD_SKIP_SHMINIT (1 << 5) /* only used for simulation */
540 #define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /* reuse for sample collect */
541
542 /* macintstatus/macintmask */
543 #define MI_MACSSPNDD (1 << 0) /* MAC has gracefully suspended */
544 #define MI_BCNTPL (1 << 1) /* beacon template available */
545 #define MI_TBTT (1 << 2) /* TBTT indication */
546 #define MI_BCNSUCCESS (1 << 3) /* beacon successfully tx'd */
547 #define MI_BCNCANCLD (1 << 4) /* beacon canceled (IBSS) */
548 #define MI_ATIMWINEND (1 << 5) /* end of ATIM-window (IBSS) */
549 #define MI_PMQ (1 << 6) /* PMQ entries available */
550 #define MI_NSPECGEN_0 (1 << 7) /* non-specific gen-stat bits that are set by PSM */
551 #define MI_NSPECGEN_1 (1 << 8) /* non-specific gen-stat bits that are set by PSM */
552 #define MI_MACTXERR (1 << 9) /* MAC level Tx error */
553 #define MI_NSPECGEN_3 (1 << 10) /* non-specific gen-stat bits that are set by PSM */
554 #define MI_PHYTXERR (1 << 11) /* PHY Tx error */
555 #define MI_PME (1 << 12) /* Power Management Event */
556 #define MI_GP0 (1 << 13) /* General-purpose timer0 */
557 #define MI_GP1 (1 << 14) /* General-purpose timer1 */
558 #define MI_DMAINT (1 << 15) /* (ORed) DMA-interrupts */
559 #define MI_TXSTOP (1 << 16) /* MAC has completed a TX FIFO Suspend/Flush */
560 #define MI_CCA (1 << 17) /* MAC has completed a CCA measurement */
561 #define MI_BG_NOISE (1 << 18) /* MAC has collected background noise samples */
562 #define MI_DTIM_TBTT (1 << 19) /* MBSS DTIM TBTT indication */
563 #define MI_PRQ (1 << 20) /* Probe response queue needs attention */
564 #define MI_PWRUP (1 << 21) /* Radio/PHY has been powered back up. */
565 #define MI_BT_RFACT_STUCK (1 << 22) /* MAC has detected invalid BT_RFACT pin */
566 #define MI_BT_PRED_REQ (1 << 23) /* MAC requested driver BTCX predictor calc */
567 #define MI_P2P (1 << 25) /* WiFi P2P interrupt */
568 #define MI_DMATX (1 << 26) /* MAC new frame ready */
569 #define MI_TSSI_LIMIT (1 << 27) /* Tssi Limit Reach, TxIdx=0 Interrupt */
570 #define MI_RFDISABLE (1 << 28) /* MAC detected a change on RF Disable input
571 * (corerev >= 10)
572 */
573 #define MI_TFS (1 << 29) /* MAC has completed a TX (corerev >= 5) */
574 #define MI_PHYCHANGED (1 << 30) /* A phy status change wrt G mode */
575 #define MI_TO (1U << 31) /* general purpose timeout (corerev >= 3) */
576
577 /* Mac capabilities registers */
578 /* machwcap */
579 #define MCAP_TKIPMIC 0x80000000 /* TKIP MIC hardware present */
580 #define MCAP_TKIPPH2KEY 0x40000000 /* TKIP phase 2 key hardware present */
581 #define MCAP_BTCX 0x20000000 /* BT coexistence hardware and pins present */
582 #define MCAP_MBSS 0x10000000 /* Multi-BSS hardware present */
583 #define MCAP_RXFSZ_MASK 0x03f80000 /* Rx fifo size (* 512 bytes) */
584 #define MCAP_RXFSZ_SHIFT 19
585 #define MCAP_NRXQ_MASK 0x00070000 /* Max Rx queues supported - 1 */
586 #define MCAP_NRXQ_SHIFT 16
587 #define MCAP_UCMSZ_MASK 0x0000e000 /* Ucode memory size */
588 #define MCAP_UCMSZ_3K3 0 /* 3328 Words Ucode memory, in unit of 50-bit */
589 #define MCAP_UCMSZ_4K 1 /* 4096 Words Ucode memory */
590 #define MCAP_UCMSZ_5K 2 /* 5120 Words Ucode memory */
591 #define MCAP_UCMSZ_6K 3 /* 6144 Words Ucode memory */
592 #define MCAP_UCMSZ_8K 4 /* 8192 Words Ucode memory */
593 #define MCAP_UCMSZ_SHIFT 13
594 #define MCAP_TXFSZ_MASK 0x00000ff8 /* Tx fifo size (* 512 bytes) */
595 #define MCAP_TXFSZ_SHIFT 3
596 #define MCAP_NTXQ_MASK 0x00000007 /* Max Tx queues supported - 1 */
597 #define MCAP_NTXQ_SHIFT 0
598
599 /* machwcap1 */
600 #define MCAP1_ERC_MASK 0x00000001 /* external radio coexistence */
601 #define MCAP1_ERC_SHIFT 0
602 #define MCAP1_SHMSZ_MASK 0x0000000e /* shm size (corerev >= 16) */
603 #define MCAP1_SHMSZ_SHIFT 1
604 #define MCAP1_SHMSZ_1K 0 /* 1024 words in unit of 32-bit */
605 #define MCAP1_SHMSZ_2K 1 /* 1536 words in unit of 32-bit */
606
607 /* BTCX control */
608 #define BTCX_CTRL_EN 0x0001 /* Enable BTCX module */
609 #define BTCX_CTRL_SW 0x0002 /* Enable software override */
610
611 /* BTCX status */
612 #define BTCX_STAT_RA 0x0001 /* RF_ACTIVE state */
613
614 /* BTCX transaction control */
615 #define BTCX_TRANS_ANTSEL 0x0040 /* ANTSEL output */
616 #define BTCX_TRANS_TXCONF 0x0080 /* TX_CONF output */
617
618 /* pmqhost data */
619 #define PMQH_DATA_MASK 0xffff0000 /* data entry of head pmq entry */
620 #define PMQH_BSSCFG 0x00100000 /* PM entry for BSS config */
621 #define PMQH_PMOFF 0x00010000 /* PM Mode OFF: power save off */
622 #define PMQH_PMON 0x00020000 /* PM Mode ON: power save on */
623 #define PMQH_DASAT 0x00040000 /* Dis-associated or De-authenticated */
624 #define PMQH_ATIMFAIL 0x00080000 /* ATIM not acknowledged */
625 #define PMQH_DEL_ENTRY 0x00000001 /* delete head entry */
626 #define PMQH_DEL_MULT 0x00000002 /* delete head entry to cur read pointer -1 */
627 #define PMQH_OFLO 0x00000004 /* pmq overflow indication */
628 #define PMQH_NOT_EMPTY 0x00000008 /* entries are present in pmq */
629
630 /* phydebug (corerev >= 3) */
631 #define PDBG_CRS (1 << 0) /* phy is asserting carrier sense */
632 #define PDBG_TXA (1 << 1) /* phy is taking xmit byte from mac this cycle */
633 #define PDBG_TXF (1 << 2) /* mac is instructing the phy to transmit a frame */
634 #define PDBG_TXE (1 << 3) /* phy is signalling a transmit Error to the mac */
635 #define PDBG_RXF (1 << 4) /* phy detected the end of a valid frame preamble */
636 #define PDBG_RXS (1 << 5) /* phy detected the end of a valid PLCP header */
637 #define PDBG_RXFRG (1 << 6) /* rx start not asserted */
638 #define PDBG_RXV (1 << 7) /* mac is taking receive byte from phy this cycle */
639 #define PDBG_RFD (1 << 16) /* RF portion of the radio is disabled */
640
641 /* objaddr register */
642 #define OBJADDR_SEL_MASK 0x000F0000
643 #define OBJADDR_UCM_SEL 0x00000000
644 #define OBJADDR_SHM_SEL 0x00010000
645 #define OBJADDR_SCR_SEL 0x00020000
646 #define OBJADDR_IHR_SEL 0x00030000
647 #define OBJADDR_RCMTA_SEL 0x00040000
648 #define OBJADDR_SRCHM_SEL 0x00060000
649 #define OBJADDR_WINC 0x01000000
650 #define OBJADDR_RINC 0x02000000
651 #define OBJADDR_AUTO_INC 0x03000000
652
653 /* pcmaddr bits */
654 #define PCMADDR_INC 0x4000
655 #define PCMADDR_UCM_SEL 0x0000
656
657 #define WEP_PCMADDR 0x07d4
658 #define WEP_PCMDATA 0x07d6
659
660 /* frmtxstatus */
661 #define TXS_V (1 << 0) /* valid bit */
662 #define TXS_STATUS_MASK 0xffff
663 /* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */
664 #define TXS_COMPAT_MASK 0x3
665 #define TXS_COMPAT_SHIFT 1
666 #define TXS_FID_MASK 0xffff0000
667 #define TXS_FID_SHIFT 16
668
669 /* frmtxstatus2 */
670 #define TXS_SEQ_MASK 0xffff
671 #define TXS_PTX_MASK 0xff0000
672 #define TXS_PTX_SHIFT 16
673 #define TXS_MU_MASK 0x01000000
674 #define TXS_MU_SHIFT 24
675
676 /* clk_ctl_st, corerev >= 17 */
677 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /* d11 core pll request */
678 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /* PHY pll request */
679 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /* d11 core pll available */
680 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /* PHY pll available */
681
682 /* HT Cloclk Ctrl and Clock Avail for 4313 */
683 #define CCS_ERSRC_REQ_HT 0x00000010 /* HT avail request */
684 #define CCS_ERSRC_AVAIL_HT 0x00020000 /* HT clock available */
685
686 /* d11_pwrctl, corerev16 only */
687 #define D11_PHYPLL_AVAIL_REQ 0x000010000 /* request PHY PLL resource */
688 #define D11_PHYPLL_AVAIL_STS 0x001000000 /* PHY PLL is available */
689
690
691 /* tsf_cfprep register */
692 #define CFPREP_CBI_MASK 0xffffffc0
693 #define CFPREP_CBI_SHIFT 6
694 #define CFPREP_CFPP 0x00000001
695
696 /* transmit fifo control for 2-byte pio */
697 #define XFC_BV_MASK 0x3 /* bytes valid */
698 #define XFC_LO (1 << 0) /* low byte valid */
699 #define XFC_HI (1 << 1) /* high byte valid */
700 #define XFC_BOTH (XFC_HI | XFC_LO) /* both bytes valid */
701 #define XFC_EF (1 << 2) /* end of frame */
702 #define XFC_FR (1 << 3) /* frame ready */
703 #define XFC_FL (1 << 5) /* flush request */
704 #define XFC_FP (1 << 6) /* flush pending */
705 #define XFC_SE (1 << 7) /* suspend request */
706 #define XFC_SP (1 << 8)
707 #define XFC_CC_MASK 0xfc00 /* committed count */
708 #define XFC_CC_SHIFT 10
709
710 /* transmit fifo control for 4-byte pio */
711 #define XFC4_BV_MASK 0xf /* bytes valid */
712 #define XFC4_EF (1 << 4) /* end of frame */
713 #define XFC4_FR (1 << 7) /* frame ready */
714 #define XFC4_SE (1 << 8) /* suspend request */
715 #define XFC4_SP (1 << 9)
716 #define XFC4_FL (1 << 10) /* flush request */
717 #define XFC4_FP (1 << 11) /* flush pending */
718
719 /* receive fifo control */
720 #define RFC_FR (1 << 0) /* frame ready */
721 #define RFC_DR (1 << 1) /* data ready */
722
723 /* tx fifo sizes for corerev >= 9 */
724 /* tx fifo sizes values are in terms of 256 byte blocks */
725 #define TXFIFOCMD_RESET_MASK (1 << 15) /* reset */
726 #define TXFIFOCMD_FIFOSEL_SHIFT 8 /* fifo */
727 #define TXFIFO_FIFOTOP_SHIFT 8 /* fifo start */
728
729 /* Must redefine to 65 for 16 MBSS */
730 #ifdef WLLPRS
731 #define TXFIFO_START_BLK16 (65+16) /* Base address + 32 * 512 B/P + 8 * 512 11g P */
732 #else /* WLLPRS */
733 #define TXFIFO_START_BLK16 65 /* Base address + 32 * 512 B/P */
734 #endif /* WLLPRS */
735 #define TXFIFO_START_BLK 6 /* Base address + 6 * 256 B */
736 #define TXFIFO_SIZE_UNIT 256 /* one unit corresponds to 256 bytes */
737 #define MBSS16_TEMPLMEM_MINBLKS 65 /* one unit corresponds to 256 bytes */
738
739 /* phy versions, PhyVersion:Revision field */
740 #define PV_AV_MASK 0xf000 /* analog block version */
741 #define PV_AV_SHIFT 12 /* analog block version bitfield offset */
742 #define PV_PT_MASK 0x0f00 /* phy type */
743 #define PV_PT_SHIFT 8 /* phy type bitfield offset */
744 #define PV_PV_MASK 0x000f /* phy version */
745 #define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT)
746
747 /* phy types, PhyVersion:PhyType field */
748 #define PHY_TYPE_A 0 /* A-Phy value */
749 #define PHY_TYPE_B 1 /* B-Phy value */
750 #define PHY_TYPE_G 2 /* G-Phy value */
751 #define PHY_TYPE_N 4 /* N-Phy value */
752 #define PHY_TYPE_LP 5 /* LP-Phy value */
753 #define PHY_TYPE_SSN 6 /* SSLPN-Phy value */
754 #define PHY_TYPE_HT 7 /* 3x3 HTPhy value */
755 #define PHY_TYPE_LCN 8 /* LCN-Phy value */
756 #define PHY_TYPE_LCNXN 9 /* LCNXN-Phy value */
757 #define PHY_TYPE_LCN40 10 /* LCN40-Phy value */
758 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
759
760 /* analog types, PhyVersion:AnalogType field */
761 #define ANA_11G_018 1
762 #define ANA_11G_018_ALL 2
763 #define ANA_11G_018_ALLI 3
764 #define ANA_11G_013 4
765 #define ANA_11N_013 5
766 #define ANA_11LP_013 6
767
768 /* 802.11a PLCP header def */
769 typedef struct ofdm_phy_hdr ofdm_phy_hdr_t;
770 BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr {
771 uint8 rlpt[3]; /* rate, length, parity, tail */
772 uint16 service;
773 uint8 pad;
774 } BWL_POST_PACKED_STRUCT;
775
776 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f)
777 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01)
778 #define D11A_PHY_HDR_GLENGTH(phdr) (((uint32 *)((phdr)->rlpt) >> 5) & 0x0fff)
779 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01)
780 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f)
781
782 /* rate encoded per 802.11a-1999 sec 17.3.4.1 */
783 #define D11A_PHY_HDR_SRATE(phdr, rate) \
784 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf))
785 /* set reserved field to zero */
786 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef)
787 /* length is number of octets in PSDU */
788 #define D11A_PHY_HDR_SLENGTH(phdr, length) \
789 (*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \
790 (((length) & 0x0fff) << 5))
791 /* set the tail to all zeros */
792 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03)
793
794 #define D11A_PHY_HDR_LEN_L 3 /* low-rate part of PLCP header */
795 #define D11A_PHY_HDR_LEN_R 2 /* high-rate part of PLCP header */
796
797 #define D11A_PHY_TX_DELAY (2) /* 2.1 usec */
798
799 #define D11A_PHY_HDR_TIME (4) /* low-rate part of PLCP header */
800 #define D11A_PHY_PRE_TIME (16)
801 #define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME)
802
803 /* 802.11b PLCP header def */
804 typedef struct cck_phy_hdr cck_phy_hdr_t;
805 BWL_PRE_PACKED_STRUCT struct cck_phy_hdr {
806 uint8 signal;
807 uint8 service;
808 uint16 length;
809 uint16 crc;
810 } BWL_POST_PACKED_STRUCT;
811
812 #define D11B_PHY_HDR_LEN 6
813
814 #define D11B_PHY_TX_DELAY (3) /* 3.4 usec */
815
816 #define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3)
817 #define D11B_PHY_LPRE_TIME (144)
818 #define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME)
819
820 #define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1)
821 #define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1)
822 #define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME)
823
824 #define D11B_PLCP_SIGNAL_LOCKED (1 << 2)
825 #define D11B_PLCP_SIGNAL_LE (1 << 7)
826
827 /* AMPDUXXX: move to ht header file once it is ready: Mimo PLCP */
828 #define MIMO_PLCP_MCS_MASK 0x7f /* mcs index */
829 #define MIMO_PLCP_40MHZ 0x80 /* 40 Hz frame */
830 #define MIMO_PLCP_AMPDU 0x08 /* ampdu */
831
832 #define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8))
833 #define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8))
834 #define WLC_SET_MIMO_PLCP_LEN(plcp, len) \
835 plcp[1] = len & 0xff; plcp[2] = ((len >> 8) & 0xff);
836
837 #define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU)
838 #define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU)
839 #define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU)
840
841 /* The dot11a PLCP header is 5 bytes. To simplify the software (so that we
842 * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header has
843 * padding added in the ucode.
844 */
845 #define D11_PHY_HDR_LEN 6
846
847 /* TX DMA buffer header */
848 typedef struct d11txh d11txh_t;
849 BWL_PRE_PACKED_STRUCT struct d11txh {
850 uint16 MacTxControlLow; /* 0x0 */
851 uint16 MacTxControlHigh; /* 0x1 */
852 uint16 MacFrameControl; /* 0x2 */
853 uint16 TxFesTimeNormal; /* 0x3 */
854 uint16 PhyTxControlWord; /* 0x4 */
855 uint16 PhyTxControlWord_1; /* 0x5 */
856 uint16 PhyTxControlWord_1_Fbr; /* 0x6 */
857 uint16 PhyTxControlWord_1_Rts; /* 0x7 */
858 uint16 PhyTxControlWord_1_FbrRts; /* 0x8 */
859 uint16 MainRates; /* 0x9 */
860 uint16 XtraFrameTypes; /* 0xa */
861 uint8 IV[16]; /* 0x0b - 0x12 */
862 uint8 TxFrameRA[6]; /* 0x13 - 0x15 */
863 uint16 TxFesTimeFallback; /* 0x16 */
864 uint8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */
865 uint16 RTSDurFallback; /* 0x1a */
866 uint8 FragPLCPFallback[6]; /* 0x1b - 1d */
867 uint16 FragDurFallback; /* 0x1e */
868 uint16 MModeLen; /* 0x1f */
869 uint16 MModeFbrLen; /* 0x20 */
870 uint16 TstampLow; /* 0x21 */
871 uint16 TstampHigh; /* 0x22 */
872 uint16 ABI_MimoAntSel; /* 0x23 */
873 uint16 PreloadSize; /* 0x24 */
874 uint16 AmpduSeqCtl; /* 0x25 */
875 uint16 TxFrameID; /* 0x26 */
876 uint16 TxStatus; /* 0x27 */
877 uint16 MaxNMpdus; /* 0x28 corerev >=16 */
878 union {
879 uint16 MaxAggDur; /* 0x29 corerev >=16 */
880 uint16 MaxAggLen;
881 } u1;
882 union {
883 uint16 MaxRNum; /* 0x2a corerev >=16 */
884 uint16 MaxAggLen_FBR;
885 } u2;
886 uint16 MinMBytes; /* 0x2b corerev >=16 */
887 uint8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */
888 struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */
889 uint16 PAD; /* 0x37 */
890 } BWL_POST_PACKED_STRUCT;
891
892 #define D11_TXH_LEN 112 /* bytes */
893
894 /* Frame Types */
895 #define FT_CCK 0
896 #define FT_OFDM 1
897 #define FT_HT 2
898 #define FT_N 3
899
900 /* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */
901 #define TXC_AMPDU_SHIFT 9 /* shift for ampdu settings */
902 #define TXC_AMPDU_NONE 0 /* Regular MPDU, not an A-MPDU */
903 #define TXC_AMPDU_FIRST 1 /* first MPDU of an A-MPDU */
904 #define TXC_AMPDU_MIDDLE 2 /* intermediate MPDU of an A-MPDU */
905 #define TXC_AMPDU_LAST 3 /* last (or single) MPDU of an A-MPDU */
906
907 /* MacTxControlLow */
908 #define TXC_AMIC 0x8000
909 #define TXC_USERIFS 0x4000
910 #define TXC_LIFETIME 0x2000
911 #define TXC_FRAMEBURST 0x1000
912 #define TXC_SENDCTS 0x0800
913 #define TXC_AMPDU_MASK 0x0600
914 #define TXC_BW_40 0x0100
915 #define TXC_FREQBAND_5G 0x0080
916 #define TXC_DFCS 0x0040
917 #define TXC_IGNOREPMQ 0x0020
918 #define TXC_HWSEQ 0x0010
919 #define TXC_STARTMSDU 0x0008
920 #define TXC_SENDRTS 0x0004
921 #define TXC_LONGFRAME 0x0002
922 #define TXC_IMMEDACK 0x0001
923
924 /* MacTxControlHigh */
925 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */
926 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */
927 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /* Main fallback rate preamble type
928 * 1 = SHORT for OFDM/GF for MIMO
929 * 0 = LONG for CCK/MM for MIMO
930 */
931 /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */
932 #define TXC_AMPDU_FBR 0x1000 /* use fallback rate for this AMPDU */
933 #define TXC_SECKEY_MASK 0x0FF0
934 #define TXC_SECKEY_SHIFT 4
935 #define TXC_ALT_TXPWR 0x0008 /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */
936 #define TXC_SECTYPE_MASK 0x0007
937 #define TXC_SECTYPE_SHIFT 0
938
939 /* Null delimiter for Fallback rate */
940 #define AMPDU_FBR_NULL_DELIM 5 /* Location of Null delimiter count for AMPDU */
941
942 /* PhyTxControl for Mimophy */
943 #define PHY_TXC_PWR_MASK 0xFC00
944 #define PHY_TXC_PWR_SHIFT 10
945 #define PHY_TXC_ANT_MASK 0x03C0 /* bit 6, 7, 8, 9 */
946 #define PHY_TXC_ANT_SHIFT 6
947 #define PHY_TXC_ANT_0_1 0x00C0 /* auto, last rx */
948 #define PHY_TXC_LPPHY_ANT_LAST 0x0000
949 #define PHY_TXC_ANT_3 0x0200 /* virtual antenna 3 */
950 #define PHY_TXC_ANT_2 0x0100 /* virtual antenna 2 */
951 #define PHY_TXC_ANT_1 0x0080 /* virtual antenna 1 */
952 #define PHY_TXC_ANT_0 0x0040 /* virtual antenna 0 */
953 #define PHY_TXC_SHORT_HDR 0x0010
954 #define PHY_TXC_FT_MASK 0x0003
955 #define PHY_TXC_FT_CCK 0x0000
956 #define PHY_TXC_FT_OFDM 0x0001
957 #define PHY_TXC_FT_HT 0x0002
958 #define PHY_TXC_FT_11N 0x0003
959
960 #define PHY_TXC_OLD_ANT_0 0x0000
961 #define PHY_TXC_OLD_ANT_1 0x0100
962 #define PHY_TXC_OLD_ANT_LAST 0x0300
963
964 /* PhyTxControl_1 for Mimophy */
965 #define PHY_TXC1_BW_MASK 0x0007
966 #define PHY_TXC1_BW_10MHZ 0
967 #define PHY_TXC1_BW_10MHZ_UP 1
968 #define PHY_TXC1_BW_20MHZ 2
969 #define PHY_TXC1_BW_20MHZ_UP 3
970 #define PHY_TXC1_BW_40MHZ 4
971 #define PHY_TXC1_BW_40MHZ_DUP 5
972 #define PHY_TXC1_MODE_SHIFT 3
973 #define PHY_TXC1_MODE_MASK 0x0038
974 #define PHY_TXC1_MODE_SISO 0
975 #define PHY_TXC1_MODE_CDD 1
976 #define PHY_TXC1_MODE_STBC 2
977 #define PHY_TXC1_MODE_SDM 3
978 #define PHY_TXC1_CODE_RATE_SHIFT 8
979 #define PHY_TXC1_CODE_RATE_MASK 0x0700
980 #define PHY_TXC1_CODE_RATE_1_2 0
981 #define PHY_TXC1_CODE_RATE_2_3 1
982 #define PHY_TXC1_CODE_RATE_3_4 2
983 #define PHY_TXC1_CODE_RATE_4_5 3
984 #define PHY_TXC1_CODE_RATE_5_6 4
985 #define PHY_TXC1_CODE_RATE_7_8 6
986 #define PHY_TXC1_MOD_SCHEME_SHIFT 11
987 #define PHY_TXC1_MOD_SCHEME_MASK 0x3800
988 #define PHY_TXC1_MOD_SCHEME_BPSK 0
989 #define PHY_TXC1_MOD_SCHEME_QPSK 1
990 #define PHY_TXC1_MOD_SCHEME_QAM16 2
991 #define PHY_TXC1_MOD_SCHEME_QAM64 3
992 #define PHY_TXC1_MOD_SCHEME_QAM256 4
993
994 /* PhyTxControl for HTphy that are different from Mimophy */
995 #define PHY_TXC_HTANT_MASK 0x3fC0 /* bit 6, 7, 8, 9, 10, 11, 12, 13 */
996 #define PHY_TXC_HTCORE_MASK 0x03C0 /* core enable core3:core0, 1=enable, 0=disable */
997 #define PHY_TXC_HTCORE_SHIFT 6 /* bit 6, 7, 8, 9 */
998 #define PHY_TXC_HTANT_IDX_MASK 0x3C00 /* 4-bit, 16 possible antenna configuration */
999 #define PHY_TXC_HTANT_IDX_SHIFT 10
1000 #define PHY_TXC_HTANT_IDX0 0
1001 #define PHY_TXC_HTANT_IDX1 1
1002 #define PHY_TXC_HTANT_IDX2 2
1003 #define PHY_TXC_HTANT_IDX3 3
1004
1005 /* PhyTxControl_1 for HTphy that are different from Mimophy */
1006 #define PHY_TXC1_HTSPARTIAL_MAP_MASK 0x7C00 /* bit 14:10 */
1007 #define PHY_TXC1_HTSPARTIAL_MAP_SHIFT 10
1008 #define PHY_TXC1_HTTXPWR_OFFSET_MASK 0x01f8 /* bit 8:3 */
1009 #define PHY_TXC1_HTTXPWR_OFFSET_SHIFT 3
1010
1011 /* XtraFrameTypes */
1012 #define XFTS_RTS_FT_SHIFT 2
1013 #define XFTS_FBRRTS_FT_SHIFT 4
1014 #define XFTS_CHANNEL_SHIFT 8
1015
1016 /* Antenna diversity bit in ant_wr_settle */
1017 #define PHY_AWS_ANTDIV 0x2000
1018
1019 /* PHY CRS states */
1020 #define APHY_CRS_RESET 0
1021 #define APHY_CRS_SEARCH 1
1022 #define APHY_CRS_CLIP 3
1023 #define APHY_CRS_G_CLIP_POW1 4
1024 #define APHY_CRS_G_CLIP_POW2 5
1025 #define APHY_CRS_G_CLIP_NRSSI1 6
1026 #define APHY_CRS_G_CLIP_NRSSI1_POW1 7
1027 #define APHY_CRS_G_CLIP_NRSSI2 8
1028
1029 /* IFS ctl */
1030 #define IFS_USEEDCF (1 << 2)
1031
1032 /* IFS ctl1 */
1033 #define IFS_CTL1_EDCRS (1 << 3)
1034 #define IFS_CTL1_EDCRS_20L (1 << 4)
1035 #define IFS_CTL1_EDCRS_40 (1 << 5)
1036 #define IFS_EDCRS_MASK (IFS_CTL1_EDCRS | IFS_CTL1_EDCRS_20L | IFS_CTL1_EDCRS_40)
1037 #define IFS_EDCRS_SHIFT 3
1038
1039 /* ABI_MimoAntSel */
1040 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00
1041 #define ABI_MAS_ADDR_BMP_IDX_SHIFT 8
1042 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0
1043 #define ABI_MAS_FBR_ANT_PTN_SHIFT 4
1044 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f
1045
1046 /* MinMBytes */
1047 #define MINMBYTES_PKT_LEN_MASK 0x0300
1048 #define MINMBYTES_FBRATE_PWROFFSET_MASK 0xFC00
1049 #define MINMBYTES_FBRATE_PWROFFSET_SHIFT 10
1050
1051 /* tx status packet for core rev 4 */
1052 typedef struct tx_status_cr4 tx_status_cr4_t;
1053 BWL_PRE_PACKED_STRUCT struct tx_status_cr4 {
1054 uint16 framelen;
1055 uint16 PAD;
1056 uint16 frameid;
1057 uint16 status;
1058 uint16 lasttxtime;
1059 uint16 sequence;
1060 uint16 phyerr;
1061 uint16 ackphyrxsh;
1062 } BWL_POST_PACKED_STRUCT;
1063
1064
1065 /* Generic tx status packet for software use. This is independent of hardware
1066 * structure for a particular core. Hardware structure should be read and converted
1067 * to this structure before being sent for the sofware consumption.
1068 */
1069 typedef struct tx_status tx_status_t;
1070 BWL_PRE_PACKED_STRUCT struct tx_status {
1071 uint16 framelen;
1072 uint16 frameid;
1073 uint16 status;
1074 uint16 sequence;
1075 uint32 lasttxtime;
1076 uint16 phyerr;
1077 uint16 ackphyrxsh;
1078 } BWL_POST_PACKED_STRUCT;
1079
1080 #define TXSTATUS_LEN 16
1081
1082 /* status field bit definitions */
1083 #define TX_STATUS_FRM_RTX_MASK 0xF000
1084 #define TX_STATUS_FRM_RTX_SHIFT 12
1085 #define TX_STATUS_RTS_RTX_MASK 0x0F00
1086 #define TX_STATUS_RTS_RTX_SHIFT 8
1087 #define TX_STATUS_MASK 0x00FE
1088 #define TX_STATUS_PMINDCTD (1 << 7) /* PM mode indicated to AP */
1089 #define TX_STATUS_INTERMEDIATE (1 << 6) /* intermediate or 1st ampdu pkg */
1090 #define TX_STATUS_AMPDU (1 << 5) /* AMPDU status */
1091 #define TX_STATUS_SUPR_MASK 0x1C /* suppress status bits (4:2) */
1092 #define TX_STATUS_SUPR_SHIFT 2
1093 #define TX_STATUS_ACK_RCV (1 << 1) /* ACK received */
1094 #define TX_STATUS_VALID (1 << 0) /* Tx status valid (corerev >= 5) */
1095 #define TX_STATUS_NO_ACK 0
1096
1097 /* suppress status reason codes */
1098 #define TX_STATUS_SUPR_PMQ (1 << 2) /* PMQ entry */
1099 #define TX_STATUS_SUPR_FLUSH (2 << 2) /* flush request */
1100 #define TX_STATUS_SUPR_FRAG (3 << 2) /* previous frag failure */
1101 #define TX_STATUS_SUPR_TBTT (3 << 2) /* SHARED: Probe response supr for TBTT */
1102 #define TX_STATUS_SUPR_BADCH (4 << 2) /* channel mismatch */
1103 #define TX_STATUS_SUPR_EXPTIME (5 << 2) /* lifetime expiry */
1104 #define TX_STATUS_SUPR_UF (6 << 2) /* underflow */
1105 #if defined(WLAFTERBURNER) || defined(WLP2P)
1106 #define TX_STATUS_SUPR_NACK_ABS (7 << 2) /* BSS entered ABSENCE period or afterburner NACK */
1107 #endif
1108
1109 /* Unexpected tx status for rate update */
1110 #define TX_STATUS_UNEXP(status) \
1111 ((((status) & TX_STATUS_INTERMEDIATE) != 0) && \
1112 TX_STATUS_UNEXP_AMPDU(status))
1113
1114 /* Unexpected tx status for A-MPDU rate update */
1115 #if defined(WLAFTERBURNER) || defined(WLP2P)
1116 #define TX_STATUS_UNEXP_AMPDU(status) \
1117 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
1118 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME) && \
1119 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_NACK_ABS))
1120 #else
1121 #define TX_STATUS_UNEXP_AMPDU(status) \
1122 ((((status) & TX_STATUS_SUPR_MASK) != 0) && \
1123 (((status) & TX_STATUS_SUPR_MASK) != TX_STATUS_SUPR_EXPTIME))
1124 #endif /* WLAFTERBURNER */
1125
1126 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /* ba bitmap 0:3 in 1st pkg */
1127 #define TX_STATUS_BA_BMAP03_SHIFT 12 /* ba bitmap 0:3 in 1st pkg */
1128 #define TX_STATUS_BA_BMAP47_MASK 0x001E /* ba bitmap 4:7 in 2nd pkg */
1129 #define TX_STATUS_BA_BMAP47_SHIFT 3 /* ba bitmap 4:7 in 2nd pkg */
1130
1131
1132 /* RXE (Receive Engine) */
1133
1134 /* RCM_CTL */
1135 #define RCM_INC_MASK_H 0x0080
1136 #define RCM_INC_MASK_L 0x0040
1137 #define RCM_INC_DATA 0x0020
1138 #define RCM_INDEX_MASK 0x001F
1139 #define RCM_SIZE 15
1140
1141 #define RCM_MAC_OFFSET 0 /* current MAC address */
1142 #define RCM_BSSID_OFFSET 3 /* current BSSID address */
1143 #define RCM_F_BSSID_0_OFFSET 6 /* foreign BSS CFP tracking */
1144 #define RCM_F_BSSID_1_OFFSET 9 /* foreign BSS CFP tracking */
1145 #define RCM_F_BSSID_2_OFFSET 12 /* foreign BSS CFP tracking */
1146
1147 #define RCM_WEP_TA0_OFFSET 16
1148 #define RCM_WEP_TA1_OFFSET 19
1149 #define RCM_WEP_TA2_OFFSET 22
1150 #define RCM_WEP_TA3_OFFSET 25
1151
1152 /* PSM Block */
1153
1154 /* psm_phy_hdr_param bits */
1155 #define MAC_PHY_RESET 1
1156 #define MAC_PHY_CLOCK_EN 2
1157 #define MAC_PHY_FORCE_CLK 4
1158
1159 /* WEP Block */
1160
1161 /* WEP_WKEY */
1162 #define WKEY_START (1 << 8)
1163 #define WKEY_SEL_MASK 0x1F
1164
1165 /* WEP data formats */
1166
1167 /* the number of RCMTA entries */
1168 #define RCMTA_SIZE 50
1169
1170 /* max keys in M_TKMICKEYS_BLK */
1171 #define WSEC_MAX_TKMIC_ENGINE_KEYS 12 /* 8 + 4 default */
1172
1173 /* max keys in M_WAPIMICKEYS_BLK */
1174 #define WSEC_MAX_SMS4MIC_ENGINE_REAL_KEYS 12 /* (4 * 2) + 4 default */
1175 #define WSEC_MAX_SMS4MIC_ENGINE_KEYS 8 /* (4 * 2) + 4 default */
1176
1177 /* max RXE match registers */
1178 #define WSEC_MAX_RXE_KEYS 4
1179
1180 /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */
1181 /* SKL (Security Key Lookup) */
1182 #define SKL_ALGO_MASK 0x0007
1183 #define SKL_ALGO_SHIFT 0
1184 #define SKL_KEYID_MASK 0x0008
1185 #define SKL_KEYID_SHIFT 3
1186 #define SKL_INDEX_MASK 0x03F0
1187 #define SKL_INDEX_SHIFT 4
1188 #define SKL_GRP_ALGO_MASK 0x1c00
1189 #define SKL_GRP_ALGO_SHIFT 10
1190
1191 /* additional bits defined for IBSS group key support */
1192 #define SKL_IBSS_INDEX_MASK 0x01F0
1193 #define SKL_IBSS_INDEX_SHIFT 4
1194 #define SKL_IBSS_KEYID1_MASK 0x0600
1195 #define SKL_IBSS_KEYID1_SHIFT 9
1196 #define SKL_IBSS_KEYID2_MASK 0x1800
1197 #define SKL_IBSS_KEYID2_SHIFT 11
1198 #define SKL_IBSS_KEYALGO_MASK 0xE000
1199 #define SKL_IBSS_KEYALGO_SHIFT 13
1200
1201 #define WSEC_MODE_OFF 0
1202 #define WSEC_MODE_HW 1
1203 #define WSEC_MODE_SW 2
1204
1205 #define WSEC_ALGO_OFF 0
1206 #define WSEC_ALGO_WEP1 1
1207 #define WSEC_ALGO_TKIP 2
1208 #define WSEC_ALGO_AES 3
1209 #define WSEC_ALGO_WEP128 4
1210 #define WSEC_ALGO_AES_LEGACY 5
1211 #define WSEC_ALGO_SMS4 6
1212 #define WSEC_ALGO_NALG 7
1213
1214 #define AES_MODE_NONE 0
1215 #define AES_MODE_CCM 1
1216 #define AES_MODE_OCB_MSDU 2
1217 #define AES_MODE_OCB_MPDU 3
1218
1219 /* WEP_CTL (Rev 0) */
1220 #define WECR0_KEYREG_SHIFT 0
1221 #define WECR0_KEYREG_MASK 0x7
1222 #define WECR0_DECRYPT (1 << 3)
1223 #define WECR0_IVINLINE (1 << 4)
1224 #define WECR0_WEPALG_SHIFT 5
1225 #define WECR0_WEPALG_MASK (0x7 << 5)
1226 #define WECR0_WKEYSEL_SHIFT 8
1227 #define WECR0_WKEYSEL_MASK (0x7 << 8)
1228 #define WECR0_WKEYSTART (1 << 11)
1229 #define WECR0_WEPINIT (1 << 14)
1230 #define WECR0_ICVERR (1 << 15)
1231
1232 /* Frame template map byte offsets */
1233 #define T_ACTS_TPL_BASE (0)
1234 #define T_NULL_TPL_BASE (0xc * 2)
1235 #define T_QNULL_TPL_BASE (0x1c * 2)
1236 #define T_RR_TPL_BASE (0x2c * 2)
1237 #define T_BCN0_TPL_BASE (0x34 * 2)
1238 #define T_PRS_TPL_BASE (0x134 * 2)
1239 #define T_BCN1_TPL_BASE (0x234 * 2)
1240
1241
1242 #define T_BA_TPL_BASE T_QNULL_TPL_BASE /* template area for BA */
1243
1244 #define T_RAM_ACCESS_SZ 4 /* template ram is 4 byte access only */
1245
1246 #define TPLBLKS_PER_BCN 2
1247 #if defined(WLLPRS) && defined(MBSS)
1248 #define TPLBLKS_PER_PRS 4
1249 #else
1250 #define TPLBLKS_PER_PRS 2
1251 #endif /* WLLPRS && MBSS */
1252 /* calculate the number of template mem blks needed for beacons
1253 * and probe responses of all the BSSs. add one additional block
1254 * to account for 104 bytes of space reserved (?) at the start of
1255 * template memory.
1256 */
1257 #define MBSS_TPLBLKS(n) (1 + ((n) * (TPLBLKS_PER_BCN + TPLBLKS_PER_PRS)))
1258 #define MBSS_TXFIFO_START_BLK(n) MBSS_TPLBLKS(n)
1259 #define MBSS_PRS_BLKS_START(n) (T_BCN0_TPL_BASE + \
1260 ((n) * TPLBLKS_PER_BCN * TXFIFO_SIZE_UNIT))
1261
1262 /* Shared Mem byte offsets */
1263
1264 /* Location where the ucode expects the corerev */
1265 #define M_MACHW_VER (0x00b * 2)
1266
1267 /* Location where the ucode expects the MAC capabilities */
1268 #define M_MACHW_CAP_L (0x060 * 2)
1269 #define M_MACHW_CAP_H (0x061 * 2)
1270
1271 /* WME shared memory */
1272 #define M_EDCF_STATUS_OFF (0x007 * 2)
1273 #define M_TXF_CUR_INDEX (0x018 * 2)
1274 #define M_EDCF_QINFO (0x120 * 2)
1275
1276 /* PS-mode related parameters */
1277 #define M_DOT11_SLOT (0x008 * 2)
1278 #define M_DOT11_DTIMPERIOD (0x009 * 2)
1279 #define M_NOSLPZNATDTIM (0x026 * 2)
1280
1281 /* Beacon-related parameters */
1282 #define M_BCN0_FRM_BYTESZ (0x00c * 2) /* Bcn 0 template length */
1283 #define M_BCN1_FRM_BYTESZ (0x00d * 2) /* Bcn 1 template length */
1284 #define M_BCN_TXTSF_OFFSET (0x00e * 2)
1285 #define M_TIMBPOS_INBEACON (0x00f * 2)
1286 #define M_SFRMTXCNTFBRTHSD (0x022 * 2)
1287 #define M_LFRMTXCNTFBRTHSD (0x023 * 2)
1288 #define M_BCN_PCTLWD (0x02a * 2)
1289 #define M_BCN_LI (0x05b * 2) /* beacon listen interval */
1290
1291 /* MAX Rx Frame len */
1292 #define M_MAXRXFRM_LEN (0x010 * 2)
1293
1294 /* ACK/CTS related params */
1295 #define M_RSP_PCTLWD (0x011 * 2)
1296
1297 /* Hardware Power Control */
1298 #define M_TXPWR_N (0x012 * 2)
1299 #define M_TXPWR_TARGET (0x013 * 2)
1300 #define M_TXPWR_MAX (0x014 * 2)
1301 #define M_TXPWR_CUR (0x019 * 2)
1302
1303 /* Rx-related parameters */
1304 #define M_RX_PAD_DATA_OFFSET (0x01a * 2)
1305
1306 /* WEP Shared mem data */
1307 #define M_SEC_DEFIVLOC (0x01e * 2)
1308 #define M_SEC_VALNUMSOFTMCHTA (0x01f * 2)
1309 #define M_PHYVER (0x028 * 2)
1310 #define M_PHYTYPE (0x029 * 2)
1311 #define M_SECRXKEYS_PTR (0x02b * 2)
1312 #define M_TKMICKEYS_PTR (0x059 * 2)
1313 #define M_WAPIMICKEYS_PTR (0x051 * 2)
1314 #define M_SECKINDXALGO_BLK (0x2ea * 2)
1315 #define M_SECKINDXALGO_BLK_SZ 54
1316 #define M_SECPSMRXTAMCH_BLK (0x2fa * 2)
1317 #define M_TKIP_TSC_TTAK (0x18c * 2)
1318 #define D11_MAX_KEY_SIZE 16
1319
1320 #define M_MAX_ANTCNT (0x02e * 2) /* antenna swap threshold */
1321
1322 /* Probe response related parameters */
1323 #define M_SSIDLEN (0x024 * 2)
1324 #define M_PRB_RESP_FRM_LEN (0x025 * 2)
1325 #define M_PRS_MAXTIME (0x03a * 2)
1326 #define M_SSID (0xb0 * 2)
1327 #define M_CTXPRS_BLK (0xc0 * 2)
1328 #define C_CTX_PCTLWD_POS (0x4 * 2)
1329
1330
1331 /* Delta between OFDM and CCK power in CCK power boost mode */
1332 #define M_OFDM_OFFSET (0x027 * 2)
1333
1334 /* TSSI for last 4 11b/g CCK packets transmitted */
1335 #define M_B_TSSI_0 (0x02c * 2)
1336 #define M_B_TSSI_1 (0x02d * 2)
1337
1338 /* Host flags to turn on ucode options */
1339 #define M_HOST_FLAGS1 (0x02f * 2)
1340 #define M_HOST_FLAGS2 (0x030 * 2)
1341 #define M_HOST_FLAGS3 (0x031 * 2)
1342 #define M_HOST_FLAGS4 (0x03c * 2)
1343 #define M_HOST_FLAGS5 (0x06a * 2)
1344 #define M_HOST_FLAGS_SZ 16
1345
1346 #define M_RADAR_REG (0x033 * 2)
1347
1348 /* TSSI for last 4 11a OFDM packets transmitted */
1349 #define M_A_TSSI_0 (0x034 * 2)
1350 #define M_A_TSSI_1 (0x035 * 2)
1351
1352 /* noise interference measurement */
1353 #define M_NOISE_IF_COUNT (0x034 * 2)
1354 #define M_NOISE_IF_TIMEOUT (0x035 * 2)
1355
1356
1357 #define M_RF_RX_SP_REG1 (0x036 * 2)
1358
1359 /* TSSI for last 4 11g OFDM packets transmitted */
1360 #define M_G_TSSI_0 (0x038 * 2)
1361 #define M_G_TSSI_1 (0x039 * 2)
1362
1363 /* Background noise measure */
1364 #define M_JSSI_0 (0x44 * 2)
1365 #define M_JSSI_1 (0x45 * 2)
1366 #define M_JSSI_AUX (0x46 * 2)
1367
1368 #define M_CUR_2050_RADIOCODE (0x47 * 2)
1369
1370 /* TX fifo sizes */
1371 #define M_FIFOSIZE0 (0x4c * 2)
1372 #define M_FIFOSIZE1 (0x4d * 2)
1373 #define M_FIFOSIZE2 (0x4e * 2)
1374 #define M_FIFOSIZE3 (0x4f * 2)
1375 #define D11_MAX_TX_FRMS 32 /* max frames allowed in tx fifo */
1376
1377 /* Current channel number plus upper bits */
1378 #define M_CURCHANNEL (0x50 * 2)
1379 #define D11_CURCHANNEL_5G 0x0100;
1380 #define D11_CURCHANNEL_40 0x0200;
1381 #define D11_CURCHANNEL_MAX 0x00FF;
1382
1383 /* last posted frameid on the bcmc fifo */
1384 #define M_BCMC_FID (0x54 * 2)
1385 #define INVALIDFID 0xffff
1386
1387 /* extended beacon phyctl bytes for 11N */
1388 #define M_BCN_PCTL1WD (0x058 * 2)
1389
1390 /* idle busy ratio to duty_cycle requirement */
1391 #define M_TX_IDLE_BUSY_RATIO_X_16_CCK (0x52 * 2)
1392 #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM (0x5A * 2)
1393
1394 /* SHM_reg = 2*(wlc_read_shm(M_SSLPNPHYREGS_PTR) + offset) */
1395 #define M_SSLPNPHYREGS_PTR (71 * 2)
1396
1397 /* CW RSSI for SSLPNPHY */
1398 #define M_SSLPN_RSSI_0 0x1332
1399 #define M_SSLPN_RSSI_1 0x1338
1400 #define M_SSLPN_RSSI_2 0x133e
1401 #define M_SSLPN_RSSI_3 0x1344
1402
1403 /* SNR for SSLPNPHY */
1404 #define M_SSLPN_SNR_A_0 0x1334
1405 #define M_SSLPN_SNR_B_0 0x1336
1406
1407 #define M_SSLPN_SNR_A_1 0x133a
1408 #define M_SSLPN_SNR_B_1 0x133c
1409
1410 #define M_SSLPN_SNR_A_2 0x1340
1411 #define M_SSLPN_SNR_B_2 0x1342
1412
1413 #define M_SSLPN_SNR_A_3 0x1346
1414 #define M_SSLPN_SNR_B_3 0x1348
1415
1416
1417 /* Olympic N9037.4Mhz crystal change */
1418 #define M_SSLPNPHY_REG_55f_REG_VAL 16
1419 #define M_SSLPNPHY_REG_4F2_2_4 17
1420 #define M_SSLPNPHY_REG_4F3_2_4 18
1421 #define M_SSLPNPHY_REG_4F2_16_64 19
1422 #define M_SSLPNPHY_REG_4F3_16_64 20
1423 #define M_SSLPNPHY_REG_4F2_CCK 21
1424 #define M_SSLPNPHY_REG_4F3_CCK 22
1425 #define M_SSLPNPHY_ANTDIV_REG 27
1426
1427 /* Olympic N9037.4Mhz crystal change */
1428 #define M_55f_REG_VAL 16
1429 #define M_SSLPNPHY_REG_4F2_2_4 17
1430 #define M_SSLPNPHY_REG_4F3_2_4 18
1431 #define M_SSLPNPHY_REG_4F2_16_64 19
1432 #define M_SSLPNPHY_REG_4F3_16_64 20
1433 #define M_SSLPNPHY_REG_4F2_CCK 21
1434 #define M_SSLPNPHY_REG_4F3_CCK 22
1435 #define M_SSLPNPHY_ANTDIV_REG 27
1436 #define M_SSLPNPHY_NOISE_SAMPLES 34
1437 #define M_SSLPNPHY_TSSICAL_EN 35
1438 #define M_SSLPNPHY_LNA_TX 36
1439 #define M_SSLPNPHY_TXPWR_BLK 40
1440
1441 /* For noise cal */
1442 #define M_NOISE_CAL_MIN 35
1443 #define M_NOISE_CAL_MAX 36
1444 #define M_NOISE_CAL_METRIC 37
1445 #define M_NOISE_CAL_ACC 38
1446 #define M_NOISE_CAL_CMD 39
1447 #define M_NOISE_CAL_RSP 40
1448
1449 #define M_SSLPN_ACI_TMOUT 0x1308
1450 #define M_SSLPN_ACI_CNT 0x130a
1451
1452 #define M_SSLPN_LAST_RESET (81*2)
1453 #define M_SSLPN_LAST_LOC (63*2)
1454 #define M_SSLPNPHY_RESET_STATUS (4902)
1455 #define M_SSLPNPHY_DSC_TIME (0x98d*2)
1456 #define M_SSLPNPHY_RESET_CNT_DSC (0x98b*2)
1457 #define M_SSLPNPHY_RESET_CNT (0x98c*2)
1458
1459
1460 #define M_LCNPHYREGS_PTR M_SSLPNPHYREGS_PTR
1461
1462 /* CW RSSI and SNR for LCNPHY */
1463 #define M_LCN_RSSI_0 (4 *2)
1464 #define M_LCN_SNR_A_0 (5 *2)
1465 #define M_LCN_SNR_B_0 (6 *2)
1466
1467 #define M_LCN_RSSI_1 (7 *2)
1468 #define M_LCN_SNR_A_1 (8 *2)
1469 #define M_LCN_SNR_B_1 (9 *2)
1470
1471 #define M_LCN_RSSI_2 (10*2)
1472 #define M_LCN_SNR_A_2 (11*2)
1473 #define M_LCN_SNR_B_2 (12*2)
1474
1475 #define M_LCN_RSSI_3 (13*2)
1476 #define M_LCN_SNR_A_3 (14*2)
1477 #define M_LCN_SNR_B_3 (15*2)
1478
1479 #define M_LCN_ACI_TMOUT 0x1308
1480 #define M_LCN_ACI_CNT 0x130a
1481
1482 #define M_LCN_LAST_RESET (81*2)
1483 #define M_LCN_LAST_LOC (63*2)
1484 #define M_LCNPHY_RESET_STATUS (4902)
1485 #define M_LCNPHY_DSC_TIME (0x98d*2)
1486 #define M_LCNPHY_RESET_CNT_DSC (0x98b*2)
1487 #define M_LCNPHY_RESET_CNT (0x98c*2)
1488
1489 /* Rate table offsets */
1490 #define M_RT_DIRMAP_A (0xe0 * 2)
1491 #define M_RT_BBRSMAP_A (0xf0 * 2)
1492 #define M_RT_DIRMAP_B (0x100 * 2)
1493 #define M_RT_BBRSMAP_B (0x110 * 2)
1494 #define D11_RT_DIRMAP_SIZE 16
1495
1496 /* Rate table entry offsets */
1497 #define M_RT_PRS_PLCP_POS 10
1498 #define M_RT_PRS_DUR_POS 16
1499 #define M_RT_OFDM_PCTL1_POS 18
1500 #define M_RT_TXPWROFF_POS 20
1501
1502 #define M_20IN40_IQ (0x380 * 2)
1503
1504 /* SHM locations where ucode stores the current power index */
1505 #define M_CURR_IDX1 (0x384 *2)
1506 #define M_CURR_IDX2 (0x387 *2)
1507
1508 #define M_BSCALE_ANT0 (0x5e * 2)
1509 #define M_BSCALE_ANT1 (0x5f * 2)
1510
1511 /* Antenna Diversity Testing */
1512 #define M_MIMO_ANTSEL_RXDFLT (0x63 * 2)
1513 #define M_ANTSEL_CLKDIV (0x61 * 2)
1514 #define M_MIMO_ANTSEL_TXDFLT (0x64 * 2)
1515
1516 #define M_MIMO_MAXSYM (0x5d * 2)
1517 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */
1518 #define MIMO_MAXSYM_MAX 0xffff /* 64k */
1519
1520 #define M_WATCHDOG_8TU (0x1e * 2)
1521 #define WATCHDOG_8TU_DEF 5
1522 #define WATCHDOG_8TU_MAX 10
1523
1524 /* Manufacturing Test Variables */
1525 #define M_PKTENG_CTRL (0x6c * 2) /* PER test mode */
1526 #define M_PKTENG_IFS (0x6d * 2) /* IFS for TX mode */
1527 #define M_PKTENG_FRMCNT_LO (0x6e * 2) /* Lower word of tx frmcnt/rx lostcnt */
1528 #define M_PKTENG_FRMCNT_HI (0x6f * 2) /* Upper word of tx frmcnt/rx lostcnt */
1529
1530 /* Index variation in vbat ripple */
1531 #define M_SSLPN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1532 #define M_SSLPN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1533 #define M_LCN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1534 #define M_LCN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1535
1536 /* Index variation in vbat ripple */
1537 #define M_SSLPN_PWR_IDX_MAX (0x67 * 2) /* highest index read by ucode */
1538 #define M_SSLPN_PWR_IDX_MIN (0x66 * 2) /* lowest index read by ucode */
1539
1540 /* M_PKTENG_CTRL bit definitions */
1541 #define M_PKTENG_MODE_TX 0x0001
1542 #define M_PKTENG_MODE_TX_RIFS 0x0004
1543 #define M_PKTENG_MODE_TX_CTS 0x0008
1544 #define M_PKTENG_MODE_RX 0x0002
1545 #define M_PKTENG_MODE_RX_WITH_ACK 0x0402
1546 #define M_PKTENG_MODE_MASK 0x0003
1547 #define M_PKTENG_FRMCNT_VLD 0x0100 /* TX frames indicated in the frmcnt reg */
1548
1549 /* Sample Collect parameters (bitmap and type) */
1550 #define M_SMPL_COL_BMP (0x372 * 2) /* Trigger bitmap for sample collect */
1551 #define M_SMPL_COL_CTL (0x373 * 2) /* Sample collect type */
1552
1553 #define ANTSEL_CLKDIV_4MHZ 6
1554 #define MIMO_ANTSEL_BUSY 0x4000 /* bit 14 (busy) */
1555 #define MIMO_ANTSEL_SEL 0x8000 /* bit 15 write the value */
1556 #define MIMO_ANTSEL_WAIT 50 /* 50us wait */
1557 #define MIMO_ANTSEL_OVERRIDE 0x8000 /* flag */
1558
1559 #define M_AFEOVR_PTR (0x2c*2)
1560 /* address of stored default ifs_ctl1 value */
1561 #define M_IFSCTL1 (0x2d*2)
1562
1563 typedef struct shm_acparams shm_acparams_t;
1564 BWL_PRE_PACKED_STRUCT struct shm_acparams {
1565 uint16 txop;
1566 uint16 cwmin;
1567 uint16 cwmax;
1568 uint16 cwcur;
1569 uint16 aifs;
1570 uint16 bslots;
1571 uint16 reggap;
1572 uint16 status;
1573 uint16 rsvd[8];
1574 } BWL_POST_PACKED_STRUCT;
1575 #define M_EDCF_QLEN (16 * 2)
1576
1577 #define WME_STATUS_NEWAC (1 << 8)
1578
1579 /* M_HOST_FLAGS */
1580 #define MHFMAX 5 /* Number of valid hostflag half-word (uint16) */
1581 #define MHF1 0 /* Hostflag 1 index */
1582 #define MHF2 1 /* Hostflag 2 index */
1583 #define MHF3 2 /* Hostflag 3 index */
1584 #define MHF4 3 /* Hostflag 4 index */
1585 #define MHF5 4 /* Hostflag 5 index */
1586
1587 /* Flags in M_HOST_FLAGS */
1588 #define MHF1_ANTDIV 0x0001 /* Enable ucode antenna diversity help */
1589 #define MHF1_WLAN_CRITICAL 0x0002 /* WLAN is in critical state */
1590 #define MHF1_MBSS_EN 0x0004 /* Enable MBSS: RXPUWAR deprecated for rev >= 9 */
1591 #define MHF1_CCKPWR 0x0008 /* Enable 4 Db CCK power boost */
1592 #define MHF1_4331EPA_MUX 0x0008 /* WAR pin mux, shared with CCK power boost */
1593 #define MHF1_BTCOEXIST 0x0010 /* Enable Bluetooth / WLAN coexistence */
1594 #define MHF1_DCFILTWAR 0x0020 /* Enable g-mode DC canceler filter bw WAR */
1595 #define MHF1_PACTL 0x0040 /* Enable PA gain boost for OFDM frames */
1596 #define MHF1_ACPRWAR 0x0080 /* Enable ACPR. Disable for Japan, channel 14 */
1597 #define MHF1_EDCF 0x0100 /* Enable EDCF access control */
1598 #define MHF1_IQSWAP_WAR 0x0200
1599 #define MHF1_FORCEFASTCLK 0x0400 /* Disable Slow clock request, for corerev < 11 */
1600 #define MHF1_ACIWAR 0x0800 /* Enable ACI war: shiftbits by 2 on PHY_CRS */
1601 #define MHF1_A2060WAR 0x1000 /* PR15874WAR */
1602 #define MHF1_RADARWAR 0x2000
1603 #define MHF1_DEFKEYVALID 0x4000 /* Enable use of the default keys */
1604 #define MHF1_AFTERBURNER 0x8000 /* Enable afterburner */
1605
1606 /* Flags in M_HOST_FLAGS2 */
1607 #define MHF2_MBSSIDMODE 0x0001 /* MBSSID mode */
1608 #define MHF2_4317FWAKEWAR 0x0002 /* PR19311WAR: 4317PCMCIA, fast wakeup ucode */
1609 #define MHF2_SYNTHPUWAR 0x0004
1610 #define MHF2_PCISLOWCLKWAR 0x0008 /* PR16165WAR : Enable ucode PCI slow clock WAR */
1611 #define MHF2_SKIP_ADJTSF 0x0010 /* skip TSF update when receiving bcn/probeRsp */
1612 #define MHF2_4317PIORXWAR 0x0020 /* PR38778WAR : PIO receiving */
1613 #define MHF2_TXBCMC_NOW 0x0040 /* Flush BCMC FIFO immediately */
1614 #define MHF2_PPR_HWPWRCTL 0x0080 /* For corerev24+, ppr; for GPHY, Hwpwrctrl */
1615 #define MHF2_BTC2WIRE_ALTGPIO 0x0100 /* BTC 2wire in alternate pins */
1616 #define MHF2_BTCPREMPT 0x0200 /* BTC enable bluetooth check during tx */
1617 #define MHF2_SKIP_CFP_UPDATE 0x0400 /* Skip CFP update */
1618 #define MHF2_NPHY40MHZ_WAR 0x0800
1619 #define MHF2_TMP_HTRSP 0x1000 /* Temp hack to use HT response frames in ucode */
1620 #define MHF2_PAPD_FLT_DIS 0x2000 /* LPPHY adjust tx filter */
1621 #define MHF2_BTCANTMODE 0x4000 /* BTC ant mode ?? */
1622 #define MHF2_NITRO_MODE 0x8000 /* Enable Nitro mode */
1623
1624 /* Flags in M_HOST_FLAGS3 */
1625 #define MHF3_ANTSEL_EN 0x0001 /* enabled mimo antenna selection */
1626 #define MHF3_ANTSEL_MODE 0x0002 /* antenna selection mode: 0: 2x3, 1: 2x4 */
1627 #define MHF3_BTCX_DEF_BT 0x0004 /* corerev >= 13 BT Coex. */
1628 #define MHF3_BTCX_ACTIVE_PROT 0x0008 /* corerev >= 13 BT Coex. */
1629 #define MHF3_NPHY_MLADV_WAR 0x0010
1630 #define MHF3_KNOISE 0x0020 /* Use this to enable/disable knoise. */
1631 #define MHF3_UCAMPDU_RETX 0x0040 /* ucode handles AMPDU retransmission */
1632 #define MHF3_BTCX_DELL_WAR 0x0080
1633 #define MHF3_BTCX_SIM_RSP 0x0100 /* allow limited lwo power tx when BT is active */
1634 #define MHF3_BTCX_PS_PROTECT 0x0200 /* use PS mode to protect BT activity */
1635 #define MHF3_BTCX_SIM_TX_LP 0x0400 /* use low power for simultaneous tx responses */
1636 #define MHF3_PR45960_WAR 0x0800
1637 #define MHF3_BTCX_ECI 0x1000 /* Enable BTCX ECI interface */
1638 #define MHF3_BTCX_EXTRA_PRI 0x2000 /* Extra priority for 4th wire */
1639 #define MHF3_PAPD_OFF_CCK 0x4000 /* Disable PAPD comp for CCK frames */
1640 #define MHF3_PAPD_OFF_OFDM 0x8000 /* Disable PAPD comp for OFDM frames */
1641
1642 /* Flags in M_HOST_FLAGS4 */
1643 #define MHF4_CISCOTKIP_WAR 0x0001 /* Change WME timings under certain conditions */
1644 #define MHF4_RCMTA_BSSID_EN 0x0002 /* BTAMP: multiSta BSSIDs matching in RCMTA area */
1645 #define MHF4_BCN_ROT_RR 0x0004 /* MBSSID: beacon roarate in round-robin fashion */
1646 #define MHF4_OPT_SLEEP 0x0008 /* enable opportunistic sleep */
1647 #define MHF4_PROXY_STA 0x0010 /* enable proxy-STA feature */
1648 #define MHF4_AGING 0x0020 /* Enable aging threshold for RF awareness */
1649 #define MHF4_BPHY_2TXCORES 0x0040 /* bphy Tx on both cores (negative logic) */
1650 #define MHF4_BPHY_TXCORE0 0x0080 /* force bphy Tx on core 0 (board level WAR) */
1651 #define MHF4_BTAMP_TXLOWPWR 0x0100 /* BTAMP, low tx-power mode */
1652 #define MHF4_WMAC_ACKTMOUT 0x0200 /* reserved for WMAC testing */
1653 #define MHF4_IBSS_SEC 0x0800 /* IBSS WPA2-PSK operating mode */
1654 #define MHF4_EXTPA_ENABLE 0x4000 /* for 4313A0 FEM boards */
1655
1656 /* Flags in M_HOST_FLAGS5 */
1657 #define MHF5_4313_BTCX_GPIOCTRL 0x0001 /* Enable gpio for bt/wlan sel for 4313 */
1658 #define MHF5_BTCX_LIGHT 0x0002 /* light coex mode, turn off txpu only for critical BT */
1659 #define MHF5_BTCX_PARALLEL 0x0004 /* BT and WLAN run in parallel. */
1660 #define MHF5_BTCX_DEFANT 0x0008 /* default position for shared antenna */
1661 #define MHF5_P2P_MODE 0x0010 /* Enable P2P mode */
1662 #define MHF5_LEGACY_PRS 0x0020 /* Enable legacy probe resp support */
1663 #define MHF5_BTCX_AUX_SHARED 0x0040 /* BT uses AUX antenna */
1664 #define MHF5_HTPHY_RSSI_PWRDN 0x0080 /* Disable RSSI_PWRDN feature */
1665 #define MHF5_TONEJAMMER_WAR 0x0100 /* Enable Tone Jammer war */
1666 #define MHF5_TXBA_BURST 0x0400 /* Throughput boost for Intel */
1667 #define MHF5_DMAHANG_WAR 0x0800 /* Enable DMA Hang war */
1668
1669 /* Radio power setting for ucode */
1670 #define M_RADIO_PWR (0x32 * 2)
1671
1672 /* phy noise recorded by ucode right after tx */
1673 #define M_PHY_NOISE (0x037 * 2)
1674 #define PHY_NOISE_MASK 0x00ff
1675
1676 /* Receive Frame Data Header for 802.11b DCF-only frames */
1677 typedef struct d11rxhdr d11rxhdr_t;
1678 BWL_PRE_PACKED_STRUCT struct d11rxhdr {
1679 uint16 RxFrameSize; /* Actual byte length of the frame data received */
1680 uint16 PAD;
1681 uint16 PhyRxStatus_0; /* PhyRxStatus 15:0 */
1682 uint16 PhyRxStatus_1; /* PhyRxStatus 31:16 */
1683 uint16 PhyRxStatus_2; /* PhyRxStatus 47:32 */
1684 uint16 PhyRxStatus_3; /* PhyRxStatus 63:48 */
1685 uint16 PhyRxStatus_4; /* PhyRxStatus 79:64 */
1686 uint16 PhyRxStatus_5; /* PhyRxStatus 95:80 */
1687 uint16 RxStatus1; /* MAC Rx Status */
1688 uint16 RxStatus2; /* extended MAC Rx status */
1689 uint16 RxTSFTime; /* RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */
1690 uint16 RxChan; /* gain code, channel radio code, and phy type */
1691 } BWL_POST_PACKED_STRUCT;
1692
1693 #define RXHDR_LEN 24 /* sizeof d11rxhdr_t */
1694 #define FRAMELEN(h) ((h)->RxFrameSize)
1695
1696 typedef struct wlc_d11rxhdr wlc_d11rxhdr_t;
1697 BWL_PRE_PACKED_STRUCT struct wlc_d11rxhdr {
1698 d11rxhdr_t rxhdr;
1699 uint32 tsf_l; /* TSF_L reading */
1700 int8 rssi; /* computed instanteneous rssi in BMAC */
1701 int8 rxpwr0; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1702 int8 rxpwr1; /* obsoleted, place holder for legacy ROM code. use rxpwr[] */
1703 int8 do_rssi_ma; /* do per-pkt sampling for per-antenna ma in HIGH */
1704 int8 rxpwr[WL_RSSI_ANT_MAX]; /* rssi for supported antennas */
1705 } BWL_POST_PACKED_STRUCT;
1706
1707 #define WRXHDR_LEN 36 /* sizeof wlc_d11rxhdr_t */
1708
1709
1710 /* PhyRxStatus_0: */
1711 #define PRXS0_FT_MASK 0x0003 /* NPHY only: CCK, OFDM, preN, N */
1712 #define PRXS0_CLIP_MASK 0x000C /* NPHY only: clip count adjustment steps by AGC */
1713 #define PRXS0_CLIP_SHIFT 2
1714 #define PRXS0_UNSRATE 0x0010 /* PHY received a frame with unsupported rate */
1715 #define PRXS0_RXANT_UPSUBBAND 0x0020 /* GPHY: rx ant, NPHY: upper sideband */
1716 #define PRXS0_LCRS 0x0040 /* CCK frame only: lost crs during cck frame reception */
1717 #define PRXS0_SHORTH 0x0080 /* Short Preamble */
1718 #define PRXS0_PLCPFV 0x0100 /* PLCP violation */
1719 #define PRXS0_PLCPHCF 0x0200 /* PLCP header integrity check failed */
1720 #define PRXS0_GAIN_CTL 0x4000 /* legacy PHY gain control */
1721 #define PRXS0_ANTSEL_MASK 0xF000 /* NPHY: Antennas used for received frame, bitmask */
1722 #define PRXS0_ANTSEL_SHIFT 0x12
1723
1724 /* subfield PRXS0_FT_MASK */
1725 #define PRXS0_CCK 0x0000
1726 #define PRXS0_OFDM 0x0001 /* valid only for G phy, use rxh->RxChan for A phy */
1727 #define PRXS0_PREN 0x0002
1728 #define PRXS0_STDN 0x0003
1729
1730 /* subfield PRXS0_ANTSEL_MASK */
1731 #define PRXS0_ANTSEL_0 0x0 /* antenna 0 is used */
1732 #define PRXS0_ANTSEL_1 0x2 /* antenna 1 is used */
1733 #define PRXS0_ANTSEL_2 0x4 /* antenna 2 is used */
1734 #define PRXS0_ANTSEL_3 0x8 /* antenna 3 is used */
1735
1736 /* PhyRxStatus_1: */
1737 #define PRXS1_JSSI_MASK 0x00FF
1738 #define PRXS1_JSSI_SHIFT 0
1739 #define PRXS1_SQ_MASK 0xFF00
1740 #define PRXS1_SQ_SHIFT 8
1741
1742 /* nphy PhyRxStatus_1: */
1743 #define PRXS1_nphy_PWR0_MASK 0x00FF
1744 #define PRXS1_nphy_PWR1_MASK 0xFF00
1745
1746 /* PhyRxStatus_2: */
1747 #define PRXS2_LNAGN_MASK 0xC000
1748 #define PRXS2_LNAGN_SHIFT 14
1749 #define PRXS2_PGAGN_MASK 0x3C00
1750 #define PRXS2_PGAGN_SHIFT 10
1751 #define PRXS2_FOFF_MASK 0x03FF
1752
1753 /* nphy PhyRxStatus_2: */
1754 #define PRXS2_nphy_SQ_ANT0 0x000F /* nphy overall signal quality for antenna 0 */
1755 #define PRXS2_nphy_SQ_ANT1 0x00F0 /* nphy overall signal quality for antenna 0 */
1756 #define PRXS2_nphy_cck_SQ 0x00FF /* bphy signal quality(when FT field is 0) */
1757 #define PRXS3_nphy_SSQ_MASK 0xFF00 /* spatial conditioning of the two receive channels */
1758 #define PRXS3_nphy_SSQ_SHIFT 8
1759
1760 /* PhyRxStatus_3: */
1761 #define PRXS3_DIGGN_MASK 0x1800
1762 #define PRXS3_DIGGN_SHIFT 11
1763 #define PRXS3_TRSTATE 0x0400
1764
1765 /* nphy PhyRxStatus_3: */
1766 #define PRXS3_nphy_MMPLCPLen_MASK 0x0FFF /* Mixed-mode preamble PLCP length */
1767 #define PRXS3_nphy_MMPLCP_RATE_MASK 0xF000 /* Mixed-mode preamble rate field */
1768 #define PRXS3_nphy_MMPLCP_RATE_SHIFT 12
1769
1770 #define NPHY_MMPLCPLen(rxs) ((rxs)->PhyRxStatus_3 & PRXS3_nphy_MMPLCPLen_MASK)
1771
1772 /* HTPHY Rx Status defines */
1773 /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */
1774 #define PRXS0_BAND 0x0400 /* 0 = 2.4G, 1 = 5G */
1775 #define PRXS0_RSVD 0x0800 /* reserved; set to 0 */
1776 #define PRXS0_UNUSED 0xF000 /* unused and not defined; set to 0 */
1777
1778 /* htphy PhyRxStatus_1: */
1779 #define PRXS1_HTPHY_CORE_MASK 0x000F /* core enables for {3..0}, 0=disabled, 1=enabled */
1780 #define PRXS1_HTPHY_ANTCFG_MASK 0x00F0 /* antenna configation */
1781 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /* Mixmode PLCP Length low byte mask */
1782
1783 /* htphy PhyRxStatus_2: */
1784 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /* Mixmode PLCP Length high byte maskw */
1785 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /* Mixmode PLCP rate mask */
1786 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /* Rx power on core 0 */
1787
1788 /* htphy PhyRxStatus_3: */
1789 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /* Rx power on core 1 */
1790 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /* Rx power on core 2 */
1791
1792 /* htphy PhyRxStatus_4: */
1793 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /* Rx power on core 3 */
1794 #define PRXS4_HTPHY_CFO 0xFF00 /* Coarse frequency offset */
1795
1796 /* htphy PhyRxStatus_5: */
1797 #define PRXS5_HTPHY_FFO 0x00FF /* Fine frequency offset */
1798 #define PRXS5_HTPHY_AR 0xFF00 /* Advance Retard */
1799
1800 #define HTPHY_MMPLCPLen(rxs) ((((rxs)->PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \
1801 (((rxs)->PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8))
1802 /* Get Rx power on core 0 */
1803 #define HTPHY_RXPWR_ANT0(rxs) ((((rxs)->PhyRxStatus_2) & PRXS2_HTPHY_RXPWR_ANT0) >> 8)
1804 /* Get Rx power on core 1 */
1805 #define HTPHY_RXPWR_ANT1(rxs) (((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT1)
1806 /* Get Rx power on core 2 */
1807 #define HTPHY_RXPWR_ANT2(rxs) ((((rxs)->PhyRxStatus_3) & PRXS3_HTPHY_RXPWR_ANT2) >> 8)
1808
1809 /* ucode RxStatus1: */
1810 #define RXS_BCNSENT 0x8000
1811 #define RXS_SECKINDX_MASK 0x07e0
1812 #define RXS_SECKINDX_SHIFT 5
1813 #define RXS_DECERR (1 << 4)
1814 #define RXS_DECATMPT (1 << 3)
1815 #define RXS_PBPRES (1 << 2) /* PAD bytes to make IP data 4 bytes aligned */
1816 #define RXS_RESPFRAMETX (1 << 1)
1817 #define RXS_FCSERR (1 << 0)
1818
1819 /* ucode RxStatus2: */
1820 #define RXS_AMSDU_MASK 1
1821 #define RXS_AGGTYPE_MASK 0x6
1822 #define RXS_AGGTYPE_SHIFT 1
1823 #define RXS_AMSDU_FIRST 1
1824 #define RXS_AMSDU_INTERMEDIATE 0
1825 #define RXS_AMSDU_LAST 2
1826 #define RXS_AMSDU_N_ONE 3
1827 #define RXS_TKMICATMPT (1 << 3)
1828 #define RXS_TKMICERR (1 << 4)
1829 #define RXS_PHYRXST_VALID (1 << 8)
1830 #define RXS_RXANT_MASK 0x3
1831 #define RXS_RXANT_SHIFT 12
1832
1833
1834
1835 /* RxChan */
1836 #define RXS_CHAN_40 0x1000
1837 #define RXS_CHAN_5G 0x0800
1838 #define RXS_CHAN_ID_MASK 0x07f8
1839 #define RXS_CHAN_ID_SHIFT 3
1840 #define RXS_CHAN_PHYTYPE_MASK 0x0007
1841 #define RXS_CHAN_PHYTYPE_SHIFT 0
1842
1843 /* Index of attenuations used during ucode power control. */
1844 #define M_PWRIND_BLKS (0x184 * 2)
1845 #define M_PWRIND_MAP0 (M_PWRIND_BLKS + 0x0)
1846 #define M_PWRIND_MAP1 (M_PWRIND_BLKS + 0x2)
1847 #define M_PWRIND_MAP2 (M_PWRIND_BLKS + 0x4)
1848 #define M_PWRIND_MAP3 (M_PWRIND_BLKS + 0x6)
1849 #define M_PWRIND_MAP4 (M_PWRIND_BLKS + 0x8)
1850 #define M_PWRIND_MAP5 (M_PWRIND_BLKS + 0xa)
1851 /* M_PWRIND_MAP(core) macro */
1852 #define M_PWRIND_MAP(core) (M_PWRIND_BLKS + ((core)<<1))
1853
1854 /* CCA Statistics */
1855 #define M_CCA_STATS_BLK (0x360 * 2)
1856 #define M_CCA_TXDUR_L (M_CCA_STATS_BLK + 0x0)
1857 #define M_CCA_TXDUR_H (M_CCA_STATS_BLK + 0x2)
1858 #define M_CCA_INBSS_L (M_CCA_STATS_BLK + 0x4)
1859 #define M_CCA_INBSS_H (M_CCA_STATS_BLK + 0x6)
1860 #define M_CCA_OBSS_L (M_CCA_STATS_BLK + 0x8)
1861 #define M_CCA_OBSS_H (M_CCA_STATS_BLK + 0xa)
1862 #define M_CCA_NOCTG_L (M_CCA_STATS_BLK + 0xc)
1863 #define M_CCA_NOCTG_H (M_CCA_STATS_BLK + 0xe)
1864 #define M_CCA_NOPKT_L (M_CCA_STATS_BLK + 0x10)
1865 #define M_CCA_NOPKT_H (M_CCA_STATS_BLK + 0x12)
1866 #define M_MAC_DOZE_L (M_CCA_STATS_BLK + 0x14)
1867 #define M_MAC_DOZE_H (M_CCA_STATS_BLK + 0x16)
1868
1869 #define M_CCA_FLAGS (0x9b7 * 2)
1870
1871 /* PSM SHM variable offsets */
1872 #define M_PSM_SOFT_REGS 0x0
1873 #define M_BOM_REV_MAJOR (M_PSM_SOFT_REGS + 0x0)
1874 #define M_BOM_REV_MINOR (M_PSM_SOFT_REGS + 0x2)
1875 #define M_UCODE_DATE (M_PSM_SOFT_REGS + 0x4) /* 4:4:8 year:month:day format */
1876 #define M_UCODE_TIME (M_PSM_SOFT_REGS + 0x6) /* 5:6:5 hour:min:sec format */
1877 #define M_UCODE_DBGST (M_PSM_SOFT_REGS + 0x40) /* ucode debug status code */
1878 #define M_UCODE_MACSTAT (M_PSM_SOFT_REGS + 0xE0) /* macstat counters */
1879
1880 #define M_AGING_THRSH (0x3e * 2) /* max time waiting for medium before tx */
1881 #define M_MBURST_SIZE (0x40 * 2) /* max frames in a frameburst */
1882 #define M_MBURST_TXOP (0x41 * 2) /* max frameburst TXOP in unit of us */
1883 #define M_SYNTHPU_DLY (0x4a * 2) /* pre-wakeup for synthpu, default: 500 */
1884 #define M_PRETBTT (0x4b * 2)
1885
1886 #define M_BTCX_MAX_INDEX 89
1887 #define M_BTCX_BLK_PTR (M_PSM_SOFT_REGS + (0x49 * 2))
1888 #define M_BTCX_PRED_PER (4 * 2)
1889 #define M_BTCX_LAST_SCO (12 * 2)
1890 #define M_BTCX_LAST_SCO_H (13 * 2)
1891 #define M_BTCX_NEXT_SCO (14 * 2)
1892 #define M_BTCX_LAST_DATA (23 * 2)
1893 #define M_BTCX_A2DP_BUFFER (30 * 2)
1894 #define M_BTCX_LAST_A2DP (38 * 2)
1895 #define M_BTCX_A2DP_BUFFER_LOWMARK (40 * 2)
1896 #define M_BTCX_PRED_PER_COUNT (72 * 2)
1897 #define M_BTCX_PROT_RSSI_THRESH (73 * 2)
1898 #define M_BTCX_AMPDUTX_RSSI_THRESH (74 * 2)
1899 #define M_BTCX_AMPDURX_RSSI_THRESH (75 * 2)
1900 #define M_BTCX_DIVERSITY_SAVE (89 * 2)
1901
1902 #define M_ALT_TXPWR_IDX (M_PSM_SOFT_REGS + (0x3b * 2)) /* offset to the target txpwr */
1903 #define M_PHY_TX_FLT_PTR (M_PSM_SOFT_REGS + (0x3d * 2))
1904 #define M_CTS_DURATION (M_PSM_SOFT_REGS + (0x5c * 2))
1905 #define M_SSLPN_OLYMPIC (M_PSM_SOFT_REGS + (0x68 * 2))
1906 #define M_LP_RCCAL_OVR (M_PSM_SOFT_REGS + (0x6b * 2))
1907
1908 #ifdef WLP2P
1909 /* WiFi P2P SHM location */
1910 #define M_P2P_BLK_PTR (M_PSM_SOFT_REGS + (0x57 * 2))
1911
1912 /* The number of scheduling blocks */
1913 #define M_P2P_BSS_MAX 4
1914
1915 /* WiFi P2P interrupt block positions */
1916 #define M_P2P_I_BLK_SZ 4
1917 #define M_P2P_I_BLK(b) ((0x0 * 2) + (M_P2P_I_BLK_SZ * (b) * 2))
1918 #define M_P2P_I(b, i) (M_P2P_I_BLK(b) + ((i) * 2))
1919
1920 #define M_P2P_I_PRE_TBTT 0 /* pretbtt */
1921 #define M_P2P_I_CTW_END 1 /* CTWindow ends */
1922 #define M_P2P_I_ABS 2 /* absence period starts */
1923 #define M_P2P_I_PRS 3 /* presence period starts */
1924
1925 /* P2P hps flags */
1926 #define M_P2P_HPS ((0x10 * 2))
1927 #define M_P2P_HPS_CTW(b) (1 << (b))
1928 #define M_P2P_HPS_NOA(b) (1 << ((b) + M_P2P_BSS_MAX))
1929
1930 /* WiFi P2P address attribute block */
1931 #define M_ADDR_BMP_BLK_SZ 12
1932 #define M_ADDR_BMP_BLK(b) ((0x11 * 2) + ((b) * 2))
1933
1934 #define ADDR_BMP_RA (1 << 0) /* Receiver Address (RA) */
1935 #define ADDR_BMP_TA (1 << 1) /* Transmitter Address (TA) */
1936 #define ADDR_BMP_BSSID (1 << 2) /* BSSID */
1937 #define ADDR_BMP_AP (1 << 3) /* Infra-BSS Access Point (AP) */
1938 #define ADDR_BMP_STA (1 << 4) /* Infra-BSS Station (STA) */
1939 #define ADDR_BMP_P2P_DISC (1 << 5) /* P2P Device */
1940 #define ADDR_BMP_P2P_GO (1 << 6) /* P2P Group Owner */
1941 #define ADDR_BMP_P2P_GC (1 << 7) /* P2P Client */
1942 #define ADDR_BMP_BSS_IDX_MASK (3 << 8) /* BSS control block index */
1943 #define ADDR_BMP_BSS_IDX_SHIFT 8
1944
1945 /* WiFi P2P address starts from this entry in RCMTA */
1946 #define P2P_ADDR_STRT_INDX (RCMTA_SIZE - M_ADDR_BMP_BLK_SZ)
1947
1948 /* WiFi P2P per BSS control block positions.
1949 * all time related fields are in units of 32us unless noted otherwise.
1950 */
1951 #define M_P2P_BSS_BLK_SZ 11
1952 #define M_P2P_BSS_BLK(b) ((0x1d * 2) + (M_P2P_BSS_BLK_SZ * (b) * 2))
1953 #define M_P2P_BSS(b, p) (M_P2P_BSS_BLK(b) + (p) * 2)
1954 #define M_P2P_BSS_BCN_INT(b) (M_P2P_BSS_BLK(b) + (0 * 2)) /* beacon interval */
1955 #define M_P2P_BSS_DTIM_CNT(b) (M_P2P_BSS_BLK(b) + (1 * 2)) /* DTIM interval? */
1956 #define M_P2P_BSS_ST(b) (M_P2P_BSS_BLK(b) + (2 * 2)) /* current state */
1957 #define M_P2P_BSS_PRE_TBTT(b) (M_P2P_BSS_BLK(b) + (3 * 2)) /* pretbtt time */
1958 #define M_P2P_BSS_CTW(b) (M_P2P_BSS_BLK(b) + (4 * 2)) /* CTWindow duration */
1959 #define M_P2P_BSS_N_CTW_END(b) (M_P2P_BSS_BLK(b) + (5 * 2)) /* next CTWindow end */
1960 #define M_P2P_BSS_NOA_CNT(b) (M_P2P_BSS_BLK(b) + (6 * 2)) /* NoA count */
1961 #define M_P2P_BSS_N_NOA(b) (M_P2P_BSS_BLK(b) + (7 * 2)) /* next absence time */
1962 #define M_P2P_BSS_NOA_DUR(b) (M_P2P_BSS_BLK(b) + (8 * 2)) /* absence period */
1963 #define M_P2P_BSS_NOA_TD(b) (M_P2P_BSS_BLK(b) + (9 * 2)) /* presence period (int - dur) */
1964 #define M_P2P_BSS_NOA_OFS(b) (M_P2P_BSS_BLK(b) + (10 * 2)) /* last 5 bits of interval */
1965
1966 /* M_P2P_BSS_ST word positions. */
1967 #define M_P2P_BSS_ST_CTW (1 << 0) /* BSS is in CTWindow */
1968 #define M_P2P_BSS_ST_SUPR (1 << 1) /* BSS is suppressing frames */
1969 #define M_P2P_BSS_ST_ABS (1 << 2) /* BSS is in absence period */
1970 #define M_P2P_BSS_ST_WAKE (1 << 3)
1971 #define M_P2P_BSS_ST_AP (1 << 4) /* BSS is Infra-BSS AP */
1972 #define M_P2P_BSS_ST_STA (1 << 5) /* BSS is Infra-BSS STA */
1973 #define M_P2P_BSS_ST_GO (1 << 6) /* BSS is P2P Group Owner */
1974 #define M_P2P_BSS_ST_GC (1 << 7) /* BSS is P2P Client */
1975
1976 /* WiFi P2P TSF block positions */
1977 #define M_P2P_TSF_BLK_SZ 4
1978 #define M_P2P_TSF_BLK(b) ((0x49 * 2) + (M_P2P_TSF_BLK_SZ * (b) * 2))
1979 #define M_P2P_TSF(b, w) (M_P2P_TSF_BLK(b) + (w) * 2)
1980
1981 /* GO operating channel */
1982 #define M_P2P_GO_CHANNEL ((0x59 * 2))
1983 #endif /* WLP2P */
1984
1985 #ifdef WLP2P
1986 /* Reserve bottom of RCMTA for P2P Addresses */
1987 #define WSEC_MAX_RCMTA_KEYS (54 - M_ADDR_BMP_BLK_SZ)
1988 #else
1989 #define WSEC_MAX_RCMTA_KEYS 54
1990 #endif
1991
1992 /* PKTENG Rx Stats Block */
1993 #define M_RXSTATS_BLK_PTR (M_PSM_SOFT_REGS + (0x65 * 2))
1994
1995 /* LUT for Phy/Radio Registers for Idle TSSI measurement */
1996 #define M_TSSI_MSMT_BLK_PTR (M_PSM_SOFT_REGS + (53 * 2))
1997 #define M_LCNPHY_TSSICAL_EN (0 * 2)
1998 #define M_PHY_REG_LUT_CNT (1 * 2)
1999 #define M_RADIO_REG_LUT_CNT (2 * 2)
2000 #define M_LUT_PHY_REG_RESTORE_BLK (3 * 2) /* 26 locations, 13 regs */
2001 #define M_LUT_PHY_REG_SETUP_BLK (29 * 2) /* 26 locations, 13 regs */
2002 #define M_LUT_RADIO_REG_RESTORE_BLK (55 * 2) /* 30 locations, 15 regs */
2003 #define M_LUT_RADIO_REG_SETUP_BLK (85 * 2) /* 30 locations, 15 regs */
2004 #define M_LCNPHY_TSSICAL_DELAY (115 * 2)
2005 #define M_LCNPHY_TSSICAL_TIME (116 * 2)
2006
2007 /* Txcore Mask related parameters 5 locations (BPHY, OFDM, 1-streams ~ 3-Streams */
2008 #define M_COREMASK_BLK 0x374
2009 #define M_COREMASK_BPHY ((M_COREMASK_BLK + 0) * 2)
2010 #define M_COREMASK_OFDM ((M_COREMASK_BLK + 1) * 2)
2011 #define M_COREMASK_MCS ((M_COREMASK_BLK + 2) * 2)
2012 #define TXCOREMASK 0x0F
2013 #define SPATIAL_SHIFT 8
2014 #define MAX_COREMASK_BLK 5
2015
2016
2017
2018 /* ucode debug status codes */
2019 #define DBGST_INACTIVE 0 /* not valid really */
2020 #define DBGST_INIT 1 /* after zeroing SHM, before suspending at init */
2021 #define DBGST_ACTIVE 2 /* "normal" state */
2022 #define DBGST_SUSPENDED 3 /* suspended */
2023 #define DBGST_ASLEEP 4 /* asleep (PS mode) */
2024
2025 /* Scratch Reg defs */
2026 typedef enum
2027 {
2028 S_RSV0 = 0,
2029 S_RSV1,
2030 S_RSV2,
2031
2032 /* scratch registers for Dot11-contants */
2033 S_DOT11_CWMIN, /* CW-minimum 0x03 */
2034 S_DOT11_CWMAX, /* CW-maximum 0x04 */
2035 S_DOT11_CWCUR, /* CW-current 0x05 */
2036 S_DOT11_SRC_LMT, /* short retry count limit 0x06 */
2037 S_DOT11_LRC_LMT, /* long retry count limit 0x07 */
2038 S_DOT11_DTIMCOUNT, /* DTIM-count 0x08 */
2039
2040 /* Tx-side scratch registers */
2041 S_SEQ_NUM, /* hardware sequence number reg 0x09 */
2042 S_SEQ_NUM_FRAG, /* seq-num for frags (Set at the start os MSDU 0x0A */
2043 S_FRMRETX_CNT, /* frame retx count 0x0B */
2044 S_SSRC, /* Station short retry count 0x0C */
2045 S_SLRC, /* Station long retry count 0x0D */
2046 S_EXP_RSP, /* Expected response frame 0x0E */
2047 S_OLD_BREM, /* Remaining backoff ctr 0x0F */
2048 S_OLD_CWWIN, /* saved-off CW-cur 0x10 */
2049 S_TXECTL, /* TXE-Ctl word constructed in scr-pad 0x11 */
2050 S_CTXTST, /* frm type-subtype as read from Tx-descr 0x12 */
2051
2052 /* Rx-side scratch registers */
2053 S_RXTST, /* Type and subtype in Rxframe 0x13 */
2054
2055 /* Global state register */
2056 S_STREG, /* state storage actual bit maps below 0x14 */
2057
2058 S_TXPWR_SUM, /* Tx power control: accumulator 0x15 */
2059 S_TXPWR_ITER, /* Tx power control: iteration 0x16 */
2060 S_RX_FRMTYPE, /* Rate and PHY type for frames 0x17 */
2061 S_THIS_AGG, /* Size of this AGG (A-MSDU) 0x18 */
2062
2063 S_KEYINDX, /* 0x19 */
2064 S_RXFRMLEN, /* Receive MPDU length in bytes 0x1A */
2065
2066 /* Receive TSF time stored in SCR */
2067 S_RXTSFTMRVAL_WD3, /* TSF value at the start of rx 0x1B */
2068 S_RXTSFTMRVAL_WD2, /* TSF value at the start of rx 0x1C */
2069 S_RXTSFTMRVAL_WD1, /* TSF value at the start of rx 0x1D */
2070 S_RXTSFTMRVAL_WD0, /* TSF value at the start of rx 0x1E */
2071 S_RXSSN, /* Received start seq number for A-MPDU BA 0x1F */
2072 S_RXQOSFLD, /* Rx-QoS field (if present) 0x20 */
2073
2074 /* Scratch pad regs used in microcode as temp storage */
2075 S_TMP0, /* stmp0 0x21 */
2076 S_TMP1, /* stmp1 0x22 */
2077 S_TMP2, /* stmp2 0x23 */
2078 S_TMP3, /* stmp3 0x24 */
2079 S_TMP4, /* stmp4 0x25 */
2080 S_TMP5, /* stmp5 0x26 */
2081 S_PRQPENALTY_CTR, /* Probe response queue penalty counter 0x27 */
2082 S_ANTCNT, /* unsuccessful attempts on current ant. 0x28 */
2083 S_SYMBOL, /* flag for possible symbol ctl frames 0x29 */
2084 S_RXTP, /* rx frame type 0x2A */
2085 S_STREG2, /* extra state storage 0x2B */
2086 S_STREG3, /* even more extra state storage 0x2C */
2087 S_STREG4, /* ... 0x2D */
2088 S_STREG5, /* remember to initialize it to zero 0x2E */
2089
2090 S_NITRO_TXT, /* NITRO: time of MP_ACK or Rsp frm trans 0x2F */
2091 S_NITRO_RXAID, /* NITRO: received child AID (at Parent) 0x30 */
2092
2093 S_ADJPWR_IDX,
2094 S_CUR_PTR, /* Temp pointer for A-MPDU re-Tx SHM table 0x32 */
2095 S_REVID4, /* 0x33 */
2096 S_INDX, /* 0x34 */
2097 S_ADDR0, /* 0x35 */
2098 S_ADDR1, /* 0x36 */
2099 S_ADDR2, /* 0x37 */
2100 S_ADDR3, /* 0x38 */
2101 S_ADDR4, /* 0x39 */
2102 S_ADDR5, /* 0x3A */
2103 S_TMP6, /* 0x3B */
2104 S_KEYINDX_BU, /* Backup for Key index 0x3C */
2105 S_MFGTEST_TMP0, /* Temp register used for RX test calculations 0x3D */
2106 S_RXESN, /* Received end sequence number for A-MPDU BA 0x3E */
2107 S_STREG6, /* 0x3F */
2108 } ePsmScratchPadRegDefinitions;
2109
2110 #define S_BEACON_INDX S_OLD_BREM
2111 #define S_PRS_INDX S_OLD_CWWIN
2112 #define S_BTCX_BT_DUR S_REVID4
2113 #define S_PHYTYPE S_SSRC
2114 #define S_PHYVER S_SLRC
2115
2116 /* IHR offsets */
2117 #define TSF_TMR_TSF_L 0x119
2118 #define TSF_TMR_TSF_ML 0x11A
2119 #define TSF_TMR_TSF_MU 0x11B
2120 #define TSF_TMR_TSF_H 0x11C
2121
2122 #define TSF_GPT_0_STAT 0x123
2123 #define TSF_GPT_1_STAT 0x124
2124 #define TSF_GPT_0_CTR_L 0x125
2125 #define TSF_GPT_1_CTR_L 0x126
2126 #define TSF_GPT_0_CTR_H 0x127
2127 #define TSF_GPT_1_CTR_H 0x128
2128 #define TSF_GPT_0_VAL_L 0x129
2129 #define TSF_GPT_1_VAL_L 0x12A
2130 #define TSF_GPT_0_VAL_H 0x12B
2131 #define TSF_GPT_1_VAL_H 0x12C
2132
2133 /* GPT_2 is corerev >= 3 */
2134 #define TSF_GPT_2_STAT 0x133
2135 #define TSF_GPT_2_CTR_L 0x134
2136 #define TSF_GPT_2_CTR_H 0x135
2137 #define TSF_GPT_2_VAL_L 0x136
2138 #define TSF_GPT_2_VAL_H 0x137
2139
2140 /* Slow timer registers */
2141 #define SLOW_CTRL 0x150
2142 #define SLOW_TIMER_L 0x151
2143 #define SLOW_TIMER_H 0x152
2144 #define SLOW_FRAC 0x153
2145 #define FAST_PWRUP_DLY 0x154
2146
2147 /* IHR TSF_GPT STAT values */
2148 #define TSF_GPT_PERIODIC (1 << 12)
2149 #define TSF_GPT_ADJTSF (1 << 13)
2150 #define TSF_GPT_USETSF (1 << 14)
2151 #define TSF_GPT_ENABLE (1 << 15)
2152
2153 /* IHR SLOW_CTRL values */
2154 #define SLOW_CTRL_PDE (1 << 0)
2155 #define SLOW_CTRL_FD (1 << 8)
2156
2157
2158 /* ucode mac statistic counters in shared memory */
2159 typedef struct macstat {
2160 uint16 txallfrm; /* 0x80 */
2161 uint16 txrtsfrm; /* 0x82 */
2162 uint16 txctsfrm; /* 0x84 */
2163 uint16 txackfrm; /* 0x86 */
2164 uint16 txdnlfrm; /* 0x88 */
2165 uint16 txbcnfrm; /* 0x8a */
2166 uint16 txfunfl[8]; /* 0x8c - 0x9b */
2167 uint16 txtplunfl; /* 0x9c */
2168 uint16 txphyerr; /* 0x9e */
2169 uint16 pktengrxducast; /* 0xa0 */
2170 uint16 pktengrxdmcast; /* 0xa2 */
2171 uint16 rxfrmtoolong; /* 0xa4 */
2172 uint16 rxfrmtooshrt; /* 0xa6 */
2173 uint16 rxinvmachdr; /* 0xa8 */
2174 uint16 rxbadfcs; /* 0xaa */
2175 uint16 rxbadplcp; /* 0xac */
2176 uint16 rxcrsglitch; /* 0xae */
2177 uint16 rxstrt; /* 0xb0 */
2178 uint16 rxdfrmucastmbss; /* 0xb2 */
2179 uint16 rxmfrmucastmbss; /* 0xb4 */
2180 uint16 rxcfrmucast; /* 0xb6 */
2181 uint16 rxrtsucast; /* 0xb8 */
2182 uint16 rxctsucast; /* 0xba */
2183 uint16 rxackucast; /* 0xbc */
2184 uint16 rxdfrmocast; /* 0xbe */
2185 uint16 rxmfrmocast; /* 0xc0 */
2186 uint16 rxcfrmocast; /* 0xc2 */
2187 uint16 rxrtsocast; /* 0xc4 */
2188 uint16 rxctsocast; /* 0xc6 */
2189 uint16 rxdfrmmcast; /* 0xc8 */
2190 uint16 rxmfrmmcast; /* 0xca */
2191 uint16 rxcfrmmcast; /* 0xcc */
2192 uint16 rxbeaconmbss; /* 0xce */
2193 uint16 rxdfrmucastobss; /* 0xd0 */
2194 uint16 rxbeaconobss; /* 0xd2 */
2195 uint16 rxrsptmout; /* 0xd4 */
2196 uint16 bcntxcancl; /* 0xd6 */
2197 uint16 PAD;
2198 uint16 rxf0ovfl; /* 0xda */
2199 uint16 rxf1ovfl; /* 0xdc */
2200 uint16 rxf2ovfl; /* 0xde */
2201 uint16 txsfovfl; /* 0xe0 */
2202 uint16 pmqovfl; /* 0xe2 */
2203 uint16 rxcgprqfrm; /* 0xe4 */
2204 uint16 rxcgprsqovfl; /* 0xe6 */
2205 uint16 txcgprsfail; /* 0xe8 */
2206 uint16 txcgprssuc; /* 0xea */
2207 uint16 prs_timeout; /* 0xec */
2208 uint16 rxnack;
2209 uint16 frmscons;
2210 uint16 txnack;
2211 uint16 txglitch_nack;
2212 uint16 txburst; /* 0xf6 # tx bursts */
2213 uint16 bphy_rxcrsglitch; /* bphy rx crs glitch */
2214 uint16 phywatchdog; /* 0xfa # of phy watchdog events */
2215 uint16 PAD;
2216 uint16 bphy_badplcp; /* bphy bad plcp */
2217 } macstat_t;
2218
2219 /* dot11 core-specific control flags */
2220 #define SICF_PCLKE 0x0004 /* PHY clock enable */
2221 #define SICF_PRST 0x0008 /* PHY reset */
2222 #define SICF_MPCLKE 0x0010 /* MAC PHY clockcontrol enable */
2223 #define SICF_FREF 0x0020 /* PLL FreqRefSelect (corerev >= 5) */
2224 /* NOTE: the following bw bits only apply when the core is attached
2225 * to a NPHY (and corerev >= 11 which it will always be for NPHYs).
2226 */
2227 #define SICF_BWMASK 0x00c0 /* phy clock mask (b6 & b7) */
2228 #define SICF_BW40 0x0080 /* 40MHz BW (160MHz phyclk) */
2229 #define SICF_BW20 0x0040 /* 20MHz BW (80MHz phyclk) */
2230 #define SICF_BW10 0x0000 /* 10MHz BW (40MHz phyclk) */
2231 #define SICF_GMODE 0x2000 /* gmode enable */
2232
2233 /* dot11 core-specific status flags */
2234 #define SISF_2G_PHY 0x0001 /* 2.4G capable phy (corerev >= 5) */
2235 #define SISF_5G_PHY 0x0002 /* 5G capable phy (corerev >= 5) */
2236 #define SISF_FCLKA 0x0004 /* FastClkAvailable (corerev >= 5) */
2237 #define SISF_DB_PHY 0x0008 /* Dualband phy (corerev >= 11) */
2238
2239
2240 /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */
2241
2242 #define BPHY_REG_OFT_BASE 0x0
2243 /* offsets for indirect access to bphy registers */
2244 #define BPHY_BB_CONFIG 0x01
2245 #define BPHY_ADCBIAS 0x02
2246 #define BPHY_ANACORE 0x03
2247 #define BPHY_PHYCRSTH 0x06
2248 #define BPHY_TEST 0x0a
2249 #define BPHY_PA_TX_TO 0x10
2250 #define BPHY_SYNTH_DC_TO 0x11
2251 #define BPHY_PA_TX_TIME_UP 0x12
2252 #define BPHY_RX_FLTR_TIME_UP 0x13
2253 #define BPHY_TX_POWER_OVERRIDE 0x14
2254 #define BPHY_RF_OVERRIDE 0x15
2255 #define BPHY_RF_TR_LOOKUP1 0x16
2256 #define BPHY_RF_TR_LOOKUP2 0x17
2257 #define BPHY_COEFFS 0x18
2258 #define BPHY_PLL_OUT 0x19
2259 #define BPHY_REFRESH_MAIN 0x1a
2260 #define BPHY_REFRESH_TO0 0x1b
2261 #define BPHY_REFRESH_TO1 0x1c
2262 #define BPHY_RSSI_TRESH 0x20
2263 #define BPHY_IQ_TRESH_HH 0x21
2264 #define BPHY_IQ_TRESH_H 0x22
2265 #define BPHY_IQ_TRESH_L 0x23
2266 #define BPHY_IQ_TRESH_LL 0x24
2267 #define BPHY_GAIN 0x25
2268 #define BPHY_LNA_GAIN_RANGE 0x26
2269 #define BPHY_JSSI 0x27
2270 #define BPHY_TSSI_CTL 0x28
2271 #define BPHY_TSSI 0x29
2272 #define BPHY_TR_LOSS_CTL 0x2a
2273 #define BPHY_LO_LEAKAGE 0x2b
2274 #define BPHY_LO_RSSI_ACC 0x2c
2275 #define BPHY_LO_IQMAG_ACC 0x2d
2276 #define BPHY_TX_DC_OFF1 0x2e
2277 #define BPHY_TX_DC_OFF2 0x2f
2278 #define BPHY_PEAK_CNT_THRESH 0x30
2279 #define BPHY_FREQ_OFFSET 0x31
2280 #define BPHY_DIVERSITY_CTL 0x32
2281 #define BPHY_PEAK_ENERGY_LO 0x33
2282 #define BPHY_PEAK_ENERGY_HI 0x34
2283 #define BPHY_SYNC_CTL 0x35
2284 #define BPHY_TX_PWR_CTRL 0x36
2285 #define BPHY_TX_EST_PWR 0x37
2286 #define BPHY_STEP 0x38
2287 #define BPHY_WARMUP 0x39
2288 #define BPHY_LMS_CFF_READ 0x3a
2289 #define BPHY_LMS_COEFF_I 0x3b
2290 #define BPHY_LMS_COEFF_Q 0x3c
2291 #define BPHY_SIG_POW 0x3d
2292 #define BPHY_RFDC_CANCEL_CTL 0x3e
2293 #define BPHY_HDR_TYPE 0x40
2294 #define BPHY_SFD_TO 0x41
2295 #define BPHY_SFD_CTL 0x42
2296 #define BPHY_DEBUG 0x43
2297 #define BPHY_RX_DELAY_COMP 0x44
2298 #define BPHY_CRS_DROP_TO 0x45
2299 #define BPHY_SHORT_SFD_NZEROS 0x46
2300 #define BPHY_DSSS_COEFF1 0x48
2301 #define BPHY_DSSS_COEFF2 0x49
2302 #define BPHY_CCK_COEFF1 0x4a
2303 #define BPHY_CCK_COEFF2 0x4b
2304 #define BPHY_TR_CORR 0x4c
2305 #define BPHY_ANGLE_SCALE 0x4d
2306 #define BPHY_TX_PWR_BASE_IDX 0x4e
2307 #define BPHY_OPTIONAL_MODES2 0x4f
2308 #define BPHY_CCK_LMS_STEP 0x50
2309 #define BPHY_BYPASS 0x51
2310 #define BPHY_CCK_DELAY_LONG 0x52
2311 #define BPHY_CCK_DELAY_SHORT 0x53
2312 #define BPHY_PPROC_CHAN_DELAY 0x54
2313 #define BPHY_DDFS_ENABLE 0x58
2314 #define BPHY_PHASE_SCALE 0x59
2315 #define BPHY_FREQ_CONTROL 0x5a
2316 #define BPHY_LNA_GAIN_RANGE_10 0x5b
2317 #define BPHY_LNA_GAIN_RANGE_32 0x5c
2318 #define BPHY_OPTIONAL_MODES 0x5d
2319 #define BPHY_RX_STATUS2 0x5e
2320 #define BPHY_RX_STATUS3 0x5f
2321 #define BPHY_DAC_CONTROL 0x60
2322 #define BPHY_ANA11G_FILT_CTRL 0x62
2323 #define BPHY_REFRESH_CTRL 0x64
2324 #define BPHY_RF_OVERRIDE2 0x65
2325 #define BPHY_SPUR_CANCEL_CTRL 0x66
2326 #define BPHY_FINE_DIGIGAIN_CTRL 0x67
2327 #define BPHY_RSSI_LUT 0x88
2328 #define BPHY_RSSI_LUT_END 0xa7
2329 #define BPHY_TSSI_LUT 0xa8
2330 #define BPHY_TSSI_LUT_END 0xc7
2331 #define BPHY_TSSI2PWR_LUT 0x380
2332 #define BPHY_TSSI2PWR_LUT_END 0x39f
2333 #define BPHY_LOCOMP_LUT 0x3a0
2334 #define BPHY_LOCOMP_LUT_END 0x3bf
2335 #define BPHY_TXGAIN_LUT 0x3c0
2336 #define BPHY_TXGAIN_LUT_END 0x3ff
2337
2338 /* Bits in BB_CONFIG: */
2339 #define PHY_BBC_ANT_MASK 0x0180
2340 #define PHY_BBC_ANT_SHIFT 7
2341 #define BB_DARWIN 0x1000
2342 #define BBCFG_RESETCCA 0x4000
2343 #define BBCFG_RESETRX 0x8000
2344
2345 /* Bits in phytest(0x0a): */
2346 #define TST_DDFS 0x2000
2347 #define TST_TXFILT1 0x0800
2348 #define TST_UNSCRAM 0x0400
2349 #define TST_CARR_SUPP 0x0200
2350 #define TST_DC_COMP_LOOP 0x0100
2351 #define TST_LOOPBACK 0x0080
2352 #define TST_TXFILT0 0x0040
2353 #define TST_TXTEST_ENABLE 0x0020
2354 #define TST_TXTEST_RATE 0x0018
2355 #define TST_TXTEST_PHASE 0x0007
2356
2357 /* phytest txTestRate values */
2358 #define TST_TXTEST_RATE_1MBPS 0
2359 #define TST_TXTEST_RATE_2MBPS 1
2360 #define TST_TXTEST_RATE_5_5MBPS 2
2361 #define TST_TXTEST_RATE_11MBPS 3
2362 #define TST_TXTEST_RATE_SHIFT 3
2363
2364 /*
2365 * MBSS shared memory address definitions; see MultiBSSUcode Twiki page
2366 * Local terminology:
2367 * addr is byte offset used by SW.
2368 * offset is word offset used by uCode.
2369 */
2370
2371 #define SHM_MBSS_BASE_ADDR (0x320 * 2)
2372 #define SHM_MBSS_WORD_OFFSET_TO_ADDR(n) (SHM_MBSS_BASE_ADDR + ((n) * 2))
2373
2374 #define SHM_MBSS_BSSID0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0)
2375 #define SHM_MBSS_BSSID1 SHM_MBSS_WORD_OFFSET_TO_ADDR(1)
2376 #define SHM_MBSS_BSSID2 SHM_MBSS_WORD_OFFSET_TO_ADDR(2)
2377 #define SHM_MBSS_BCN_COUNT SHM_MBSS_WORD_OFFSET_TO_ADDR(3)
2378 #define SHM_MBSS_PRQ_BASE SHM_MBSS_WORD_OFFSET_TO_ADDR(4)
2379 #define SHM_MBSS_BC_FID0 SHM_MBSS_WORD_OFFSET_TO_ADDR(5)
2380 #define SHM_MBSS_BC_FID1 SHM_MBSS_WORD_OFFSET_TO_ADDR(6)
2381 #define SHM_MBSS_BC_FID2 SHM_MBSS_WORD_OFFSET_TO_ADDR(7)
2382 #define SHM_MBSS_BC_FID3 SHM_MBSS_WORD_OFFSET_TO_ADDR(8)
2383 #define SHM_MBSS_PRE_TBTT SHM_MBSS_WORD_OFFSET_TO_ADDR(9)
2384
2385 /* SSID lengths are encoded, two at a time in 16-bits */
2386 #define SHM_MBSS_SSID_LEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(10)
2387 #define SHM_MBSS_SSID_LEN1 SHM_MBSS_WORD_OFFSET_TO_ADDR(11)
2388
2389 /* New for ucode template based mbss */
2390 #define SHM_MBSS_BSSID_NUM SHM_MBSS_WORD_OFFSET_TO_ADDR(12)
2391 #define SHM_MBSS_BC_BITMAP SHM_MBSS_WORD_OFFSET_TO_ADDR(13)
2392 #define SHM_MBSS_PRS_TPLPTR SHM_MBSS_WORD_OFFSET_TO_ADDR(14)
2393 #define SHM_MBSS_TIMPOS_INBCN SHM_MBSS_WORD_OFFSET_TO_ADDR(15)
2394
2395 /* Re-uses M_SSID */
2396 #define SHM_MBSS_BCNLEN0 M_SSID
2397 /* Re-uses part of extended SSID storage */
2398 #define SHM_MBSS_PRSLEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x10)
2399 #define SHM_MBSS_BCFID0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x20)
2400 #define SHM_MBSS_SSIDLEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x30)
2401 #define SHM_MBSS_LPRSLEN0 SHM_MBSS_WORD_OFFSET_TO_ADDR(0x38)
2402 #define SHM_MBSS_CLOSED_NET (0x80) /* indicates closed network */
2403
2404 /* set value for 16 mbss */
2405 #define SHM_MBSS_PRS_TPL0 (2 * 0x1034)
2406 #define SHM_MBSS_LPRS_TPL0 (2 * 0x2034)
2407
2408 /* SSID Search Engine entries */
2409 #define SHM_MBSS_SSIDSE_BASE_ADDR (0)
2410 #define SHM_MBSS_SSIDSE_BLKSZ (36)
2411 #define SHM_MBSS_SSIDLEN_BLKSZ (4)
2412 #define SHM_MBSS_SSID_BLKSZ (32)
2413
2414
2415 /* END New for ucode template based mbss */
2416
2417
2418 /* Uses uCode (HW) BSS config IDX */
2419 #define SHM_MBSS_SSID_ADDR(idx) \
2420 (((idx) == 0) ? M_SSID : SHM_MBSS_WORD_OFFSET_TO_ADDR(0x10 * (idx)))
2421
2422 /* Uses uCode (HW) BSS config IDX */
2423 #define SHM_MBSS_BC_FID_ADDR(ucidx) SHM_MBSS_WORD_OFFSET_TO_ADDR(5 + (ucidx))
2424 #define SHM_MBSS_BC_FID_ADDR16(ucidx) (SHM_MBSS_BCFID0 + (2 * ucidx))
2425
2426 /*
2427 * Definitions for PRQ fifo data as per MultiBSSUcode Twiki page
2428 */
2429
2430 #define SHM_MBSS_PRQ_ENTRY_BYTES 10 /* Size of each PRQ entry */
2431 #define SHM_MBSS_PRQ_ENTRY_COUNT 12 /* Number of PRQ entries */
2432 #define SHM_MBSS_PRQ_TOT_BYTES (SHM_MBSS_PRQ_ENTRY_BYTES * SHM_MBSS_PRQ_ENTRY_COUNT)
2433
2434 #define SHM_MBSS_PRQ_READ_PTR (0x5E * 2)
2435 #define SHM_MBSS_PRQ_WRITE_PTR (0x5F * 2)
2436
2437 typedef struct shm_mbss_prq_entry_s shm_mbss_prq_entry_t;
2438 BWL_PRE_PACKED_STRUCT struct shm_mbss_prq_entry_s {
2439 struct ether_addr ta;
2440 uint8 prq_info[2];
2441 uint16 time_stamp; /* 7:0 timestamp, 8 HT STA Indication, 15:9 Reserved */
2442 } BWL_POST_PACKED_STRUCT;
2443
2444 typedef enum shm_mbss_prq_ft_e {
2445 SHM_MBSS_PRQ_FT_CCK,
2446 SHM_MBSS_PRQ_FT_OFDM,
2447 SHM_MBSS_PRQ_FT_MIMO,
2448 SHM_MBSS_PRQ_FT_RESERVED
2449 } shm_mbss_prq_ft_t;
2450
2451 #define SHM_MBSS_PRQ_FT_COUNT SHM_MBSS_PRQ_FT_RESERVED
2452 #define SHM_MBSS_PRQ_ENT_FRAMETYPE(entry) ((entry)->prq_info[0] & 0x3)
2453 #define SHM_MBSS_PRQ_ENT_UPBAND(entry) ((((entry)->prq_info[0] >> 2) & 0x1) != 0)
2454
2455 /* What was the index matched? */
2456 #define SHM_MBSS_PRQ_ENT_UC_BSS_IDX(entry) (((entry)->prq_info[0] >> 2) & 0x3)
2457 #define SHM_MBSS_PRQ_ENT_PLCP0(entry) ((entry)->prq_info[1])
2458
2459 /* Was this directed to a specific SSID or BSSID? If bit clear, quantity known */
2460 #define SHM_MBSS_PRQ_ENT_DIR_SSID(entry) \
2461 ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 1)
2462 #define SHM_MBSS_PRQ_ENT_DIR_BSSID(entry) \
2463 ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 2)
2464
2465 /* Was the probe request from a ht STA or a legacy STA */
2466 #define SHM_MBSS_PRQ_ENT_HTSTA(entry) ((ltoh16((entry)->time_stamp) >> 8) & 0x1)
2467 #define SHM_MBSS_PRQ_ENT_TIMESTAMP(entry) (ltoh16((entry)->time_stamp) & 0xFF)
2468
2469 /* This marks the end of a packed structure section. */
2470 #include <packed_section_end.h>
2471
2472 #define SHM_BYT_CNT 0x2 /* IHR location */
2473 #define MAX_BYT_CNT 0x600 /* Maximum frame len */
2474
2475
2476 #define M_HOST_WOWLBM (0x06a * 2) /* Events to be set by driver */
2477 #define M_WAKEEVENT_IND (0x06b * 2) /* Event indication by ucode */
2478 #define M_WOWL_NOBCN (0x06c * 2) /* loss of bcn value */
2479
2480 #define M_TXPSP_CNT (0x7b * 2)
2481 #define M_PHYERR (0x7f * 2)
2482
2483 #define WOWL_PSP_TPL_BASE (0x334 * 2)
2484 #define WOWL_GTK_MSG2 (0x434 * 2)
2485 #define WOWL_TX_FIFO_TXRAM_BASE (0x628 * 2)
2486
2487
2488 /* Event definitions */
2489 #define WOWL_MAGIC (1 << 0) /* Wakeup on Magic packet */
2490 #define WOWL_NET (1 << 1) /* Wakeup on Netpattern */
2491 #define WOWL_DIS (1 << 2) /* Wakeup on loss-of-link due to Disassoc/Deauth */
2492 #define WOWL_RETR (1 << 3) /* Wakeup on retrograde TSF */
2493 #define WOWL_BCN (1 << 4) /* Wakeup on loss of beacon */
2494 #define WOWL_TST (1 << 5) /* Wakeup on test mode */
2495 #define WOWL_WPA2 (1 << 13) /* Is it WPA2 ? */
2496 #define WOWL_KEYROT (1 << 14) /* Whether broadcast key rotation should be enabled */
2497
2498 #define MAXBCNLOSS (1 << 13) - 1 /* max 12-bit value for bcn loss */
2499
2500 /* Shared memory for magic pattern */
2501 #define M_RXFRM_SRA0 (0x172 * 2) /* word 0 of the station's shifted MAC address */
2502 #define M_RXFRM_SRA1 (0x173 * 2) /* word 1 of the station's shifted MAC address */
2503 #define M_RXFRM_SRA2 (0x174 * 2) /* word 2 of the station's shifted MAC address */
2504 #define M_RXFRM_RA0 (0x175 * 2) /* word 0 of the station's MAC address */
2505 #define M_RXFRM_RA1 (0x176 * 2) /* word 1 of the station's MAC address */
2506 #define M_RXFRM_RA2 (0x177 * 2) /* word 2 of the station's MAC address */
2507
2508 /* Shared memory for net-pattern */
2509 #define M_NETPAT_NUM (0x0f9 * 2) /* #of netpatterns */
2510 #define M_NETPAT_BLK0 (0x178 * 2) /* pattern 1 */
2511
2512 /* UCODE shm view:
2513 * typedef struct {
2514 * uint16 offset; // byte offset
2515 * uint16 patternsize; // the length of value[.] in bytes
2516 * uchar bitmask[MAXPATTERNSIZE/8]; // 16 bytes, the effect length is (patternsize+7)/8
2517 * uchar value[MAXPATTERNSIZE]; // 128 bytes, the effect length is patternsize.
2518 * } netpattern_t;
2519 */
2520 #define NETPATTERNSIZE (148) /* 128 value + 16 mask + 4 offset + 4 patternsize */
2521 #define MAXPATTERNSIZE 128
2522 #define MAXMASKSIZE MAXPATTERNSIZE/8
2523
2524 /* Power-save related */
2525 #define M_AID_NBIT (0x068 * 2) /* The station's AID bit position in AP's TIM bitmap */
2526 #define M_PSP_PCTLWD (0x02a * 2) /* PHYCTL word for the PS-Poll frame */
2527 #define M_PSP_PCT1LWD (0x058 * 2) /* PHYCTL_1 word for the PS-Poll frame */
2528
2529 /* Security Algorithm defines */
2530 #define TSCPN_BLK_SIZE 6 * 4 /* 6 bytes * 4 ACs */
2531 #define M_WOWL_SECKINDXALGO_BLK (0x0f4 * 2) /* Key index mapping */
2532 #define M_WOWL_TKIP_TSC_TTAK (0x0fa * 2) /* TTAK & MSB(32, TSC/PN) */
2533 #define M_WOWL_TSCPN_BLK (0x11e * 2) /* 0-5 per AC */
2534 #define M_WOWL_SECRXKEYS_PTR (0x02b * 2)
2535 #define M_WOWL_TKMICKEYS_PTR (0x059 * 2)
2536
2537 #define M_WOWL_SECSUITE (0x069 * 2) /* Security being used */
2538
2539 /* test mode -- wakeup the system after 'x' seconds */
2540 #define M_WOWL_TEST_CYCLE (0x06d * 2) /* Time to wakeup in seconds */
2541
2542 #define M_WOWL_WAKEUP_FRM (0x468 *2) /* Frame that woke us up */
2543
2544 /* Broadcast Key rotation related */
2545 #define M_GROUP_KEY_IDX (0x0af * 2) /* Last rotated key index */
2546 #define M_KEYRC_LAST (0x2a0 * 2) /* Last good key replay counter */
2547 #define M_KCK (0x15a * 2) /* KCK */
2548 #define M_KEK (0x16a * 2) /* KEK for WEP/TKIP */
2549 #define M_AESTABLES_PTR (0x06e * 2) /* Pointer to AES tables (see below) */
2550 #define M_CTX_GTKMSG2 (0x2a4 * 2) /* Tx descriptor for GTK MSG2 (see below) */
2551
2552 #define EXPANDED_KEY_RNDS 10
2553 #define EXPANDED_KEY_LEN 176 /* the expanded key from KEK (4*11*4, 16-byte state, 11 rounds) */
2554
2555 /* Txcore Mask related parameters 5 locations (BPHY, OFDM, 1-streams ~ 3-Streams) for WOWL
2556 * The base address is different than normal ucode(offset is the same)
2557 * Refer to above M_COREMASK_BLK definition
2558 */
2559 #define M_COREMASK_BLK_WOWL 0x3fa
2560 #define M_COREMASK_BPHY_WOWL ((M_COREMASK_BLK_WOWL + 0) * 2)
2561 #define M_COREMASK_OFDM_WOWL ((M_COREMASK_BLK_WOWL + 1) * 2)
2562 #define M_COREMASK_MCS_WOWL ((M_COREMASK_BLK_WOWL + 2) * 2)
2563
2564 /* Organization of Template RAM is as follows
2565 * typedef struct {
2566 * uint8 AES_XTIME9DBE[1024];
2567 * uint8 AES_INVSBOX[256];
2568 * uint8 AES_KEYW[176];
2569 * } AES_TABLES_t;
2570 */
2571 /* See dot11_firmware/diag/wmac_tcl/wmac_762_wowl_gtk_aes: proc write_aes_tables,
2572 * for an example of writing those tables into the tx fifo buffer.
2573 */
2574
2575 typedef struct {
2576 uint16 MacTxControlLow; /* mac-tx-ctl-low word */
2577 uint16 MacTxControlHigh; /* mac-tx-ctl-high word */
2578 uint16 PhyTxControlWord; /* phy control word */
2579 uint16 PhyTxControlWord_1; /* extra phy control word for mimophy */
2580 uint16 XtraFrameTypes; /* frame type for RTS/FRAG fallback (used only for AES) */
2581 uint8 RTSPLCPFallback[6]; /* RTSPLCPFALLBACK */
2582
2583 /* For detailed definition of the above field,
2584 * please see the general description of the tx descriptor
2585 * at http://hwnbu-twiki.broadcom.com/bin/view/Mwgroup/TxDescriptor.
2586 */
2587
2588 uint16 mac_frmtype; /* MAC frame type for GTK MSG2, can be
2589 * dot11_data frame (0x20) or dot11_QoS_Data frame (0x22).
2590 */
2591 uint16 frm_bytesize; /* number of bytes in the template, it includes:
2592 * PLCP, MAC header, IV/EIV, the data payload
2593 * (eth-hdr and EAPOL-Key), TKIP MIC
2594 */
2595 uint16 payload_wordoffset; /* the word offset of the data payload */
2596
2597 uint16 seqnum; /* Sequence number for this frame */
2598 uint8 seciv[18]; /* 10-byte TTAK used for TKIP, 8-byte IV/EIV.
2599 * See <SecurityInitVector> in the general tx descriptor.
2600 */
2601 } ctx_gtkmsg2_t;
2602
2603 #define CTX_GTKMSG2_LEN 42 /* For making sure that no PADs are needed */
2604
2605 /* constant tables required for AES key unwraping for key rotation */
2606 extern uint16 aes_invsbox[128];
2607 extern uint16 aes_xtime9dbe[512];
2608
2609 /* Common to ucode/hw agg : WLAMPDU_MAC not defined yet here */
2610 #if defined(WLAMPDU_UCODE) || defined(WLAMPDU_HW)
2611 #define M_TXMPDU_CNT (0x74 * 2) /* # of total MPDUs in AMPDUs tx'd */
2612 #define M_TXAMPDU_CNT (0x7d * 2) /* # of total AMPDUs tx'd */
2613 #define M_RXBA_CNT (0xaa * 2) /* # of rx'ed block acks */
2614 #endif /* defined(WLAMPDU_UCODE) || defined(WLAMPDU_HW) */
2615
2616 #ifdef WLAMPDU_UCODE
2617 /* ucode assisted AMPDU aggregation */
2618 /* ucode allocates a big block starting with 4 side channels, followed by 4 descriptor blocks */
2619 #define M_TXFS_PTR (M_PSM_SOFT_REGS + (0x69 * 2)) /* pointer to txfs block */
2620 #define TOT_TXFS_WSIZE 50 /* totally 50 entries */
2621 #define C_TXFSD_WOFFSET TOT_TXFS_WSIZE /* offset of M_TXFS_INTF_BLK in M_TXFS_BLK */
2622
2623 #define C_TXFSD_SIZE 10 /* Each descriptor is 10 bytes */
2624 #define C_TXFSD_STRT_POS(base, q) (base + (q * C_TXFSD_SIZE) + 0) /* start */
2625 #define C_TXFSD_END_POS(base, q) (base + (q * C_TXFSD_SIZE) + 2) /* end */
2626 #define C_TXFSD_WPTR_POS(base, q) (base + (q * C_TXFSD_SIZE) + 4) /* driver updates */
2627 #define C_TXFSD_RPTR_POS(base, q) (base + (q * C_TXFSD_SIZE) + 6) /* ucode updates */
2628 #define C_TXFSD_RNUM_POS(base, q) (base + (q * C_TXFSD_SIZE) + 8) /* For ucode debugging */
2629
2630 #define MPDU_LEN_SHIFT 0
2631 #define MPDU_LEN_MASK (0xfff << MPDU_LEN_SHIFT) /* Bits 0 - 11 */
2632 #define MPDU_EPOCH_SHIFT 14
2633 #define MPDU_EPOCH_MASK (0x1 << MPDU_EPOCH_SHIFT) /* Bit 14 */
2634 #define MPDU_DEBUG_SHIFT 15
2635 #define MPDU_DEBUG_MASK (0x1 << MPDU_DEBUG_SHIFT) /* Bit 15 */
2636 #endif /* WLAMPDU_UCODE */
2637
2638 #ifdef WLAMPDU_HW
2639 #define AGGFIFO_CAP 64
2640 #define MPDU_LEN_SHIFT 0
2641 #define MPDU_LEN_MASK (0xfff << MPDU_LEN_SHIFT) /* Bits 0 - 11 */
2642 #define MPDU_EPOCH_HW_SHIFT 12
2643 #define MPDU_EPOCH_HW_MASK (0x1 << MPDU_EPOCH_HW_SHIFT) /* Bit 12 */
2644 #define MPDU_RSVD_SHIFT 13
2645 #define MPDU_RSVD_MASK (0x7 << MPDU_RSVD_SHIFT) /* Bit 13-15 */
2646 #define MPDU_FIFOSEL_SHIFT 16
2647 #define MPDU_FIFOSEL_MASK (0x3 << MPDU_FIFOSEL_SHIFT) /* Bit 16-17 */
2648 #endif /* WLAMPDU_HW */
2649
2650 #define MAX_MPDU_SPACE (D11_TXH_LEN + 1538)
2651 #define M_HWAGG_STATS_PTR (0x69 * 2)
2652 #define C_HWAGG_STATS_MPDU_WSZ 66 /* comes first */
2653 #define C_HWAGG_RDEMP_WOFF 64 /* offset within the above block */
2654 #define C_HWAGG_NAMPDU_WOFF 65
2655 #define C_HWAGG_STATS_TXMCS_WSZ 32 /* next blocks: txmcs (32 bytes) and txmcs_succ (32 bytes) */
2656 #define C_HWAGG_STATS_WSZ (C_HWAGG_STATS_MPDU_WSZ + C_HWAGG_STATS_TXMCS_WSZ * 2)
2657 #define C_MBURST_WOFF C_HWAGG_STATS_WSZ
2658 #define C_MBURST_WSZ 8
2659 #define C_AGGBURST_STATS_WSZ (C_HWAGG_STATS_WSZ + C_MBURST_WSZ)
2660
2661 #define M_LCNPHY_BLK_PTR (0x3d * 2)
2662 #define M_LCNPHY_PABIAS_CCK_OFFSET 0
2663 #define M_LCNPHY_PABIAS_OFDM_OFFSET 1
2664 #endif /* _D11_H */
Tomato firmware and modifications.