2 * Broadcom device-specific manifest constants.
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: bcmdevs.h,v 13.290.2.44 2011-02-10 02:07:54 Exp $
25 #define VENDOR_EPIGRAM 0xfeda
26 #define VENDOR_BROADCOM 0x14e4
27 #define VENDOR_3COM 0x10b7
28 #define VENDOR_NETGEAR 0x1385
29 #define VENDOR_DIAMOND 0x1092
30 #define VENDOR_INTEL 0x8086
31 #define VENDOR_DELL 0x1028
32 #define VENDOR_HP 0x103c
33 #define VENDOR_HP_COMPAQ 0x0e11
34 #define VENDOR_APPLE 0x106b
35 #define VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */
36 #define VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */
37 #define VENDOR_TI 0x104c /* Texas Instruments */
38 #define VENDOR_RICOH 0x1180 /* Ricoh */
39 #define VENDOR_JMICRON 0x197b
42 /* PCMCIA vendor IDs */
43 #define VENDOR_BROADCOM_PCMCIA 0x02d0
46 #define VENDOR_BROADCOM_SDIO 0x00BF
49 #define BCM_DNGL_VID 0x0a5c
50 #define BCM_DNGL_BL_PID_4328 0xbd12
51 #define BCM_DNGL_BL_PID_4322 0xbd13
52 #define BCM_DNGL_BL_PID_4319 0xbd16
53 #define BCM_DNGL_BL_PID_43236 0xbd17
54 #define BCM_DNGL_BL_PID_4332 0xbd18
55 #define BCM_DNGL_BL_PID_4330 0xbd19
56 #define BCM_DNGL_BL_PID_43239 0xbd1b
57 #define BCM_DNGL_BDC_PID 0x0bdc
58 #define BCM_DNGL_JTAG_PID 0x4a44
60 /* HW USB BLOCK [CPULESS USB] PIDs */
61 #define BCM_HWUSB_PID_43239 43239
64 #define BCM4210_DEVICE_ID 0x1072 /* never used */
65 #define BCM4230_DEVICE_ID 0x1086 /* never used */
66 #define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
67 #define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
68 #define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
69 #define BCM4211_DEVICE_ID 0x4211
70 #define BCM4231_DEVICE_ID 0x4231
71 #define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
72 #define BCM4311_D11G_ID 0x4311 /* 4311 802.11b/g id */
73 #define BCM4311_D11DUAL_ID 0x4312 /* 4311 802.11a/b/g id */
74 #define BCM4311_D11A_ID 0x4313 /* 4311 802.11a id */
75 #define BCM4328_D11DUAL_ID 0x4314 /* 4328/4312 802.11a/g id */
76 #define BCM4328_D11G_ID 0x4315 /* 4328/4312 802.11g id */
77 #define BCM4328_D11A_ID 0x4316 /* 4328/4312 802.11a id */
78 #define BCM4318_D11G_ID 0x4318 /* 4318 802.11b/g id */
79 #define BCM4318_D11DUAL_ID 0x4319 /* 4318 802.11a/b/g id */
80 #define BCM4318_D11A_ID 0x431a /* 4318 802.11a id */
81 #define BCM4325_D11DUAL_ID 0x431b /* 4325 802.11a/g id */
82 #define BCM4325_D11G_ID 0x431c /* 4325 802.11g id */
83 #define BCM4325_D11A_ID 0x431d /* 4325 802.11a id */
84 #define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
85 #define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
86 #define BCM4306_UART_ID 0x4322 /* 4306 uart */
87 #define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
88 #define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
89 #define BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G_ID; INF w/loose binding war */
90 #define BCM4321_D11N_ID 0x4328 /* 4321 802.11n dualband id */
91 #define BCM4321_D11N2G_ID 0x4329 /* 4321 802.11n 2.4Ghz band id */
92 #define BCM4321_D11N5G_ID 0x432a /* 4321 802.11n 5Ghz band id */
93 #define BCM4322_D11N_ID 0x432b /* 4322 802.11n dualband device */
94 #define BCM4322_D11N2G_ID 0x432c /* 4322 802.11n 2.4GHz device */
95 #define BCM4322_D11N5G_ID 0x432d /* 4322 802.11n 5GHz device */
96 #define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */
97 #define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
98 #define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
99 #define BCM4315_D11DUAL_ID 0x4334 /* 4315 802.11a/g id */
100 #define BCM4315_D11G_ID 0x4335 /* 4315 802.11g id */
101 #define BCM4315_D11A_ID 0x4336 /* 4315 802.11a id */
102 #define BCM4319_D11N_ID 0x4337 /* 4319 802.11n dualband device */
103 #define BCM4319_D11N2G_ID 0x4338 /* 4319 802.11n 2.4G device */
104 #define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
105 #define BCM43231_D11N2G_ID 0x4340 /* 43231 802.11n 2.4GHz device */
106 #define BCM43221_D11N2G_ID 0x4341 /* 43221 802.11n 2.4GHz device */
107 #define BCM43222_D11N_ID 0x4350 /* 43222 802.11n dualband device */
108 #define BCM43222_D11N2G_ID 0x4351 /* 43222 802.11n 2.4GHz device */
109 #define BCM43222_D11N5G_ID 0x4352 /* 43222 802.11n 5GHz device */
110 #define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
111 #define BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */
112 #define BCM43226_D11N_ID 0x4354 /* 43226 802.11n dualband device */
113 #define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
114 #define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
115 #define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
116 #define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
117 #define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */
118 #define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
119 #define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */
120 #define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */
121 #define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */
122 #define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
123 #define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */
124 #define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
125 #define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
126 #define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
127 #define BCM43237_D11N_ID 0x4355 /* 43237 802.11n dualband device */
128 #define BCM43237_D11N5G_ID 0x4356 /* 43237 802.11n 5GHz device */
129 #define BCM43227_D11N2G_ID 0x4358 /* 43228 802.11n 2.4GHz device */
130 #define BCM43228_D11N_ID 0x4359 /* 43228 802.11n DualBand device */
131 #define BCM43228_D11N5G_ID 0x435a /* 43228 802.11n 5GHz device */
132 #define BCM43362_D11N_ID 0x4363 /* 43362 802.11n 2.4GHz device */
133 #define BCM43239_D11N_ID 0x4370 /* 43239 802.11n dualband device */
134 #define BCM4324_D11N_ID 0x4374 /* 4324 802.11n dualband device */
135 #define BCM43217_D11N2G_ID 0x43a9 /* 43217 802.11n 2.4GHz device */
136 #define BCM43131_D11N2G_ID 0x43aa /* 43131 802.11n 2.4GHz device */
138 #define BCM4314_D11N2G_ID 0x4364 /* 4314 802.11n 2.4G device */
139 #define BCM43142_D11N2G_ID 0x4365 /* 43142 802.11n 2.4G device */
141 #define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
142 #define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
143 #define FPGA_JTAGM_ID 0x43f0 /* FPGA jtagm device id */
144 #define BCM_JTAGM_ID 0x43f1 /* BCM jtagm device id */
145 #define SDIOH_FPGA_ID 0x43f2 /* sdio host fpga */
146 #define BCM_SDIOH_ID 0x43f3 /* BCM sdio host id */
147 #define SDIOD_FPGA_ID 0x43f4 /* sdio device fpga */
148 #define SPIH_FPGA_ID 0x43f5 /* PCI SPI Host Controller FPGA */
149 #define BCM_SPIH_ID 0x43f6 /* Synopsis SPI Host Controller */
150 #define MIMO_FPGA_ID 0x43f8 /* FPGA mimo minimacphy device id */
151 #define BCM_JTAGM2_ID 0x43f9 /* BCM alternate jtagm device id */
152 #define SDHCI_FPGA_ID 0x43fa /* Standard SDIO Host Controller FPGA */
153 #define BCM4402_ENET_ID 0x4402 /* 4402 enet */
154 #define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
155 #define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
156 #define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
157 #define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
158 #define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
159 #define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
160 #define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
161 #define BCM47XX_AUDIO_ID 0x4711 /* 47xx audio codec */
162 #define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
163 #define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
164 #define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
165 #define BCM47XX_GMAC_ID 0x4715 /* 47xx Unimac based GbE */
166 #define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
167 #define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
168 #define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
169 #define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
170 #define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
171 #define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
172 #define BCM47XX_ATA100_ID 0x471d /* 47xx parallel ATA */
173 #define BCM47XX_SATAXOR_ID 0x471e /* 47xx serial ATA & XOR DMA */
174 #define BCM47XX_GIGETH_ID 0x471f /* 47xx GbE (5700) */
175 #define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
176 #define BCM4716_DEVICE_ID 0x4722 /* 4716 base devid */
177 #define BCM47XX_SMBUS_EMU_ID 0x47fe /* 47xx emulated SMBus device */
178 #define BCM47XX_XOR_EMU_ID 0x47ff /* 47xx emulated XOR engine */
179 #define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
180 #define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
181 #define JINVANI_SDIOH_ID 0x4743 /* Jinvani SDIO Gold Host */
182 #define BCM27XX_SDIOH_ID 0x2702 /* BCM27xx Standard SDIO Host */
183 #define PCIXX21_FLASHMEDIA_ID 0x803b /* TI PCI xx21 Standard Host Controller */
184 #define PCIXX21_SDIOH_ID 0x803c /* TI PCI xx21 Standard Host Controller */
185 #define R5C822_SDIOH_ID 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */
186 #define JMICRON_SDIOH_ID 0x2381 /* JMicron Standard SDIO Host Controller */
189 #define BCM4306_CHIP_ID 0x4306 /* 4306 chipcommon chipid */
190 #define BCM4311_CHIP_ID 0x4311 /* 4311 PCIe 802.11a/b/g */
191 #define BCM43111_CHIP_ID 43111 /* 43111 chipcommon chipid (OTP chipid) */
192 #define BCM43112_CHIP_ID 43112 /* 43112 chipcommon chipid (OTP chipid) */
193 #define BCM4312_CHIP_ID 0x4312 /* 4312 chipcommon chipid */
194 #define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
195 #define BCM43131_CHIP_ID 43131 /* 43131 chip id (OTP chipid) */
196 #define BCM4315_CHIP_ID 0x4315 /* 4315 chip id */
197 #define BCM4318_CHIP_ID 0x4318 /* 4318 chipcommon chipid */
198 #define BCM4319_CHIP_ID 0x4319 /* 4319 chip id */
199 #define BCM4320_CHIP_ID 0x4320 /* 4320 chipcommon chipid */
200 #define BCM4321_CHIP_ID 0x4321 /* 4321 chipcommon chipid */
201 #define BCM4322_CHIP_ID 0x4322 /* 4322 chipcommon chipid */
202 #define BCM43221_CHIP_ID 43221 /* 43221 chipcommon chipid (OTP chipid) */
203 #define BCM43222_CHIP_ID 43222 /* 43222 chipcommon chipid */
204 #define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
205 #define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
206 #define BCM43227_CHIP_ID 43227 /* 43227 chipcommon chipid */
207 #define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */
208 #define BCM43226_CHIP_ID 43226 /* 43226 chipcommon chipid */
209 #define BCM43231_CHIP_ID 43231 /* 43231 chipcommon chipid (OTP chipid) */
210 #define BCM43234_CHIP_ID 43234 /* 43234 chipcommon chipid */
211 #define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
212 #define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
213 #define BCM43237_CHIP_ID 43237 /* 43237 chipcommon chipid */
214 #define BCM43238_CHIP_ID 43238 /* 43238 chipcommon chipid */
215 #define BCM43239_CHIP_ID 43239 /* 43239 chipcommon chipid */
216 #define BCM43420_CHIP_ID 43420 /* 43222 chipcommon chipid (OTP, RBBU) */
217 #define BCM43421_CHIP_ID 43421 /* 43224 chipcommon chipid (OTP, RBBU) */
218 #define BCM43428_CHIP_ID 43428 /* 43228 chipcommon chipid (OTP, RBBU) */
219 #define BCM43431_CHIP_ID 43431 /* 4331 chipcommon chipid (OTP, RBBU) */
220 #define BCM4325_CHIP_ID 0x4325 /* 4325 chip id */
221 #define BCM4328_CHIP_ID 0x4328 /* 4328 chip id */
222 #define BCM4329_CHIP_ID 0x4329 /* 4329 chipcommon chipid */
223 #define BCM4331_CHIP_ID 0x4331 /* 4331 chipcommon chipid */
224 #define BCM4336_CHIP_ID 0x4336 /* 4336 chipcommon chipid */
225 #define BCM43362_CHIP_ID 43362 /* 43362 chipcommon chipid */
226 #define BCM4330_CHIP_ID 0x4330 /* 4330 chipcommon chipid */
227 #define BCM6362_CHIP_ID 0x6362 /* 6362 chipcommon chipid */
228 #define BCM4334_CHIP_ID 0x4334 /* 4334 chipcommon chipid */
229 #define BCM4334_D11N_ID 0x4380 /* 4334 802.11n dualband device */
230 #define BCM4334_D11N2G_ID 0x4381 /* 4334 802.11n 2.4G device */
231 #define BCM4334_D11N5G_ID 0x4382 /* 4334 802.11n 5G device */
232 #define BCM4314_CHIP_ID 0x4314 /* 4314 chipcommon chipid */
233 #define BCM43142_CHIP_ID 43142 /* 43142 chipcommon chipid */
234 #define BCM4324_CHIP_ID 0x4324 /* 4324 chipcommon chipid */
235 #define BCM4342_CHIP_ID 4342 /* 4342 chipcommon chipid (OTP, RBBU) */
236 #define BCM4402_CHIP_ID 0x4402 /* 4402 chipid */
237 #define BCM4704_CHIP_ID 0x4704 /* 4704 chipcommon chipid */
238 #define BCM4706_CHIP_ID 0x5300 /* 4706 chipcommon chipid */
239 #define BCM4710_CHIP_ID 0x4710 /* 4710 chipid */
240 #define BCM4712_CHIP_ID 0x4712 /* 4712 chipcommon chipid */
241 #define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
242 #define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
243 #define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
244 #define BCM4749_CHIP_ID 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */
245 #define BCM4785_CHIP_ID 0x4785 /* 4785 chipcommon chipid */
246 #define BCM5350_CHIP_ID 0x5350 /* 5350 chipcommon chipid */
247 #define BCM5352_CHIP_ID 0x5352 /* 5352 chipcommon chipid */
248 #define BCM5354_CHIP_ID 0x5354 /* 5354 chipcommon chipid */
249 #define BCM5365_CHIP_ID 0x5365 /* 5365 chipcommon chipid */
250 #define BCM5356_CHIP_ID 0x5356 /* 5356 chipcommon chipid */
251 #define BCM5357_CHIP_ID 0x5357 /* 5357 chipcommon chipid */
252 #define BCM53572_CHIP_ID 53572 /* 53572 chipcommon chipid */
255 #define BCM4303_PKG_ID 2 /* 4303 package id */
256 #define BCM4309_PKG_ID 1 /* 4309 package id */
257 #define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
258 #define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
259 #define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
260 #define BCM4328USBD11G_PKG_ID 2 /* 4328 802.11g USB package id */
261 #define BCM4328USBDUAL_PKG_ID 3 /* 4328 802.11a/g USB package id */
262 #define BCM4328SDIOD11G_PKG_ID 4 /* 4328 802.11g SDIO package id */
263 #define BCM4328SDIODUAL_PKG_ID 5 /* 4328 802.11a/g SDIO package id */
264 #define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
265 #define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
266 #define BCM5354E_PKG_ID 1 /* 5354E package id */
267 #define BCM4716_PKG_ID 8 /* 4716 package id */
268 #define BCM4717_PKG_ID 9 /* 4717 package id */
269 #define BCM4718_PKG_ID 10 /* 4718 package id */
270 #define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */
271 #define BCM5358U_PKG_ID 8 /* 5358U package id */
272 #define BCM5358_PKG_ID 9 /* 5358 package id */
273 #define BCM47186_PKG_ID 10 /* 47186 package id */
274 #define BCM5357_PKG_ID 11 /* 5357 package id */
275 #define BCM5356U_PKG_ID 12 /* 5356U package id */
276 #define BCM53572_PKG_ID 8 /* 53572 package id */
277 #define BCM5357C0_PKG_ID 8 /* 5357c0 package id (the same as 53572) */
278 #define BCM47188_PKG_ID 9 /* 47188 package id */
279 #define BCM5358C0_PKG_ID 0xa /* 5358c0 package id */
280 #define BCM5356C0_PKG_ID 0xb /* 5356c0 package id */
281 #define BCM4331TT_PKG_ID 8 /* 4331 12x12 package id */
282 #define BCM4331TN_PKG_ID 9 /* 4331 12x9 package id */
283 #define BCM4331TNA0_PKG_ID 0xb /* 4331 12x9 package id */
286 #define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
287 #define HDLSIM_PKG_ID 14 /* HDL simulator package id */
288 #define HWSIM_PKG_ID 15 /* Hardware simulator package id */
289 #define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */
290 #define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
291 #define BCM4336_WLBGA_PKG_ID 0x8
292 #define BCM4330_WLBGA_PKG_ID 0x0
293 #define BCM4314PCIE_ARM_PKG_ID (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */
294 #define BCM4314SDIO_PKG_ID (8 | 1) /* 4314 QFN SDIO package id */
295 #define BCM4314PCIE_PKG_ID (8 | 2) /* 4314 QFN PCI (ARM-less) package id */
296 #define BCM4314SDIO_ARM_PKG_ID (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */
297 #define BCM4314SDIO_FPBGA_PKG_ID (8 | 4) /* 4314 FpBGA SDIO package id */
298 #define BCM4314DEV_PKG_ID (8 | 6) /* 4314 Developement package id */
300 #define PCIXX21_FLASHMEDIA0_ID 0x8033 /* TI PCI xx21 Standard Host Controller */
301 #define PCIXX21_SDIOH0_ID 0x8034 /* TI PCI xx21 Standard Host Controller */
304 #define BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */
305 #define BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */
306 #define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
307 #define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication */
308 #define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
309 #define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
310 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
311 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
312 #define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
313 #define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
315 #define BFL_AFTERBURNER 0x00000200 /* Board supports Afterburner mode */
316 #endif /* WLAFTERBURNER */
317 #define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
318 #define BFL_FEM 0x00000800 /* Board supports the Front End Module */
319 #define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
320 #define BFL_HGPA 0x00002000 /* Board has a high gain PA */
321 #define BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios */
322 #define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
323 #define BFL_NOPA 0x00010000 /* Board has no PA */
324 #define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
325 #define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
326 #define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
327 #define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
328 #define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
329 #define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
330 #define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
331 #define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */
332 #define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
333 #define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */
334 #define BFL_FASTPWR 0x08000000
335 #define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */
336 #define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
337 #define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
338 #define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */
339 #define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field
340 * when this flag is set
342 #define BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */
345 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
346 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
347 #define BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */
348 #define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
349 #define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
350 #define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
351 #define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
352 #define BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */
353 #define BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace
356 #define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
357 #define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
358 #define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
359 #define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
360 #define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
361 #define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
362 #define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */
363 #define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */
364 #define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
365 #define BFL2_IPALVLSHIFT_3P3 0x00020000
366 #define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
367 #define BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio "ON"
368 * Most drivers will turn it off without this flag
371 #define BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */
372 #define BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */
373 #define BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */
374 #define BFL2_BT_SHARE_ANT0 0x00800000 /* share core0 antenna with BT */
375 #define BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value
376 * than programmed. The exact delta is decided by
377 * driver per chip/boardtype. This can be used
378 * when tempsense qualification happens after shipment
380 #define BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */
381 #define BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */
382 #define BFL2_EXTLNA_TX 0x08000000 /* Temp boardflag to indicate to */
383 /* ucode control of eLNA during Tx */
384 #define BFL2_4313_RADIOREG 0x10000000
387 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
388 #define BOARD_GPIO_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */
389 #define BOARD_GPIO_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */
390 #define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */
391 #define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */
392 #define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */
393 #define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */
394 #define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
395 #define BOARD_GPIO_12 0x1000 /* gpio 12 */
396 #define BOARD_GPIO_13 0x2000 /* gpio 13 */
397 #define BOARD_GPIO_BTC4_IN 0x0800 /* gpio 11, coex4, in */
398 #define BOARD_GPIO_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */
399 #define BOARD_GPIO_BTC4_STAT 0x4000 /* gpio 14, coex4, status */
400 #define BOARD_GPIO_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */
401 #define BOARD_GPIO_1_WLAN_PWR 0x2 /* throttle WLAN power on X21 board */
402 #define BOARD_GPIO_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */
404 #define GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */
405 #define GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */
406 #define GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */
407 #define GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */
408 #define GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */
409 #define GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */
410 #define GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */
412 #define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
413 #define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
414 #define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
415 #define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
417 /* power control defines */
418 #define PLL_DELAY 150 /* us pll on delay */
419 #define FREF_DELAY 200 /* us fref change delay */
420 #define MIN_SLOW_CLK 32 /* us Slow clock period */
421 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
423 /* Reference Board Types */
424 #define BU4710_BOARD 0x0400
425 #define VSIM4710_BOARD 0x0401
426 #define QT4710_BOARD 0x0402
428 #define BU4309_BOARD 0x040a
429 #define BCM94309CB_BOARD 0x040b
430 #define BCM94309MP_BOARD 0x040c
431 #define BCM4309AP_BOARD 0x040d
433 #define BCM94302MP_BOARD 0x040e
435 #define BU4306_BOARD 0x0416
436 #define BCM94306CB_BOARD 0x0417
437 #define BCM94306MP_BOARD 0x0418
439 #define BCM94710D_BOARD 0x041a
440 #define BCM94710R1_BOARD 0x041b
441 #define BCM94710R4_BOARD 0x041c
442 #define BCM94710AP_BOARD 0x041d
444 #define BU2050_BOARD 0x041f
447 #define BCM94309G_BOARD 0x0421
449 #define BU4704_BOARD 0x0423
450 #define BU4702_BOARD 0x0424
452 #define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
455 #define BCM94702MN_BOARD 0x0428
457 /* BCM4702 1U CompactPCI Board */
458 #define BCM94702CPCI_BOARD 0x0429
460 /* BCM4702 with BCM95380 VLAN Router */
461 #define BCM95380RR_BOARD 0x042a
463 /* cb4306 with SiGe PA */
464 #define BCM94306CBSG_BOARD 0x042b
466 /* cb4306 with SiGe PA */
467 #define PCSG94306_BOARD 0x042d
469 /* bu4704 with sdram */
470 #define BU4704SD_BOARD 0x042e
472 /* Dual 11a/11g Router */
473 #define BCM94704AGR_BOARD 0x042f
475 /* 11a-only minipci */
476 #define BCM94308MP_BOARD 0x0430
480 #define BU4712_BOARD 0x0444
481 #define BU4712SD_BOARD 0x045d
482 #define BU4712L_BOARD 0x045f
485 #define BCM94712AP_BOARD 0x0445
486 #define BCM94712P_BOARD 0x0446
489 #define BU4318_BOARD 0x0447
490 #define CB4318_BOARD 0x0448
491 #define MPG4318_BOARD 0x0449
492 #define MP4318_BOARD 0x044a
493 #define SD4318_BOARD 0x044b
496 #define BCM94313BU_BOARD 0x050f
497 #define BCM94313HM_BOARD 0x0510
498 #define BCM94313EPA_BOARD 0x0511
499 #define BCM94313HMG_BOARD 0x051C
502 #define BCM96338_BOARD 0x6338
503 #define BCM96348_BOARD 0x6348
504 #define BCM96358_BOARD 0x6358
505 #define BCM96368_BOARD 0x6368
507 /* Another mp4306 with SiGe */
508 #define BCM94306P_BOARD 0x044c
511 #define BCM94303MP_BOARD 0x044e
514 #define BCM94306MPSGH_BOARD 0x044f
516 /* BRCM 4306 w/ Front End Modules */
517 #define BCM94306MPM 0x0450
518 #define BCM94306MPL 0x0453
521 #define BCM94712AGR_BOARD 0x0451
524 #define PC4303_BOARD 0x0454
527 #define BCM95350K_BOARD 0x0455
530 #define BCM95350R_BOARD 0x0456
533 #define BCM94306MPLNA_BOARD 0x0457
536 #define BU4320_BOARD 0x0458
537 #define BU4320S_BOARD 0x0459
538 #define BCM94320PH_BOARD 0x045a
541 #define BCM94306MPH_BOARD 0x045b
544 #define BCM94306PCIV_BOARD 0x045c
546 #define BU4712SD_BOARD 0x045d
548 #define BCM94320PFLSH_BOARD 0x045e
550 #define BU4712L_BOARD 0x045f
551 #define BCM94712LGR_BOARD 0x0460
552 #define BCM94320R_BOARD 0x0461
554 #define BU5352_BOARD 0x0462
556 #define BCM94318MPGH_BOARD 0x0463
558 #define BU4311_BOARD 0x0464
559 #define BCM94311MC_BOARD 0x0465
560 #define BCM94311MCAG_BOARD 0x0466
562 #define BCM95352GR_BOARD 0x0467
565 #define BCM95351AGR_BOARD 0x0470
568 #define BCM94704MPCB_BOARD 0x0472
571 #define BU4785_BOARD 0x0478
574 #define BU4321_BOARD 0x046b
575 #define BU4321E_BOARD 0x047c
576 #define MP4321_BOARD 0x046c
577 #define CB2_4321_BOARD 0x046d
578 #define CB2_4321_AG_BOARD 0x0066
579 #define MC4321_BOARD 0x046e
582 #define BU4328_BOARD 0x0481
583 #define BCM4328SDG_BOARD 0x0482
584 #define BCM4328SDAG_BOARD 0x0483
585 #define BCM4328UG_BOARD 0x0484
586 #define BCM4328UAG_BOARD 0x0485
587 #define BCM4328PC_BOARD 0x0486
588 #define BCM4328CF_BOARD 0x0487
591 #define BCM94325DEVBU_BOARD 0x0490
592 #define BCM94325BGABU_BOARD 0x0491
594 #define BCM94325SDGWB_BOARD 0x0492
596 #define BCM94325SDGMDL_BOARD 0x04aa
597 #define BCM94325SDGMDL2_BOARD 0x04c6
598 #define BCM94325SDGMDL3_BOARD 0x04c9
600 #define BCM94325SDABGWBA_BOARD 0x04e1
603 #define BCM94322MC_SSID 0x04a4
604 #define BCM94322USB_SSID 0x04a8 /* dualband */
605 #define BCM94322HM_SSID 0x04b0
606 #define BCM94322USB2D_SSID 0x04bf /* single band discrete front end */
609 #define BCM4312MCGSG_BOARD 0x04b5
612 #define BCM94315DEVBU_SSID 0x04c2
613 #define BCM94315USBGP_SSID 0x04c7
614 #define BCM94315BGABU_SSID 0x04ca
615 #define BCM94315USBGP41_SSID 0x04cb
618 #define BCM94319DEVBU_SSID 0X04e5
619 #define BCM94319USB_SSID 0X04e6
620 #define BCM94319SD_SSID 0X04e7
623 #define BCM94716NR2_SSID 0x04cd
626 #define BCM94319DEVBU_SSID 0X04e5
627 #define BCM94319USBNP4L_SSID 0X04e6
628 #define BCM94319WLUSBN4L_SSID 0X04e7
629 #define BCM94319SDG_SSID 0X04ea
630 #define BCM94319LCUSBSDN4L_SSID 0X04eb
631 #define BCM94319USBB_SSID 0x04ee
632 #define BCM94319LCSDN4L_SSID 0X0507
633 #define BCM94319LSUSBN4L_SSID 0X0508
634 #define BCM94319SDNA4L_SSID 0X0517
635 #define BCM94319SDELNA4L_SSID 0X0518
636 #define BCM94319SDELNA6L_SSID 0X0539
637 #define BCM94319ARCADYAN_SSID 0X0546
638 #define BCM94319WINDSOR_SSID 0x0561
639 #define BCM94319MLAP_SSID 0x0562
640 #define BCM94319SDNA_SSID 0x058b
641 #define BCM94319BHEMU3_SSID 0x0563
642 #define BCM94319SDHMB_SSID 0x058c
643 #define BCM94319SDBREF_SSID 0x05a1
644 #define BCM94319USBSDB_SSID 0x05a2
647 #define BCM94329AGB_SSID 0X04b9
648 #define BCM94329TDKMDL1_SSID 0X04ba
649 #define BCM94329TDKMDL11_SSID 0X04fc
650 #define BCM94329OLYMPICN18_SSID 0X04fd
651 #define BCM94329OLYMPICN90_SSID 0X04fe
652 #define BCM94329OLYMPICN90U_SSID 0X050c
653 #define BCM94329OLYMPICN90M_SSID 0X050b
654 #define BCM94329AGBF_SSID 0X04ff
655 #define BCM94329OLYMPICX17_SSID 0X0504
656 #define BCM94329OLYMPICX17M_SSID 0X050a
657 #define BCM94329OLYMPICX17U_SSID 0X0509
658 #define BCM94329OLYMPICUNO_SSID 0X0564
659 #define BCM94329MOTOROLA_SSID 0X0565
660 #define BCM94329OLYMPICLOCO_SSID 0X0568
661 /* 4336 SDIO board types */
662 #define BCM94336SD_WLBGABU_SSID 0x0511
663 #define BCM94336SD_WLBGAREF_SSID 0x0519
664 #define BCM94336SDGP_SSID 0x0538
665 #define BCM94336SDG_SSID 0x0519
666 #define BCM94336SDGN_SSID 0x0538
667 #define BCM94336SDGFC_SSID 0x056B
669 /* 4330 SDIO board types */
670 #define BCM94330SDG_SSID 0x0528
671 #define BCM94330SD_FCBGABU_SSID 0x052e
672 #define BCM94330SD_WLBGABU_SSID 0x052f
673 #define BCM94330SD_FCBGA_SSID 0x0530
674 #define BCM94330FCSDAGB_SSID 0x0530
675 #define BCM94330OLYMPICAMG_SSID 0x0549
676 #define BCM94330OLYMPICAMGEPA_SSID 0x054F
677 #define BCM94330OLYMPICUNO3_SSID 0x0551
678 #define BCM94330WLSDAGB_SSID 0x0547
679 #define BCM94330CSPSDAGBB_SSID 0x054A
682 #define BCM943224X21 0x056e
683 #define BCM943224X21_FCC 0x00d1
684 #define BCM943224X21B 0x00e9
685 #define BCM943224M93 0x008b
686 #define BCM943224M93A 0x0090
689 #define BCM943228BU8_SSID 0x0540
690 #define BCM943228BU9_SSID 0x0541
691 #define BCM943228BU_SSID 0x0542
692 #define BCM943227HM4L_SSID 0x0543
693 #define BCM943227HMB_SSID 0x0544
694 #define BCM943228HM4L_SSID 0x0545
695 #define BCM943228SD_SSID 0x0573
698 #define BCM943239MOD_SSID 0x05ac
699 #define BCM943239REF_SSID 0x05aa
702 #define BCM94331X19 0x00D6 /* X19B */
703 #define BCM94331PCIEBT3Ax_SSID 0x00E4 /* X28 */
704 #define BCM94331X12_2G_SSID 0x00EC /* X12 2G */
705 #define BCM94331X12_5G_SSID 0x00ED /* X12 5G */
706 #define BCM94331X29B 0x00EF /* X29B */
707 #define BCM94331BU_SSID 0x0523
708 #define BCM94331S9BU_SSID 0x0524
709 #define BCM94331MC_SSID 0x0525
710 #define BCM94331MCI_SSID 0x0526
711 #define BCM94331PCIEBT4_SSID 0x0527
712 #define BCM94331HM_SSID 0x0574
713 #define BCM94331PCIEDUAL_SSID 0x059B
714 #define BCM94331MCH5_SSID 0x05A9
715 #define BCM94331PCIEDUALV2_SSID 0x05B7
716 #define BCM94331CS_SSID 0x05C6
717 #define BCM94331CSAX_SSID 0x00EF
720 #define BCM953572BU_SSID 0x058D
721 #define BCM953572NR2_SSID 0x058E
722 #define BCM947188NR2_SSID 0x058F
723 #define BCM953572SDRNR2_SSID 0x0590
726 #define BCM943236OLYMPICSULLEY_SSID 0x594
727 #define BCM943236PREPROTOBLU2O3_SSID 0x5b9
730 #define GPIO_NUMPINS 32
732 /* These values are used by dhd host driver. */
733 #define RDL_RAM_BASE_4319 0x60000000
734 #define RDL_RAM_BASE_4329 0x60000000
735 #define RDL_RAM_SIZE_4319 0x48000
736 #define RDL_RAM_SIZE_4329 0x48000
737 #define RDL_RAM_SIZE_43236 0x70000
738 #define RDL_RAM_BASE_43236 0x60000000
739 #define RDL_RAM_SIZE_4328 0x60000
740 #define RDL_RAM_BASE_4328 0x80000000
741 #define RDL_RAM_SIZE_4322 0x60000
742 #define RDL_RAM_BASE_4322 0x60000000
745 #define FLASH_KERNEL_NFLASH 0x00000001
746 #define FLASH_BOOT_NFLASH 0x00000002
748 #endif /* _BCMDEVS_H */
