release/src-rt/include/amemc_core.h

   1 /*
   2  * BCM47XX ARM DDR2/DDR3 memory controlers.
   3  *
   4  * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id$
  19  */
  20
  21 #ifndef _AMEMC_H
  22 #define _AMEMC_H
  23
  24 #ifdef _LANGUAGE_ASSEMBLY
  25
  26 #if     defined(IL_BIGENDIAN) && defined(BCMHND74K)
  27 /* Swapped defines for big-endian code in 74K based chips */
  28
  29 #else   /* !IL_BIGENDIAN || !BCMHND74K */
  30
  31 /*
  32  * DDR23PHY registers
  33  */
  34 #define DDR23PHY_PLL_STATUS             0x010
  35 #define DDR23PHY_PLL_CONFIG             0x014
  36 #define DDR23PHY_PLL_PRE_DIVIDER        0x018
  37 #define DDR23PHY_PLL_DIVIDER            0x01c
  38 #define DDR23PHY_STATIC_VDL_OVERRIDE    0x030
  39 #define DDR23PHY_ZQ_PVT_COMP_CTL        0x03c
  40 #define DDR23PHY_BL3_VDL_CALIBRATE      0x104
  41 #define DDR23PHY_BL3_VDL_STATUS         0x108
  42 #define DDR23PHY_BL3_READ_CONTROL       0x130
  43 #define DDR23PHY_BL3_WR_PREAMBLE_MODE   0x148
  44 #define DDR23PHY_BL2_VDL_CALIBRATE      0x204
  45 #define DDR23PHY_BL2_VDL_STATUS         0x208
  46 #define DDR23PHY_BL2_READ_CONTROL       0x230
  47 #define DDR23PHY_BL2_WR_PREAMBLE_MODE   0x248
  48 #define DDR23PHY_BL1_VDL_CALIBRATE      0x304
  49 #define DDR23PHY_BL1_VDL_STATUS         0x308
  50 #define DDR23PHY_BL1_READ_CONTROL       0x330
  51 #define DDR23PHY_BL1_WR_PREAMBLE_MODE   0x348
  52 #define DDR23PHY_BL0_VDL_CALIBRATE      0x404
  53 #define DDR23PHY_BL0_VDL_STATUS         0x408
  54 #define DDR23PHY_BL0_READ_CONTROL       0x430
  55 #define DDR23PHY_BL0_WR_PREAMBLE_MODE   0x448
  56
  57 /*
  58  * PL341 registers
  59  */
  60 #define PL341_memc_status               0x000
  61 #define PL341_memc_cmd                  0x004
  62 #define PL341_direct_cmd                0x008
  63 #define PL341_memory_cfg                0x00c
  64 #define PL341_refresh_prd               0x010
  65 #define PL341_cas_latency               0x014
  66 #define PL341_write_latency             0x018
  67 #define PL341_t_mrd                     0x01c
  68 #define PL341_t_ras                     0x020
  69 #define PL341_t_rc                      0x024
  70 #define PL341_t_rcd                     0x028
  71 #define PL341_t_rfc                     0x02c
  72 #define PL341_t_rp                      0x030
  73 #define PL341_t_rrd                     0x034
  74 #define PL341_t_wr                      0x038
  75 #define PL341_t_wtr                     0x03c
  76 #define PL341_t_xp                      0x040
  77 #define PL341_t_xsr                     0x044
  78 #define PL341_t_esr                     0x048
  79 #define PL341_memory_cfg2               0x04c
  80 #define PL341_memory_cfg3               0x050
  81 #define PL341_t_faw                     0x054
  82 #define PL341_chip_0_cfg                0x200
  83 #define PL341_user_config0              0x304
  84
  85 #endif  /* IL_BIGENDIAN && BCMHND74K */
  86
  87 #endif  /* _LANGUAGE_ASSEMBLY */
  88
  89 #define MEMC_BURST_LENGTH       (4)
  90
  91 #define AI_DDRPHY_BASE       (0x1800f000)
  92
  93 /* Default configuration from bsp_config.h of _BCM953003RSP_ */
  94 /* (required) PLL clock */
  95 #define CFG_DDR_PLL_CLOCK       (331250)        /* KHz */
  96
  97 /* (required) CAS Latency (NOTE: could be affected by PLL clock) */
  98 #define CFG_DDR_CAS_LATENCY     5
  99
 100 /* (required) t_wr (picoseconds) */
 101 #define CFG_DDR_T_WR            15000
 102
 103 /* (optional) Refresh period t_refi (picoseconds) */
 104 #define CFG_DDR_REFRESH_PRD     7800000
 105
 106 /* (optional) t_rfc (picoseconds) */
 107 #define CFG_DDR_T_RFC           105000
 108
 109 /*
 110  * Convenient macros
 111  */
 112 #define MEMCYCLES(psec)   (((psec) * (CFG_DDR_PLL_CLOCK) + 999999999) / 1000000000)
 113
 114 /*
 115  * Convenient macros (minimum requirement and truncated decimal)
 116  */
 117 #define MEMCYCLES_MIN(psec)   ((psec) * (CFG_DDR_PLL_CLOCK) / 1000000000)
 118
 119 /*
 120  * PLL clock configuration
 121  */
 122 #define PLL_NDIV_INT_VAL    (16 * (CFG_DDR_PLL_CLOCK) / 100000)
 123
 124 /*
 125  * Values for PL341 Direct Command Register
 126  */
 127 #define MCHIP_CMD_PRECHARGE_ALL         (0x0 << 18)
 128 #define MCHIP_CMD_AUTO_REFRESH          (0x1 << 18)
 129 #define MCHIP_CMD_MODE_REG              (0x2 << 18)
 130 #define MCHIP_CMD_NOP                   (0x3 << 18)
 131 #define MCHIP_MODEREG_SEL(x)            ((x) << 16)
 132 #define MCHIP_MR_WRITE_RECOVERY(x)      (((x) - 1) << 9)
 133 #define MCHIP_MR_DLL_RESET(x)           ((x) << 8)
 134 #define MCHIP_MR_CAS_LATENCY(x)         ((x) << 4)
 135 #if (MEMC_BURST_LENGTH == 4)
 136 #define MCHIP_MR_BURST_LENGTH           (2)
 137 #else
 138 #define MCHIP_MR_BURST_LENGTH           (3)
 139 #endif
 140 #define MCHIP_EMR1_DLL_DISABLE(x)       ((x) << 0)
 141 #define MCHIP_EMR1_RTT_ODT_DISABLED     (0)
 142 #define MCHIP_EMR1_RTT_75_OHM           (1 << 2)
 143 #define MCHIP_EMR1_RTT_150_OHM          (1 << 6)
 144 #define MCHIP_EMR1_RTT_50_OHM           ((1 << 6) | (1 << 2))
 145 #define MCHIP_EMR1_OCD_CALI_EXIT        (0x0 << 7)
 146 #define MCHIP_EMR1_OCD_CALI_DEFAULT     (0x3 << 7)
 147
 148 /* PVT calibration */
 149 #define PVT_MAX_RETRY       (120)
 150 #define PVT_MATCHED_COUNT   (3)
 151
 152 #endif  /* _AMEMC_H */