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Refactor complete for i386 target.
[tinycc/k1w1.git] / i386-asm.c
bloba0de7a536cdbfa2be3b9851a7d11a5fc8a7b6b51
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "tcc.h"
21 #include "i386-asm-config.h"
22
23 #define MAX_OPERANDS 3
24
25 typedef struct ASMInstr {
26 uint16_t sym;
27 uint16_t opcode;
28 uint16_t instr_type;
29 #define OPC_JMP 0x01 /* jmp operand */
30 #define OPC_B 0x02 /* only used zith OPC_WL */
31 #define OPC_WL 0x04 /* accepts w, l or no suffix */
32 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
33 #define OPC_REG 0x08 /* register is added to opcode */
34 #define OPC_MODRM 0x10 /* modrm encoding */
35 #define OPC_FWAIT 0x20 /* add fwait opcode */
36 #define OPC_TEST 0x40 /* test opcodes */
37 #define OPC_SHIFT 0x80 /* shift opcodes */
38 #define OPC_D16 0x0100 /* generate data16 prefix */
39 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
40 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
41 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
42 #define OPC_GROUP_SHIFT 13
43
44 /* in order to compress the operand type, we use specific operands and
45 we or only with EA */
46 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
53 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
54 #define OPT_SEG 8
55 #define OPT_ST 9
56 #define OPT_IM8 10
57 #define OPT_IM8S 11
58 #define OPT_IM16 12
59 #define OPT_IM32 13
60 #define OPT_EAX 14 /* %al, %ax or %eax register */
61 #define OPT_ST0 15 /* %st(0) register */
62 #define OPT_CL 16 /* %cl register */
63 #define OPT_DX 17 /* %dx register */
64 #define OPT_ADDR 18 /* OP_EA with only offset */
65 #define OPT_INDIR 19 /* *(expr) */
66
67 /* composite types */
68 #define OPT_COMPOSITE_FIRST 20
69 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
70 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
71 #define OPT_REGW 22 /* REG16 | REG32 */
72 #define OPT_IMW 23 /* IM16 | IM32 */
73
74 /* can be ored with any OPT_xxx */
75 #define OPT_EA 0x80
76
77 uint8_t nb_ops;
78 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
79 } ASMInstr;
80
81 typedef struct Operand {
82 uint32_t type;
83 #define OP_REG8 (1 << OPT_REG8)
84 #define OP_REG16 (1 << OPT_REG16)
85 #define OP_REG32 (1 << OPT_REG32)
86 #define OP_MMX (1 << OPT_MMX)
87 #define OP_SSE (1 << OPT_SSE)
88 #define OP_CR (1 << OPT_CR)
89 #define OP_TR (1 << OPT_TR)
90 #define OP_DB (1 << OPT_DB)
91 #define OP_SEG (1 << OPT_SEG)
92 #define OP_ST (1 << OPT_ST)
93 #define OP_IM8 (1 << OPT_IM8)
94 #define OP_IM8S (1 << OPT_IM8S)
95 #define OP_IM16 (1 << OPT_IM16)
96 #define OP_IM32 (1 << OPT_IM32)
97 #define OP_EAX (1 << OPT_EAX)
98 #define OP_ST0 (1 << OPT_ST0)
99 #define OP_CL (1 << OPT_CL)
100 #define OP_DX (1 << OPT_DX)
101 #define OP_ADDR (1 << OPT_ADDR)
102 #define OP_INDIR (1 << OPT_INDIR)
103
104 #define OP_EA 0x40000000
105 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
106 #define OP_IM OP_IM32
107 int8_t reg; /* register, -1 if none */
108 int8_t reg2; /* second register, -1 if none */
109 uint8_t shift;
110 ExprValue e;
111 } Operand;
112
113 static const uint8_t reg_to_size[5] = {
114 /*
115 [OP_REG8] = 0,
116 [OP_REG16] = 1,
117 [OP_REG32] = 2,
118 */
119 0, 0, 1, 0, 2
120 };
121
122 #define NB_TEST_OPCODES 30
123
124 static const uint8_t test_bits[NB_TEST_OPCODES] = {
125 0x00, /* o */
126 0x01, /* no */
127 0x02, /* b */
128 0x02, /* c */
129 0x02, /* nae */
130 0x03, /* nb */
131 0x03, /* nc */
132 0x03, /* ae */
133 0x04, /* e */
134 0x04, /* z */
135 0x05, /* ne */
136 0x05, /* nz */
137 0x06, /* be */
138 0x06, /* na */
139 0x07, /* nbe */
140 0x07, /* a */
141 0x08, /* s */
142 0x09, /* ns */
143 0x0a, /* p */
144 0x0a, /* pe */
145 0x0b, /* np */
146 0x0b, /* po */
147 0x0c, /* l */
148 0x0c, /* nge */
149 0x0d, /* nl */
150 0x0d, /* ge */
151 0x0e, /* le */
152 0x0e, /* ng */
153 0x0f, /* nle */
154 0x0f, /* g */
155 };
156
157 static const uint8_t segment_prefixes[] = {
158 0x26, /* es */
159 0x2e, /* cs */
160 0x36, /* ss */
161 0x3e, /* ds */
162 0x64, /* fs */
163 0x65 /* gs */
164 };
165
166 static const ASMInstr asm_instrs[] = {
167 #define ALT(x) x
168 #define DEF_ASM_OP0(name, opcode)
169 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
170 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
171 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
172 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
173 #include "i386-asm.h"
174
175 /* last operation */
176 { 0, },
177 };
178
179 static const uint16_t op0_codes[] = {
180 #define ALT(x)
181 #define DEF_ASM_OP0(x, opcode) opcode,
182 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
183 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
184 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
185 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
186 #include "i386-asm.h"
187 };
188
189 static inline int get_reg_shift(TCCState *s1)
190 {
191 int shift, v;
192
193 if (s1->seg_size == 16) {
194 error("invalid effective address");
195 }
196
197 v = asm_int_expr(s1);
198 switch(v) {
199 case 1:
200 shift = 0;
201 break;
202 case 2:
203 shift = 1;
204 break;
205 case 4:
206 shift = 2;
207 break;
208 case 8:
209 shift = 3;
210 break;
211 default:
212 expect("1, 2, 4 or 8 constant");
213 shift = 0;
214 break;
215 }
216 return shift;
217 }
218
219 static int asm_parse_reg(void)
220 {
221 int reg;
222 if (tok != '%')
223 goto error_32;
224 next();
225 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
226 reg = tok - TOK_ASM_eax;
227 next();
228 return reg;
229 } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
230 reg = tok - TOK_ASM_ax;
231 next();
232 return reg;
233 } else {
234 error_32:
235 expect("register");
236 return 0;
237 }
238 }
239
240 static void parse_operand(TCCState *s1, Operand *op)
241 {
242 ExprValue e;
243 int reg, indir;
244 const char *p;
245
246 indir = 0;
247 if (tok == '*') {
248 next();
249 indir = OP_INDIR;
250 }
251
252 if (tok == '%') {
253 next();
254 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
255 reg = tok - TOK_ASM_al;
256 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
257 op->reg = reg & 7;
258 if ((op->type & OP_REG) && op->reg == TREG_EAX)
259 op->type |= OP_EAX;
260 else if (op->type == OP_REG8 && op->reg == TREG_ECX)
261 op->type |= OP_CL;
262 else if (op->type == OP_REG16 && op->reg == TREG_EDX)
263 op->type |= OP_DX;
264 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
265 op->type = OP_DB;
266 op->reg = tok - TOK_ASM_dr0;
267 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
268 op->type = OP_SEG;
269 op->reg = tok - TOK_ASM_es;
270 } else if (tok == TOK_ASM_st) {
271 op->type = OP_ST;
272 op->reg = 0;
273 next();
274 if (tok == '(') {
275 next();
276 if (tok != TOK_PPNUM)
277 goto reg_error;
278 p = tokc.cstr->data;
279 reg = p[0] - '0';
280 if ((unsigned)reg >= 8 || p[1] != '\0')
281 goto reg_error;
282 op->reg = reg;
283 next();
284 skip(')');
285 }
286 if (op->reg == 0)
287 op->type |= OP_ST0;
288 goto no_skip;
289 } else {
290 reg_error:
291 error("unknown register");
292 }
293 next();
294 no_skip: ;
295 } else if (tok == '$') {
296 /* constant value */
297 next();
298 asm_expr(s1, &e);
299 op->type = OP_IM32;
300 op->e.v = e.v;
301 op->e.sym = e.sym;
302 if (!op->e.sym) {
303 if (op->e.v == (uint8_t)op->e.v)
304 op->type |= OP_IM8;
305 if (op->e.v == (int8_t)op->e.v)
306 op->type |= OP_IM8S;
307 if (op->e.v == (uint16_t)op->e.v)
308 op->type |= OP_IM16;
309 }
310 } else {
311 /* address(reg,reg2,shift) with all variants */
312 op->type = OP_EA;
313 op->reg = -1;
314 op->reg2 = -1;
315 op->shift = 0;
316 if (tok != '(') {
317 asm_expr(s1, &e);
318 op->e.v = e.v;
319 op->e.sym = e.sym;
320 } else {
321 op->e.v = 0;
322 op->e.sym = NULL;
323 }
324 if (tok == '(') {
325 next();
326 if (tok != ',') {
327 op->reg = asm_parse_reg();
328 }
329 if (tok == ',') {
330 next();
331 if (tok != ',') {
332 op->reg2 = asm_parse_reg();
333 }
334 if (tok == ',') {
335 next();
336 op->shift = get_reg_shift(s1);
337 }
338 }
339 skip(')');
340 }
341 if (op->reg == -1 && op->reg2 == -1)
342 op->type |= OP_ADDR;
343 }
344 op->type |= indir;
345 }
346
347 void gen_le16(int v)
348 {
349 g(v);
350 g(v >> 8);
351 }
352
353 /* XXX: unify with C code output ? */
354 void gen_expr32(ExprValue *pe)
355 {
356 if (pe->sym)
357 greloc(cur_text_section, pe->sym, ind, R_386_32);
358 gen_le32(pe->v);
359 }
360
361 static void gen_expr16(ExprValue *pe)
362 {
363 if (pe->sym)
364 greloc(cur_text_section, pe->sym, ind, R_386_16);
365 gen_le16(pe->v);
366 }
367
368 /* XXX: unify with C code output ? */
369 static void gen_disp32(ExprValue *pe)
370 {
371 Sym *sym;
372 sym = pe->sym;
373 if (sym) {
374 if (sym->r == cur_text_section->sh_num) {
375 /* same section: we can output an absolute value. Note
376 that the TCC compiler behaves differently here because
377 it always outputs a relocation to ease (future) code
378 elimination in the linker */
379 gen_le32(pe->v + sym->jnext - ind - 4);
380 } else {
381 greloc(cur_text_section, sym, ind, R_386_PC32);
382 gen_le32(pe->v - 4);
383 }
384 } else {
385 /* put an empty PC32 relocation */
386 put_elf_reloc(symtab_section, cur_text_section,
387 ind, R_386_PC32, 0);
388 gen_le32(pe->v - 4);
389 }
390 }
391
392 static void gen_disp16(ExprValue *pe)
393 {
394 Sym *sym;
395 sym = pe->sym;
396 if (sym) {
397 if (sym->r == cur_text_section->sh_num) {
398 /* same section: we can output an absolute value. Note
399 that the TCC compiler behaves differently here because
400 it always outputs a relocation to ease (future) code
401 elimination in the linker */
402 gen_le16(pe->v + sym->jnext - ind - 2);
403 } else {
404 greloc(cur_text_section, sym, ind, R_386_PC16);
405 gen_le16(pe->v - 2);
406 }
407 } else {
408 /* put an empty PC32 relocation */
409 put_elf_reloc(symtab_section, cur_text_section,
410 ind, R_386_PC16, 0);
411 gen_le16(pe->v - 2);
412 }
413 }
414
415 /* generate the modrm operand */
416 static inline void asm_modrm(int reg, Operand *op)
417 {
418 int mod, reg1, reg2, sib_reg1;
419
420 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
421 g(0xc0 + (reg << 3) + op->reg);
422 } else if (op->reg == -1 && op->reg2 == -1) {
423 /* displacement only */
424 if (tcc_state->seg_size == 16) {
425 g(0x06 + (reg << 3));
426 gen_expr16(&op->e);
427 } else if (tcc_state->seg_size == 32) {
428 g(0x05 + (reg << 3));
429 gen_expr32(&op->e);
430 }
431 } else {
432 sib_reg1 = op->reg;
433 /* fist compute displacement encoding */
434 if (sib_reg1 == -1) {
435 sib_reg1 = 5;
436 mod = 0x00;
437 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
438 mod = 0x00;
439 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
440 mod = 0x40;
441 } else {
442 mod = 0x80;
443 }
444 /* compute if sib byte needed */
445 reg1 = op->reg;
446 if (op->reg2 != -1)
447 reg1 = 4;
448 if (tcc_state->seg_size == 32) {
449 g(mod + (reg << 3) + reg1);
450 if (reg1 == 4) {
451 /* add sib byte */
452 reg2 = op->reg2;
453 if (reg2 == -1)
454 reg2 = 4; /* indicate no index */
455 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
456 }
457 } else if (tcc_state->seg_size == 16) {
458 /* edi = 7, esi = 6 --> di = 5, si = 4 */
459 if ((reg1 == 6) || (reg1 == 7)) {
460 reg1 -= 2;
461 /* ebx = 3 --> bx = 7 */
462 } else if (reg1 == 3) {
463 reg1 = 7;
464 /* o32 = 5 --> o16 = 6 */
465 } else if (reg1 == 5) {
466 reg1 = 6;
467 /* sib not valid in 16-bit mode */
468 } else if (reg1 == 4) {
469 reg2 = op->reg2;
470 /* bp + si + offset */
471 if ((sib_reg1 == 5) && (reg2 == 6)) {
472 reg1 = 2;
473 /* bp + di + offset */
474 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
475 reg1 = 3;
476 /* bx + si + offset */
477 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
478 reg1 = 0;
479 /* bx + di + offset */
480 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
481 reg1 = 1;
482 } else {
483 error("invalid effective address");
484 }
485 if (op->e.v == 0)
486 mod = 0;
487 } else {
488 error("invalid register");
489 }
490 g(mod + (reg << 3) + reg1);
491 }
492
493 /* add offset */
494 if (mod == 0x40) {
495 g(op->e.v);
496 } else if (mod == 0x80 || op->reg == -1) {
497 if (tcc_state->seg_size == 16)
498 gen_expr16(&op->e);
499 else if (tcc_state->seg_size == 32)
500 gen_expr32(&op->e);
501 }
502 }
503 }
504
505 void asm_opcode(TCCState *s1, int opcode)
506 {
507 const ASMInstr *pa;
508 int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
509 int nb_ops, s;
510 Operand ops[MAX_OPERANDS], *pop;
511 int op_type[3]; /* decoded op type */
512
513 int a32, o32;
514 static int addr32 = 0, data32 = 0;
515
516 /* get operands */
517 pop = ops;
518 nb_ops = 0;
519 seg_prefix = 0;
520 for(;;) {
521 if (tok == ';' || tok == TOK_LINEFEED)
522 break;
523 if (nb_ops >= MAX_OPERANDS) {
524 error("incorrect number of operands");
525 }
526 parse_operand(s1, pop);
527 if (tok == ':') {
528 if (pop->type != OP_SEG || seg_prefix) {
529 bad_prefix:
530 error("incorrect prefix");
531 }
532 seg_prefix = segment_prefixes[pop->reg];
533 next();
534 parse_operand(s1, pop);
535 #if 0
536 if (!(pop->type & OP_EA)) {
537 error("segment prefix must be followed by memory reference");
538 }
539 #endif
540 }
541 pop++;
542 nb_ops++;
543 if (tok != ',')
544 break;
545 next();
546 }
547
548 is_short_jmp = 0;
549 s = 0; /* avoid warning */
550
551 /* optimize matching by using a lookup table (no hashing is needed
552 !) */
553 for(pa = asm_instrs; pa->sym != 0; pa++) {
554 s = 0;
555 if (pa->instr_type & OPC_FARITH) {
556 v = opcode - pa->sym;
557 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
558 continue;
559 } else if (pa->instr_type & OPC_ARITH) {
560 if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
561 continue;
562 goto compute_size;
563 } else if (pa->instr_type & OPC_SHIFT) {
564 if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
565 continue;
566 goto compute_size;
567 } else if (pa->instr_type & OPC_TEST) {
568 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
569 continue;
570 } else if (pa->instr_type & OPC_B) {
571 if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
572 continue;
573 compute_size:
574 s = (opcode - pa->sym) & 3;
575 } else if (pa->instr_type & OPC_WL) {
576 if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
577 continue;
578 s = opcode - pa->sym + 1;
579 } else {
580 if (pa->sym != opcode)
581 continue;
582 }
583 if (pa->nb_ops != nb_ops)
584 continue;
585 /* now decode and check each operand */
586 for(i = 0; i < nb_ops; i++) {
587 int op1, op2;
588 op1 = pa->op_type[i];
589 op2 = op1 & 0x1f;
590 switch(op2) {
591 case OPT_IM:
592 v = OP_IM8 | OP_IM16 | OP_IM32;
593 break;
594 case OPT_REG:
595 v = OP_REG8 | OP_REG16 | OP_REG32;
596 break;
597 case OPT_REGW:
598 v = OP_REG16 | OP_REG32;
599 break;
600 case OPT_IMW:
601 v = OP_IM16 | OP_IM32;
602 break;
603 default:
604 v = 1 << op2;
605 break;
606 }
607 if (op1 & OPT_EA)
608 v |= OP_EA;
609 op_type[i] = v;
610 if ((ops[i].type & v) == 0)
611 goto next;
612 }
613 /* all is matching ! */
614 break;
615 next: ;
616 }
617 if (pa->sym == 0) {
618 if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
619 int b;
620 b = op0_codes[opcode - TOK_ASM_pusha];
621 if (opcode == TOK_ASM_o32) {
622 if (s1->seg_size == 32)
623 goto bad_prefix;
624 else
625 data32 = 1;
626 } else if (opcode == TOK_ASM_a32) {
627 if (s1->seg_size == 32)
628 goto bad_prefix;
629 else
630 addr32 = 1;
631 }
632 if (b & 0xff00)
633 g(b >> 8);
634 g(b);
635 return;
636 } else {
637 error("unknown opcode '%s'",
638 get_tok_str(opcode, NULL));
639 }
640 }
641 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
642 if (s == 3) {
643 for(i = 0; s == 3 && i < nb_ops; i++) {
644 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
645 s = reg_to_size[ops[i].type & OP_REG];
646 }
647 if (s == 3) {
648 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
649 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
650 s = 2;
651 else
652 error("cannot infer opcode suffix");
653 }
654 }
655
656 a32 = o32 = 0;
657 if (s == 1 || (pa->instr_type & OPC_D16)) {
658 if (s1->seg_size == 32)
659 o32 = 1;
660 } else if (s == 2 && !(pa->instr_type & OPC_D16)) {
661 if (s1->seg_size == 16)
662 o32 = 1;
663 }
664
665 /* generate a16/a32 prefix if needed */
666 if ((a32 == 1) && (addr32 == 0))
667 g(0x67);
668 /* generate o16/o32 prefix if needed */
669 if ((o32 == 1) && (data32 == 0))
670 g(0x66);
671
672 addr32 = data32 = 0;
673
674 /* now generates the operation */
675 if (pa->instr_type & OPC_FWAIT)
676 g(0x9b);
677 if (seg_prefix)
678 g(seg_prefix);
679
680 v = pa->opcode;
681 if (v == 0x69 || v == 0x69) {
682 /* kludge for imul $im, %reg */
683 nb_ops = 3;
684 ops[2] = ops[1];
685 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
686 v--; /* int $3 case */
687 nb_ops = 0;
688 } else if ((v == 0x06 || v == 0x07)) {
689 if (ops[0].reg >= 4) {
690 /* push/pop %fs or %gs */
691 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
692 } else {
693 v += ops[0].reg << 3;
694 }
695 nb_ops = 0;
696 } else if (v <= 0x05) {
697 /* arith case */
698 v += ((opcode - TOK_ASM_addb) >> 2) << 3;
699 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
700 /* fpu arith case */
701 v += ((opcode - pa->sym) / 6) << 3;
702 }
703 if (pa->instr_type & OPC_REG) {
704 for(i = 0; i < nb_ops; i++) {
705 if (op_type[i] & (OP_REG | OP_ST)) {
706 v += ops[i].reg;
707 break;
708 }
709 }
710 /* mov $im, %reg case */
711 if (pa->opcode == 0xb0 && s >= 1)
712 v += 7;
713 }
714 if (pa->instr_type & OPC_B)
715 v += s >= 1;
716 if (pa->instr_type & OPC_TEST)
717 v += test_bits[opcode - pa->sym];
718 if (pa->instr_type & OPC_SHORTJMP) {
719 Sym *sym;
720 int jmp_disp;
721
722 /* see if we can really generate the jump with a byte offset */
723 sym = ops[0].e.sym;
724 if (!sym)
725 goto no_short_jump;
726 if (sym->r != cur_text_section->sh_num)
727 goto no_short_jump;
728 jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
729 if (jmp_disp == (int8_t)jmp_disp) {
730 /* OK to generate jump */
731 is_short_jmp = 1;
732 ops[0].e.v = jmp_disp;
733 } else {
734 no_short_jump:
735 if (pa->instr_type & OPC_JMP) {
736 /* long jump will be allowed. need to modify the
737 opcode slightly */
738 if (v == 0xeb)
739 v = 0xe9;
740 else
741 v += 0x0f10;
742 } else {
743 error("invalid displacement");
744 }
745 }
746 }
747 op1 = v >> 8;
748 if (op1)
749 g(op1);
750 g(v);
751
752 /* search which operand will used for modrm */
753 modrm_index = 0;
754 if (pa->instr_type & OPC_SHIFT) {
755 reg = (opcode - pa->sym) >> 2;
756 if (reg == 6)
757 reg = 7;
758 } else if (pa->instr_type & OPC_ARITH) {
759 reg = (opcode - pa->sym) >> 2;
760 } else if (pa->instr_type & OPC_FARITH) {
761 reg = (opcode - pa->sym) / 6;
762 } else {
763 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
764 }
765 if (pa->instr_type & OPC_MODRM) {
766 /* first look for an ea operand */
767 for(i = 0;i < nb_ops; i++) {
768 if (op_type[i] & OP_EA)
769 goto modrm_found;
770 }
771 /* then if not found, a register or indirection (shift instructions) */
772 for(i = 0;i < nb_ops; i++) {
773 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
774 goto modrm_found;
775 }
776 #ifdef ASM_DEBUG
777 error("bad op table");
778 #endif
779 modrm_found:
780 modrm_index = i;
781 /* if a register is used in another operand then it is
782 used instead of group */
783 for(i = 0;i < nb_ops; i++) {
784 v = op_type[i];
785 if (i != modrm_index &&
786 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
787 reg = ops[i].reg;
788 break;
789 }
790 }
791
792 asm_modrm(reg, &ops[modrm_index]);
793 }
794
795 /* emit constants */
796 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
797 /* ljmp or lcall kludge */
798 if (s1->seg_size == 16) {
799 if (o32 == 0)
800 gen_expr16(&ops[1].e);
801 else if (o32 == 1)
802 gen_expr32(&ops[1].e);
803 } else
804 gen_expr32(&ops[1].e);
805 if (ops[0].e.sym) {
806 error_relocate:
807 error("cannot relocate");
808 }
809 gen_le16(ops[0].e.v);
810 } else {
811 for(i = 0;i < nb_ops; i++) {
812 v = op_type[i];
813 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
814 /* if multiple sizes are given it means we must look
815 at the op size */
816 if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
817 v == (OP_IM16 | OP_IM32)) {
818 if (s == 0)
819 v = OP_IM8;
820 else if (s == 1)
821 v = OP_IM16;
822 else
823 v = OP_IM32;
824 }
825 if (v & (OP_IM8 | OP_IM8S)) {
826 if (ops[i].e.sym)
827 goto error_relocate;
828 g(ops[i].e.v);
829 } else if (v & OP_IM16) {
830 if (s1->seg_size == 16)
831 gen_expr16(&ops[i].e);
832 else {
833 if (ops[i].e.sym)
834 goto error_relocate;
835 gen_le16(ops[i].e.v);
836 }
837 } else {
838 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
839 if (is_short_jmp)
840 g(ops[i].e.v);
841 else {
842 if (s1->seg_size == 16)
843 gen_disp16(&ops[i].e);
844 else
845 gen_disp32(&ops[i].e);
846 }
847 } else {
848 if (s1->seg_size == 16) {
849 if ((o32 == 1) && (v & OP_IM32))
850 gen_expr32(&ops[i].e);
851 else
852 gen_expr16(&ops[i].e);
853 } else if (s1->seg_size == 32) {
854 if (o32 == 1)
855 gen_expr16(&ops[i].e);
856 else
857 gen_expr32(&ops[i].e);
858 }
859 }
860 }
861 } else if (v & (OP_REG16 | OP_REG32)) {
862 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
863 /* jmp $r */
864 g(0xE0 + ops[i].reg);
865 }
866 }
867 }
868 }
869 }
870
871 /* return the constraint priority (we allocate first the lowest
872 numbered constraints) */
873 static inline int constraint_priority(const char *str)
874 {
875 int priority, c, pr;
876
877 /* we take the lowest priority */
878 priority = 0;
879 for(;;) {
880 c = *str;
881 if (c == '\0')
882 break;
883 str++;
884 switch(c) {
885 case 'A':
886 pr = 0;
887 break;
888 case 'a':
889 case 'b':
890 case 'c':
891 case 'd':
892 case 'S':
893 case 'D':
894 pr = 1;
895 break;
896 case 'q':
897 pr = 2;
898 break;
899 case 'r':
900 pr = 3;
901 break;
902 case 'N':
903 case 'M':
904 case 'I':
905 case 'i':
906 case 'm':
907 case 'g':
908 pr = 4;
909 break;
910 default:
911 error("unknown constraint '%c'", c);
912 pr = 0;
913 }
914 if (pr > priority)
915 priority = pr;
916 }
917 return priority;
918 }
919
920 static const char *skip_constraint_modifiers(const char *p)
921 {
922 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
923 p++;
924 return p;
925 }
926
927 #define REG_OUT_MASK 0x01
928 #define REG_IN_MASK 0x02
929
930 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
931
932 void asm_compute_constraints(ASMOperand *operands,
933 int nb_operands, int nb_outputs,
934 const uint8_t *clobber_regs,
935 int *pout_reg)
936 {
937 ASMOperand *op;
938 int sorted_op[MAX_ASM_OPERANDS];
939 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
940 const char *str;
941 uint8_t regs_allocated[NB_ASM_REGS];
942
943 /* init fields */
944 for(i=0;i<nb_operands;i++) {
945 op = &operands[i];
946 op->input_index = -1;
947 op->ref_index = -1;
948 op->reg = -1;
949 op->is_memory = 0;
950 op->is_rw = 0;
951 }
952 /* compute constraint priority and evaluate references to output
953 constraints if input constraints */
954 for(i=0;i<nb_operands;i++) {
955 op = &operands[i];
956 str = op->constraint;
957 str = skip_constraint_modifiers(str);
958 if (isnum(*str) || *str == '[') {
959 /* this is a reference to another constraint */
960 k = find_constraint(operands, nb_operands, str, NULL);
961 if ((unsigned)k >= i || i < nb_outputs)
962 error("invalid reference in constraint %d ('%s')",
963 i, str);
964 op->ref_index = k;
965 if (operands[k].input_index >= 0)
966 error("cannot reference twice the same operand");
967 operands[k].input_index = i;
968 op->priority = 5;
969 } else {
970 op->priority = constraint_priority(str);
971 }
972 }
973
974 /* sort operands according to their priority */
975 for(i=0;i<nb_operands;i++)
976 sorted_op[i] = i;
977 for(i=0;i<nb_operands - 1;i++) {
978 for(j=i+1;j<nb_operands;j++) {
979 p1 = operands[sorted_op[i]].priority;
980 p2 = operands[sorted_op[j]].priority;
981 if (p2 < p1) {
982 tmp = sorted_op[i];
983 sorted_op[i] = sorted_op[j];
984 sorted_op[j] = tmp;
985 }
986 }
987 }
988
989 for(i = 0;i < NB_ASM_REGS; i++) {
990 if (clobber_regs[i])
991 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
992 else
993 regs_allocated[i] = 0;
994 }
995 /* esp cannot be used */
996 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
997 /* ebp cannot be used yet */
998 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
999
1000 /* allocate registers and generate corresponding asm moves */
1001 for(i=0;i<nb_operands;i++) {
1002 j = sorted_op[i];
1003 op = &operands[j];
1004 str = op->constraint;
1005 /* no need to allocate references */
1006 if (op->ref_index >= 0)
1007 continue;
1008 /* select if register is used for output, input or both */
1009 if (op->input_index >= 0) {
1010 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1011 } else if (j < nb_outputs) {
1012 reg_mask = REG_OUT_MASK;
1013 } else {
1014 reg_mask = REG_IN_MASK;
1015 }
1016 try_next:
1017 c = *str++;
1018 switch(c) {
1019 case '=':
1020 goto try_next;
1021 case '+':
1022 op->is_rw = 1;
1023 /* FALL THRU */
1024 case '&':
1025 if (j >= nb_outputs)
1026 error("'%c' modifier can only be applied to outputs", c);
1027 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1028 goto try_next;
1029 case 'A':
1030 /* allocate both eax and edx */
1031 if (is_reg_allocated(TREG_EAX) ||
1032 is_reg_allocated(TREG_EDX))
1033 goto try_next;
1034 op->is_llong = 1;
1035 op->reg = TREG_EAX;
1036 regs_allocated[TREG_EAX] |= reg_mask;
1037 regs_allocated[TREG_EDX] |= reg_mask;
1038 break;
1039 case 'a':
1040 reg = TREG_EAX;
1041 goto alloc_reg;
1042 case 'b':
1043 reg = 3;
1044 goto alloc_reg;
1045 case 'c':
1046 reg = TREG_ECX;
1047 goto alloc_reg;
1048 case 'd':
1049 reg = TREG_EDX;
1050 goto alloc_reg;
1051 case 'S':
1052 reg = 6;
1053 goto alloc_reg;
1054 case 'D':
1055 reg = 7;
1056 alloc_reg:
1057 if (is_reg_allocated(reg))
1058 goto try_next;
1059 goto reg_found;
1060 case 'q':
1061 /* eax, ebx, ecx or edx */
1062 for(reg = 0; reg < 4; reg++) {
1063 if (!is_reg_allocated(reg))
1064 goto reg_found;
1065 }
1066 goto try_next;
1067 case 'r':
1068 /* any general register */
1069 for(reg = 0; reg < 8; reg++) {
1070 if (!is_reg_allocated(reg))
1071 goto reg_found;
1072 }
1073 goto try_next;
1074 reg_found:
1075 /* now we can reload in the register */
1076 op->is_llong = 0;
1077 op->reg = reg;
1078 regs_allocated[reg] |= reg_mask;
1079 break;
1080 case 'i':
1081 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1082 goto try_next;
1083 break;
1084 case 'I':
1085 case 'N':
1086 case 'M':
1087 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1088 goto try_next;
1089 break;
1090 case 'm':
1091 case 'g':
1092 /* nothing special to do because the operand is already in
1093 memory, except if the pointer itself is stored in a
1094 memory variable (VT_LLOCAL case) */
1095 /* XXX: fix constant case */
1096 /* if it is a reference to a memory zone, it must lie
1097 in a register, so we reserve the register in the
1098 input registers and a load will be generated
1099 later */
1100 if (j < nb_outputs || c == 'm') {
1101 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1102 /* any general register */
1103 for(reg = 0; reg < 8; reg++) {
1104 if (!(regs_allocated[reg] & REG_IN_MASK))
1105 goto reg_found1;
1106 }
1107 goto try_next;
1108 reg_found1:
1109 /* now we can reload in the register */
1110 regs_allocated[reg] |= REG_IN_MASK;
1111 op->reg = reg;
1112 op->is_memory = 1;
1113 }
1114 }
1115 break;
1116 default:
1117 error("asm constraint %d ('%s') could not be satisfied",
1118 j, op->constraint);
1119 break;
1120 }
1121 /* if a reference is present for that operand, we assign it too */
1122 if (op->input_index >= 0) {
1123 operands[op->input_index].reg = op->reg;
1124 operands[op->input_index].is_llong = op->is_llong;
1125 }
1126 }
1127
1128 /* compute out_reg. It is used to store outputs registers to memory
1129 locations references by pointers (VT_LLOCAL case) */
1130 *pout_reg = -1;
1131 for(i=0;i<nb_operands;i++) {
1132 op = &operands[i];
1133 if (op->reg >= 0 &&
1134 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1135 !op->is_memory) {
1136 for(reg = 0; reg < 8; reg++) {
1137 if (!(regs_allocated[reg] & REG_OUT_MASK))
1138 goto reg_found2;
1139 }
1140 error("could not find free output register for reloading");
1141 reg_found2:
1142 *pout_reg = reg;
1143 break;
1144 }
1145 }
1146
1147 /* print sorted constraints */
1148 #ifdef ASM_DEBUG
1149 for(i=0;i<nb_operands;i++) {
1150 j = sorted_op[i];
1151 op = &operands[j];
1152 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1153 j,
1154 op->id ? get_tok_str(op->id, NULL) : "",
1155 op->constraint,
1156 op->vt->r,
1157 op->reg);
1158 }
1159 if (*pout_reg >= 0)
1160 printf("out_reg=%d\n", *pout_reg);
1161 #endif
1162 }
1163
1164 void subst_asm_operand(CString *add_str,
1165 SValue *sv, int modifier)
1166 {
1167 int r, reg, size, val;
1168 char buf[64];
1169
1170 r = sv->r;
1171 if ((r & VT_VALMASK) == VT_CONST) {
1172 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1173 cstr_ccat(add_str, '$');
1174 if (r & VT_SYM) {
1175 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1176 if (sv->c.i != 0) {
1177 cstr_ccat(add_str, '+');
1178 } else {
1179 return;
1180 }
1181 }
1182 val = sv->c.i;
1183 if (modifier == 'n')
1184 val = -val;
1185 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1186 cstr_cat(add_str, buf);
1187 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1188 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1189 cstr_cat(add_str, buf);
1190 } else if (r & VT_LVAL) {
1191 reg = r & VT_VALMASK;
1192 if (reg >= VT_CONST)
1193 error("internal compiler error");
1194 snprintf(buf, sizeof(buf), "(%%%s)",
1195 get_tok_str(TOK_ASM_eax + reg, NULL));
1196 cstr_cat(add_str, buf);
1197 } else {
1198 /* register case */
1199 reg = r & VT_VALMASK;
1200 if (reg >= VT_CONST)
1201 error("internal compiler error");
1202
1203 /* choose register operand size */
1204 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1205 size = 1;
1206 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1207 size = 2;
1208 else
1209 size = 4;
1210 if (size == 1 && reg >= 4)
1211 size = 4;
1212
1213 if (modifier == 'b') {
1214 if (reg >= 4)
1215 error("cannot use byte register");
1216 size = 1;
1217 } else if (modifier == 'h') {
1218 if (reg >= 4)
1219 error("cannot use byte register");
1220 size = -1;
1221 } else if (modifier == 'w') {
1222 size = 2;
1223 }
1224
1225 switch(size) {
1226 case -1:
1227 reg = TOK_ASM_ah + reg;
1228 break;
1229 case 1:
1230 reg = TOK_ASM_al + reg;
1231 break;
1232 case 2:
1233 reg = TOK_ASM_ax + reg;
1234 break;
1235 default:
1236 reg = TOK_ASM_eax + reg;
1237 break;
1238 }
1239 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1240 cstr_cat(add_str, buf);
1241 }
1242 }
1243
1244 /* generate prolog and epilog code for asm statment */
1245 void asm_gen_code(ASMOperand *operands, int nb_operands,
1246 int nb_outputs, int is_output,
1247 uint8_t *clobber_regs,
1248 int out_reg)
1249 {
1250 uint8_t regs_allocated[NB_ASM_REGS];
1251 ASMOperand *op;
1252 int i, reg;
1253 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1254
1255 /* mark all used registers */
1256 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1257 for(i = 0; i < nb_operands;i++) {
1258 op = &operands[i];
1259 if (op->reg >= 0)
1260 regs_allocated[op->reg] = 1;
1261 }
1262 if (!is_output) {
1263 /* generate reg save code */
1264 for(i = 0; i < NB_SAVED_REGS; i++) {
1265 reg = reg_saved[i];
1266 if (regs_allocated[reg]) {
1267 if (tcc_state->seg_size == 16)
1268 g(0x66);
1269 g(0x50 + reg);
1270 }
1271 }
1272
1273 /* generate load code */
1274 for(i = 0; i < nb_operands; i++) {
1275 op = &operands[i];
1276 if (op->reg >= 0) {
1277 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1278 op->is_memory) {
1279 /* memory reference case (for both input and
1280 output cases) */
1281 SValue sv;
1282 sv = *op->vt;
1283 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1284 load(op->reg, &sv);
1285 } else if (i >= nb_outputs || op->is_rw) {
1286 /* load value in register */
1287 load(op->reg, op->vt);
1288 if (op->is_llong) {
1289 SValue sv;
1290 sv = *op->vt;
1291 sv.c.ul += 4;
1292 load(TREG_EDX, &sv);
1293 }
1294 }
1295 }
1296 }
1297 } else {
1298 /* generate save code */
1299 for(i = 0 ; i < nb_outputs; i++) {
1300 op = &operands[i];
1301 if (op->reg >= 0) {
1302 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1303 if (!op->is_memory) {
1304 SValue sv;
1305 sv = *op->vt;
1306 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1307 load(out_reg, &sv);
1308
1309 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1310 store(op->reg, &sv);
1311 }
1312 } else {
1313 store(op->reg, op->vt);
1314 if (op->is_llong) {
1315 SValue sv;
1316 sv = *op->vt;
1317 sv.c.ul += 4;
1318 store(TREG_EDX, &sv);
1319 }
1320 }
1321 }
1322 }
1323 /* generate reg restore code */
1324 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1325 reg = reg_saved[i];
1326 if (regs_allocated[reg]) {
1327 if (tcc_state->seg_size == 16)
1328 g(0x66);
1329 g(0x58 + reg);
1330 }
1331 }
1332 }
1333 }
1334
1335 void asm_clobber(uint8_t *clobber_regs, const char *str)
1336 {
1337 int reg;
1338 TokenSym *ts;
1339
1340 if (!strcmp(str, "memory") ||
1341 !strcmp(str, "cc"))
1342 return;
1343 ts = tok_alloc(str, strlen(str));
1344 reg = ts->tok;
1345 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1346 reg -= TOK_ASM_eax;
1347 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1348 reg -= TOK_ASM_ax;
1349 } else {
1350 error("invalid clobber register '%s'", str);
1351 }
1352 clobber_regs[reg] = 1;
1353 }
Improvements to libtcc API.