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win32: wincon.h: support more console mode flags
[tinycc.git] / riscv64-asm.c
blob2b4f496bbeb4b763d4d114a8fcf1cb3ca4c4a253
1 /*************************************************************/
2 /*
3 * RISCV64 assembler for TCC
4 *
5 */
6
7 #ifdef TARGET_DEFS_ONLY
8
9 #define CONFIG_TCC_ASM
10 /* 32 general purpose + 32 floating point registers */
11 #define NB_ASM_REGS 64
12
13 ST_FUNC void g(int c);
14 ST_FUNC void gen_le16(int c);
15 ST_FUNC void gen_le32(int c);
16
17 /*************************************************************/
18 #else
19 /*************************************************************/
20 #define USING_GLOBALS
21 #include "tcc.h"
22
23 enum {
24 OPT_REG,
25 OPT_IM12S,
26 OPT_IM32,
27 };
28 // Registers go from 0 to 31. We use next bit to choose general/float
29 #define REG_FLOAT_MASK 0x20
30 #define REG_IS_FLOAT(register_index) ((register_index) & REG_FLOAT_MASK)
31 #define REG_VALUE(register_index) ((register_index) & (REG_FLOAT_MASK-1))
32 #define C_ENCODE_RS1(register_index) (REG_VALUE(register_index) << 7)
33 #define C_ENCODE_RS2(register_index) (REG_VALUE(register_index) << 2)
34 #define ENCODE_RD(register_index) (REG_VALUE(register_index) << 7)
35 #define ENCODE_RS1(register_index) (REG_VALUE(register_index) << 15)
36 #define ENCODE_RS2(register_index) (REG_VALUE(register_index) << 20)
37 #define NTH_BIT(b, n) ((b >> n) & 1)
38 #define OP_IM12S (1 << OPT_IM12S)
39 #define OP_IM32 (1 << OPT_IM32)
40 #define OP_REG (1 << OPT_REG)
41
42 typedef struct Operand {
43 uint32_t type;
44 union {
45 uint8_t reg;
46 uint16_t regset;
47 ExprValue e;
48 };
49 } Operand;
50
51 static void asm_binary_opcode(TCCState* s1, int token);
52 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str);
53 ST_FUNC void asm_compute_constraints(ASMOperand *operands, int nb_operands, int nb_outputs, const uint8_t *clobber_regs, int *pout_reg);
54 static void asm_emit_a(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *rd1, int aq, int rl);
55 static void asm_emit_b(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm);
56 static void asm_emit_i(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
57 static void asm_emit_j(int token, uint32_t opcode, const Operand *rd, const Operand *rs2);
58 static void asm_emit_opcode(uint32_t opcode);
59 static void asm_emit_r(int token, uint32_t opcode, const Operand *rd, const Operand *rs1, const Operand *rs2);
60 static void asm_emit_s(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm);
61 static void asm_emit_u(int token, uint32_t opcode, const Operand *rd, const Operand *rs2);
62 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands, int nb_outputs, int is_output, uint8_t *clobber_regs, int out_reg);
63 static void asm_nullary_opcode(TCCState *s1, int token);
64 ST_FUNC void asm_opcode(TCCState *s1, int token);
65 static int asm_parse_csrvar(int t);
66 ST_FUNC int asm_parse_regvar(int t);
67 static void asm_ternary_opcode(TCCState *s1, int token);
68 static void asm_unary_opcode(TCCState *s1, int token);
69 static void asm_branch_opcode(TCCState *s1, int token, int argc);
70 ST_FUNC void gen_expr32(ExprValue *pe);
71 static void parse_operand(TCCState *s1, Operand *op);
72 static void parse_branch_offset_operand(TCCState *s1, Operand *op);
73 static void parse_operands(TCCState *s1, Operand *ops, int count);
74 static void parse_mem_access_operands(TCCState *s1, Operand* ops);
75 ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier);
76 /* C extension */
77 static void asm_emit_ca(int token, uint16_t opcode, const Operand *rd, const Operand *rs2);
78 static void asm_emit_cb(int token, uint16_t opcode, const Operand *rs1, const Operand *imm);
79 static void asm_emit_ci(int token, uint16_t opcode, const Operand *rd, const Operand *imm);
80 static void asm_emit_ciw(int token, uint16_t opcode, const Operand *rd, const Operand *imm);
81 static void asm_emit_cj(int token, uint16_t opcode, const Operand *imm);
82 static void asm_emit_cl(int token, uint16_t opcode, const Operand *rd, const Operand *rs1, const Operand *imm);
83 static void asm_emit_cr(int token, uint16_t opcode, const Operand *rd, const Operand *rs2);
84 static void asm_emit_cs(int token, uint16_t opcode, const Operand *rs2, const Operand *rs1, const Operand *imm);
85 static void asm_emit_css(int token, uint16_t opcode, const Operand *rs2, const Operand *imm);
86
87 /* XXX: make it faster ? */
88 ST_FUNC void g(int c)
89 {
90 int ind1;
91 if (nocode_wanted)
92 return;
93 ind1 = ind + 1;
94 if (ind1 > cur_text_section->data_allocated)
95 section_realloc(cur_text_section, ind1);
96 cur_text_section->data[ind] = c;
97 ind = ind1;
98 }
99
100 ST_FUNC void gen_le16 (int i)
101 {
102 g(i);
103 g(i>>8);
104 }
105
106 ST_FUNC void gen_le32 (int i)
107 {
108 int ind1;
109 if (nocode_wanted)
110 return;
111 ind1 = ind + 4;
112 if (ind1 > cur_text_section->data_allocated)
113 section_realloc(cur_text_section, ind1);
114 cur_text_section->data[ind++] = i & 0xFF;
115 cur_text_section->data[ind++] = (i >> 8) & 0xFF;
116 cur_text_section->data[ind++] = (i >> 16) & 0xFF;
117 cur_text_section->data[ind++] = (i >> 24) & 0xFF;
118 }
119
120 ST_FUNC void gen_expr32(ExprValue *pe)
121 {
122 gen_le32(pe->v);
123 }
124
125 static void asm_emit_opcode(uint32_t opcode) {
126 gen_le32(opcode);
127 }
128
129 static void asm_nullary_opcode(TCCState *s1, int token)
130 {
131 static const Operand nil = {.type = OP_REG};
132 static const Operand zimm = {.type = OP_IM12S};
133
134 switch (token) {
135 // Sync instructions
136
137 case TOK_ASM_fence_i: // I
138 asm_emit_opcode((0x3 << 2) | 3| (1 << 12));
139 return;
140
141 // System calls
142
143 case TOK_ASM_ecall: // I (pseudo)
144 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12));
145 return;
146 case TOK_ASM_ebreak: // I (pseudo)
147 asm_emit_opcode((0x1C << 2) | 3 | (0 << 12) | (1 << 20));
148 return;
149
150 // Other
151
152 case TOK_ASM_nop:
153 asm_emit_i(token, (4 << 2) | 3, &nil, &nil, &zimm);
154 return;
155
156 case TOK_ASM_wfi:
157 asm_emit_opcode((0x1C << 2) | 3 | (0x105 << 20));
158 return;
159
160 /* Pseudoinstructions */
161 case TOK_ASM_ret:
162 /* jalr zero, x1, 0 */
163 asm_emit_opcode( 0x67 | (0 << 12) | ENCODE_RS1(1) );
164 return;
165
166 /* C extension */
167 case TOK_ASM_c_ebreak:
168 asm_emit_cr(token, 2 | (9 << 12), &nil, &nil);
169 return;
170 case TOK_ASM_c_nop:
171 asm_emit_ci(token, 1, &nil, &zimm);
172 return;
173
174 default:
175 expect("nullary instruction");
176 }
177 }
178
179 /* Parse a text containing operand and store the result in OP */
180 static void parse_operand(TCCState *s1, Operand *op)
181 {
182 ExprValue e = {0};
183 Sym label = {0};
184 int8_t reg;
185
186 op->type = 0;
187
188 if ((reg = asm_parse_regvar(tok)) != -1) {
189 next(); // skip register name
190 op->type = OP_REG;
191 op->reg = (uint8_t) reg;
192 return;
193 } else if (tok == '$') {
194 /* constant value */
195 next(); // skip '#' or '$'
196 } else if ((e.v = asm_parse_csrvar(tok)) != -1) {
197 next();
198 } else {
199 asm_expr(s1, &e);
200 }
201 op->type = OP_IM32;
202 op->e = e;
203 /* compare against unsigned 12-bit maximum */
204 if (!op->e.sym) {
205 if ((int) op->e.v >= -0x1000 && (int) op->e.v < 0x1000)
206 op->type = OP_IM12S;
207 } else if (op->e.sym->type.t & (VT_EXTERN | VT_STATIC)) {
208 label.type.t = VT_VOID | VT_STATIC;
209
210 /* use the medium PIC model: GOT, auipc, lw */
211 if (op->e.sym->type.t & VT_STATIC)
212 greloca(cur_text_section, op->e.sym, ind, R_RISCV_PCREL_HI20, 0);
213 else
214 greloca(cur_text_section, op->e.sym, ind, R_RISCV_GOT_HI20, 0);
215 put_extern_sym(&label, cur_text_section, ind, 0);
216 greloca(cur_text_section, &label, ind+4, R_RISCV_PCREL_LO12_I, 0);
217
218 op->type = OP_IM12S;
219 op->e.v = 0;
220 } else {
221 expect("operand");
222 }
223 }
224
225 static void parse_branch_offset_operand(TCCState *s1, Operand *op){
226 ExprValue e = {0};
227
228 asm_expr(s1, &e);
229 op->type = OP_IM32;
230 op->e = e;
231 /* compare against unsigned 12-bit maximum */
232 if (!op->e.sym) {
233 if ((int) op->e.v >= -0x1000 && (int) op->e.v < 0x1000)
234 op->type = OP_IM12S;
235 } else if (op->e.sym->type.t & (VT_EXTERN | VT_STATIC)) {
236 greloca(cur_text_section, op->e.sym, ind, R_RISCV_BRANCH, 0);
237
238 /* XXX: Implement far branches */
239
240 op->type = OP_IM12S;
241 op->e.v = 0;
242 } else {
243 expect("operand");
244 }
245 }
246
247 static void parse_jump_offset_operand(TCCState *s1, Operand *op){
248 ExprValue e = {0};
249
250 asm_expr(s1, &e);
251 op->type = OP_IM32;
252 op->e = e;
253 /* compare against unsigned 12-bit maximum */
254 if (!op->e.sym) {
255 if ((int) op->e.v >= -0x1000 && (int) op->e.v < 0x1000)
256 op->type = OP_IM12S;
257 } else if (op->e.sym->type.t & (VT_EXTERN | VT_STATIC)) {
258 greloca(cur_text_section, op->e.sym, ind, R_RISCV_JAL, 0);
259 op->type = OP_IM12S;
260 op->e.v = 0;
261 } else {
262 expect("operand");
263 }
264 }
265
266 static void parse_operands(TCCState *s1, Operand* ops, int count){
267 int i;
268 for (i = 0; i < count; i++) {
269 if ( i != 0 ) {
270 if ( tok == ',')
271 next();
272 else
273 expect("','");
274 }
275 parse_operand(s1, &ops[i]);
276 }
277 }
278
279 /* parse `X, imm(Y)` to {X, Y, imm} operands */
280 static void parse_mem_access_operands(TCCState *s1, Operand* ops){
281 static const Operand zimm = {.type = OP_IM12S};
282
283 Operand op;
284
285 parse_operand(s1, &ops[0]);
286 if ( tok == ',')
287 next();
288 else
289 expect("','");
290
291 if ( tok == '(') {
292 /* `X, (Y)` case*/
293 next();
294 parse_operand(s1, &ops[1]);
295 if ( tok == ')') next(); else expect("')'");
296 ops[2] = zimm;
297 } else {
298 parse_operand(s1, &ops[2]);
299 if ( tok == '('){
300 /* `X, imm(Y)` case*/
301 next();
302 parse_operand(s1, &ops[1]);
303 if ( tok == ')') next(); else expect("')'");
304 } else {
305 /* `X, Y` case*/
306 /* we parsed Y thinking it was imm, swap and default imm to zero */
307 op = ops[2];
308 ops[1] = ops[2];
309 ops[2] = op;
310 ops[2] = zimm;
311 }
312 }
313 }
314
315 /* This is special: First operand is optional */
316 static void asm_jal_opcode(TCCState *s1, int token){
317 static const Operand ra = {.type = OP_REG, .reg = 1};
318 static const Operand zero = {.type = OP_REG};
319 Operand ops[2];
320
321 if (token == TOK_ASM_j ){
322 ops[0] = zero; // j offset
323 } else if (asm_parse_regvar(tok) == -1) {
324 ops[0] = ra; // jal offset
325 } else {
326 // jal reg, offset
327 parse_operand(s1, &ops[0]);
328 if ( tok == ',') next(); else expect("','");
329 }
330 parse_jump_offset_operand(s1, &ops[1]);
331 asm_emit_j(token, 0x6f, &ops[0], &ops[1]);
332 }
333
334 /* This is special: It can be a pseudointruction or a instruction */
335 static void asm_jalr_opcode(TCCState *s1, int token){
336 static const Operand zimm = {.type = OP_IM12S};
337 static const Operand ra = {.type = OP_REG, .reg = 1};
338 Operand ops[3];
339 Operand op;
340
341 parse_operand(s1, &ops[0]);
342 if ( tok == ',')
343 next();
344 else {
345 /* no more operands, it's the pseudoinstruction:
346 * jalr rs
347 * Expand to:
348 * jalr ra, 0(rs)
349 */
350 asm_emit_i(token, 0x67 | (0 << 12), &ra, &ops[0], &zimm);
351 return;
352 }
353
354 if ( tok == '(') {
355 /* `X, (Y)` case*/
356 next();
357 parse_operand(s1, &ops[1]);
358 if ( tok == ')') next(); else expect("')'");
359 ops[2] = zimm;
360 } else {
361 parse_operand(s1, &ops[2]);
362 if ( tok == '('){
363 /* `X, imm(Y)` case*/
364 next();
365 parse_operand(s1, &ops[1]);
366 if ( tok == ')') next(); else expect("')'");
367 } else {
368 /* `X, Y` case*/
369 /* we parsed Y thinking it was imm, swap and default imm to zero */
370 op = ops[2];
371 ops[1] = ops[2];
372 ops[2] = op;
373 ops[2] = zimm;
374 }
375 }
376 /* jalr(RD, RS1, IMM); I-format */
377 asm_emit_i(token, 0x67 | (0 << 12), &ops[0], &ops[1], &ops[2]);
378 }
379
380
381 static void asm_unary_opcode(TCCState *s1, int token)
382 {
383 uint32_t opcode = (0x1C << 2) | 3 | (2 << 12);
384 Operand op;
385 static const Operand zero = {.type = OP_REG};
386 static const Operand zimm = {.type = OP_IM12S};
387
388 parse_operands(s1, &op, 1);
389 /* Note: Those all map to CSR--so they are pseudo-instructions. */
390 opcode |= ENCODE_RD(op.reg);
391
392 switch (token) {
393 /* pseudoinstructions */
394 case TOK_ASM_rdcycle:
395 asm_emit_opcode(opcode | (0xC00 << 20));
396 return;
397 case TOK_ASM_rdcycleh:
398 asm_emit_opcode(opcode | (0xC80 << 20));
399 return;
400 case TOK_ASM_rdtime:
401 asm_emit_opcode(opcode | (0xC01 << 20) | ENCODE_RD(op.reg));
402 return;
403 case TOK_ASM_rdtimeh:
404 asm_emit_opcode(opcode | (0xC81 << 20) | ENCODE_RD(op.reg));
405 return;
406 case TOK_ASM_rdinstret:
407 asm_emit_opcode(opcode | (0xC02 << 20) | ENCODE_RD(op.reg));
408 return;
409 case TOK_ASM_rdinstreth:
410 asm_emit_opcode(opcode | (0xC82 << 20) | ENCODE_RD(op.reg));
411 return;
412
413 case TOK_ASM_jr:
414 /* jalr zero, 0(rs)*/
415 asm_emit_i(token, 0x67 | (0 << 12), &zero, &op, &zimm);
416 return;
417 case TOK_ASM_call:
418 /* auipc ra, 0 */
419 greloca(cur_text_section, op.e.sym, ind, R_RISCV_CALL, 0);
420 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(1));
421 /* jalr zero, 0(ra) */
422 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(1));
423 return;
424 case TOK_ASM_tail:
425 /* auipc x6, 0 */
426 greloca(cur_text_section, op.e.sym, ind, R_RISCV_CALL, 0);
427 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(6));
428 /* jalr zero, 0(x6) */
429 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(6));
430 return;
431
432 /* C extension */
433 case TOK_ASM_c_j:
434 asm_emit_cj(token, 1 | (5 << 13), &op);
435 return;
436 case TOK_ASM_c_jal: /* RV32C-only */
437 asm_emit_cj(token, 1 | (1 << 13), &op);
438 return;
439 case TOK_ASM_c_jalr:
440 asm_emit_cr(token, 2 | (9 << 12), &op, &zero);
441 return;
442 case TOK_ASM_c_jr:
443 asm_emit_cr(token, 2 | (8 << 12), &op, &zero);
444 return;
445 default:
446 expect("unary instruction");
447 }
448 }
449
450 static void asm_emit_u(int token, uint32_t opcode, const Operand* rd, const Operand* rs2)
451 {
452 if (rd->type != OP_REG) {
453 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
454 return;
455 }
456 if (rs2->type != OP_IM12S && rs2->type != OP_IM32) {
457 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token, NULL));
458 return;
459 } else if (rs2->e.v >= 0x100000) {
460 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0xfffff", get_tok_str(token, NULL));
461 return;
462 }
463 /* U-type instruction:
464 31...12 imm[31:12]
465 11...7 rd
466 6...0 opcode */
467 gen_le32(opcode | ENCODE_RD(rd->reg) | (rs2->e.v << 12));
468 }
469
470 static int parse_fence_operand(){
471 int t = tok;
472 if ( tok == TOK_ASM_or ){
473 // we are in a fence instruction, parse as output read
474 t = TOK_ASM_or_fence;
475 }
476 next();
477 return t - (TOK_ASM_w_fence - 1);
478 }
479
480 static void asm_fence_opcode(TCCState *s1, int token){
481 // `fence` is both an instruction and a pseudoinstruction:
482 // `fence` expands to `fence iorw, iorw`
483 int succ = 0xF, pred = 0xF;
484 if (tok != TOK_LINEFEED && tok != ';' && tok != CH_EOF){
485 pred = parse_fence_operand();
486 if ( pred > 0xF || pred < 0) {
487 tcc_error("'%s': Expected first operand that is a valid predecessor operand", get_tok_str(token, NULL));
488 }
489 if ( tok == ',') next(); else expect("','");
490 succ = parse_fence_operand();
491 if ( succ > 0xF || succ < 0) {
492 tcc_error("'%s': Expected second operand that is a valid successor operand", get_tok_str(token, NULL));
493 }
494 }
495 asm_emit_opcode((0x3 << 2) | 3 | (0 << 12) | succ<<20 | pred<<24);
496 }
497
498 static void asm_binary_opcode(TCCState* s1, int token)
499 {
500 static const Operand zero = {.type = OP_REG, .reg = 0};
501 Operand imm = {.type = OP_IM12S, .e = {.v = 0}};
502 Operand ops[2];
503 int32_t lo;
504 uint32_t hi;
505
506 parse_operands(s1, &ops[0], 2);
507 switch (token) {
508 case TOK_ASM_lui:
509 asm_emit_u(token, (0xD << 2) | 3, &ops[0], &ops[1]);
510 return;
511 case TOK_ASM_auipc:
512 asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[1]);
513 return;
514
515 /* C extension */
516 case TOK_ASM_c_add:
517 asm_emit_cr(token, 2 | (9 << 12), ops, ops + 1);
518 return;
519 case TOK_ASM_c_mv:
520 asm_emit_cr(token, 2 | (8 << 12), ops, ops + 1);
521 return;
522
523 case TOK_ASM_c_addi16sp:
524 asm_emit_ci(token, 1 | (3 << 13), ops, ops + 1);
525 return;
526 case TOK_ASM_c_addi:
527 asm_emit_ci(token, 1, ops, ops + 1);
528 return;
529 case TOK_ASM_c_addiw:
530 asm_emit_ci(token, 1 | (1 << 13), ops, ops + 1);
531 return;
532 case TOK_ASM_c_fldsp:
533 asm_emit_ci(token, 2 | (1 << 13), ops, ops + 1);
534 return;
535 case TOK_ASM_c_flwsp: /* RV32FC-only */
536 asm_emit_ci(token, 2 | (3 << 13), ops, ops + 1);
537 return;
538 case TOK_ASM_c_ldsp:
539 asm_emit_ci(token, 2 | (3 << 13), ops, ops + 1);
540 return;
541 case TOK_ASM_c_li:
542 asm_emit_ci(token, 1 | (2 << 13), ops, ops + 1);
543 return;
544 case TOK_ASM_c_lui:
545 asm_emit_ci(token, 1 | (3 << 13), ops, ops + 1);
546 return;
547 case TOK_ASM_c_lwsp:
548 asm_emit_ci(token, 2 | (2 << 13), ops, ops + 1);
549 return;
550 case TOK_ASM_c_slli:
551 asm_emit_ci(token, 2, ops, ops + 1);
552 return;
553
554 case TOK_ASM_c_addi4spn:
555 asm_emit_ciw(token, 0, ops, ops + 1);
556 return;
557
558 #define CA (1 | (3 << 10) | (4 << 13))
559 case TOK_ASM_c_addw:
560 asm_emit_ca(token, CA | (1 << 5) | (1 << 12), ops, ops + 1);
561 return;
562 case TOK_ASM_c_and:
563 asm_emit_ca(token, CA | (3 << 5), ops, ops + 1);
564 return;
565 case TOK_ASM_c_or:
566 asm_emit_ca(token, CA | (2 << 5), ops, ops + 1);
567 return;
568 case TOK_ASM_c_sub:
569 asm_emit_ca(token, CA, ops, ops + 1);
570 return;
571 case TOK_ASM_c_subw:
572 asm_emit_ca(token, CA | (1 << 12), ops, ops + 1);
573 return;
574 case TOK_ASM_c_xor:
575 asm_emit_ca(token, CA | (1 << 5), ops, ops + 1);
576 return;
577 #undef CA
578
579 case TOK_ASM_c_andi:
580 asm_emit_cb(token, 1 | (2 << 10) | (4 << 13), ops, ops + 1);
581 return;
582 case TOK_ASM_c_beqz:
583 asm_emit_cb(token, 1 | (6 << 13), ops, ops + 1);
584 return;
585 case TOK_ASM_c_bnez:
586 asm_emit_cb(token, 1 | (7 << 13), ops, ops + 1);
587 return;
588 case TOK_ASM_c_srai:
589 asm_emit_cb(token, 1 | (1 << 10) | (4 << 13), ops, ops + 1);
590 return;
591 case TOK_ASM_c_srli:
592 asm_emit_cb(token, 1 | (4 << 13), ops, ops + 1);
593 return;
594
595 case TOK_ASM_c_sdsp:
596 asm_emit_css(token, 2 | (7 << 13), ops, ops + 1);
597 return;
598 case TOK_ASM_c_swsp:
599 asm_emit_css(token, 2 | (6 << 13), ops, ops + 1);
600 return;
601 case TOK_ASM_c_fswsp: /* RV32FC-only */
602 asm_emit_css(token, 2 | (7 << 13), ops, ops + 1);
603 return;
604 case TOK_ASM_c_fsdsp:
605 asm_emit_css(token, 2 | (5 << 13), ops, ops + 1);
606 return;
607
608 /* pseudoinstructions */
609 /* rd, sym */
610 case TOK_ASM_la:
611 /* auipc rd, 0 */
612 asm_emit_u(token, 3 | (5 << 2), ops, ops + 1);
613 /* lw rd, rd, 0 */
614 asm_emit_i(token, 3 | (2 << 12), ops, ops, ops + 1);
615 return;
616 case TOK_ASM_lla:
617 /* auipc rd, 0 */
618 asm_emit_u(token, 3 | (5 << 2), ops, ops + 1);
619 /* addi rd, rd, 0 */
620 asm_emit_i(token, 3 | (4 << 2), ops, ops, ops + 1);
621 return;
622 case TOK_ASM_li:
623 if(ops[1].type != OP_IM32 && ops[1].type != OP_IM12S){
624 tcc_error("'%s': Expected first source operand that is an immediate value between 0 and 0xFFFFFFFFFFFFFFFF", get_tok_str(token, NULL));
625 }
626 lo = ops[1].e.v;
627 hi = (int64_t)ops[1].e.v >> 32;
628 if(lo < 0){
629 hi += 1;
630 }
631 imm.e.v = ((hi + 0x800) & 0xfffff000) >> 12;
632 /* lui rd, HI_20(HI_32(imm)) */
633 asm_emit_u(token, (0xD << 2) | 3, &ops[0], &imm);
634 /* addi rd, rd, LO_12(HI_32(imm)) */
635 imm.e.v = (int32_t)hi<<20>>20;
636 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
637 /* slli rd, rd, 12 */
638 imm.e.v = 12;
639 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
640 /* addi rd, rd, HI_12(LO_32(imm)) */
641 imm.e.v = (lo + (1<<19)) >> 20;
642 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
643 /* slli rd, rd, 12 */
644 imm.e.v = 12;
645 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
646 /* addi rd, rd, HI_12(LO_20(LO_32imm)) */
647 lo = lo << 12 >> 12;
648 imm.e.v = lo >> 8;
649 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
650 /* slli rd, rd, 8 */
651 imm.e.v = 8;
652 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[0], &imm);
653 /* addi rd, rd, LO_8(LO_20(LO_32imm)) */
654 lo &= 0xff;
655 imm.e.v = lo << 20 >> 20;
656 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[0], &imm);
657 return;
658 case TOK_ASM_mv:
659 /* addi rd, rs, 0 */
660 asm_emit_i(token, 3 | (4 << 2), &ops[0], &ops[1], &imm);
661 return;
662 case TOK_ASM_not:
663 /* xori rd, rs, -1 */
664 imm.e.v = -1;
665 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &imm);
666 return;
667 case TOK_ASM_neg:
668 /* sub rd, x0, rs */
669 imm.e.v = 1;
670 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &zero, &imm);
671 return;
672 case TOK_ASM_negw:
673 /* sub rd, x0, rs */
674 imm.e.v = 1;
675 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &zero, &imm);
676 return;
677 case TOK_ASM_jump:
678 /* auipc x5, 0 */
679 asm_emit_opcode(3 | (5 << 2) | ENCODE_RD(5));
680 greloca(cur_text_section, ops->e.sym, ind, R_RISCV_CALL, 0);
681 /* jalr zero, 0(x5) */
682 asm_emit_opcode(0x67 | (0 << 12) | ENCODE_RS1(5));
683 return;
684 case TOK_ASM_seqz:
685 /* sltiu rd, rs, 1 */
686 imm.e.v = 1;
687 asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &imm);
688 return;
689 case TOK_ASM_snez:
690 /* sltu rd, zero, rs */
691 imm.e.v = 1;
692 asm_emit_r(token, (0xC << 2) | 3 | (3 << 12), &ops[0], &zero, &ops[1]);
693 return;
694 case TOK_ASM_sltz:
695 /* slt rd, rs, zero */
696 asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &zero);
697 return;
698 case TOK_ASM_sgtz:
699 /* slt rd, zero, rs */
700 asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &zero, &ops[1]);
701 return;
702
703 default:
704 expect("binary instruction");
705 }
706 }
707
708 /* caller: Add funct3, funct7 into opcode */
709 static void asm_emit_r(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2)
710 {
711 if (rd->type != OP_REG) {
712 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
713 return;
714 }
715 if (rs1->type != OP_REG) {
716 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
717 return;
718 }
719 if (rs2->type != OP_REG) {
720 tcc_error("'%s': Expected second source operand that is a register or immediate", get_tok_str(token, NULL));
721 return;
722 }
723 /* R-type instruction:
724 31...25 funct7
725 24...20 rs2
726 19...15 rs1
727 14...12 funct3
728 11...7 rd
729 6...0 opcode */
730 gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg));
731 }
732
733 /* caller: Add funct3 into opcode */
734 static void asm_emit_i(int token, uint32_t opcode, const Operand* rd, const Operand* rs1, const Operand* rs2)
735 {
736 if (rd->type != OP_REG) {
737 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
738 return;
739 }
740 if (rs1->type != OP_REG) {
741 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
742 return;
743 }
744 if (rs2->type != OP_IM12S) {
745 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token, NULL));
746 return;
747 }
748 /* I-type instruction:
749 31...20 imm[11:0]
750 19...15 rs1
751 14...12 funct3
752 11...7 rd
753 6...0 opcode */
754
755 gen_le32(opcode | ENCODE_RD(rd->reg) | ENCODE_RS1(rs1->reg) | (rs2->e.v << 20));
756 }
757
758 static void asm_emit_j(int token, uint32_t opcode, const Operand* rd, const Operand* rs2)
759 {
760 uint32_t imm;
761
762 if (rd->type != OP_REG) {
763 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
764 return;
765 }
766 if (rs2->type != OP_IM12S && rs2->type != OP_IM32) {
767 tcc_error("'%s': Expected second source operand that is an immediate value", get_tok_str(token, NULL));
768 return;
769 }
770
771 imm = rs2->e.v;
772
773 /* even offsets in a +- 1 MiB range */
774 if ((int)imm > (1 << 20) -1 || (int)imm <= -1 * ((1 << 20) -1)) {
775 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 0x1fffff", get_tok_str(token, NULL));
776 return;
777 }
778
779 if (imm & 1) {
780 tcc_error("'%s': Expected second source operand that is an even immediate value", get_tok_str(token, NULL));
781 return;
782 }
783 /* J-type instruction:
784 31 imm[20]
785 30...21 imm[10:1]
786 20 imm[11]
787 19...12 imm[19:12]
788 11...7 rd
789 6...0 opcode */
790 gen_le32(opcode | ENCODE_RD(rd->reg) | (((imm >> 20) & 1) << 31) | (((imm >> 1) & 0x3ff) << 21) | (((imm >> 11) & 1) << 20) | (((imm >> 12) & 0xff) << 12));
791 }
792
793 static void asm_mem_access_opcode(TCCState *s1, int token)
794 {
795
796 Operand ops[3];
797 parse_mem_access_operands(s1, &ops[0]);
798
799 /* Pseudoinstruction: inst reg, label
800 * expand to:
801 * auipc reg, 0
802 * inst reg, 0(reg)
803 * And with the proper relocation to label
804 */
805 if (ops[1].type == OP_IM32 && ops[1].e.sym && ops[1].e.sym->type.t & VT_STATIC){
806 ops[1] = ops[0];
807 /* set the offset to zero */
808 ops[2].type = OP_IM12S;
809 ops[2].e.v = 0;
810 /* auipc reg, 0 */
811 asm_emit_u(token, (0x05 << 2) | 3, &ops[0], &ops[2]);
812 }
813
814 switch (token) {
815 // l{b|h|w|d}[u] rd, imm(rs1); I-format
816 case TOK_ASM_lb:
817 asm_emit_i(token, (0x0 << 2) | 3, &ops[0], &ops[1], &ops[2]);
818 return;
819 case TOK_ASM_lh:
820 asm_emit_i(token, (0x0 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
821 return;
822 case TOK_ASM_lw:
823 asm_emit_i(token, (0x0 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]);
824 return;
825 case TOK_ASM_ld:
826 asm_emit_i(token, (0x0 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
827 return;
828 case TOK_ASM_lbu:
829 asm_emit_i(token, (0x0 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
830 return;
831 case TOK_ASM_lhu:
832 asm_emit_i(token, (0x0 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
833 return;
834 case TOK_ASM_lwu:
835 asm_emit_i(token, (0x0 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]);
836 return;
837
838 // s{b|h|w|d} rs2, imm(rs1); S-format (with rsX swapped)
839 case TOK_ASM_sb:
840 asm_emit_s(token, (0x8 << 2) | 3 | (0 << 12), &ops[1], &ops[0], &ops[2]);
841 return;
842 case TOK_ASM_sh:
843 asm_emit_s(token, (0x8 << 2) | 3 | (1 << 12), &ops[1], &ops[0], &ops[2]);
844 return;
845 case TOK_ASM_sw:
846 asm_emit_s(token, (0x8 << 2) | 3 | (2 << 12), &ops[1], &ops[0], &ops[2]);
847 return;
848 case TOK_ASM_sd:
849 asm_emit_s(token, (0x8 << 2) | 3 | (3 << 12), &ops[1], &ops[0], &ops[2]);
850 return;
851 }
852 }
853
854 static void asm_branch_opcode(TCCState *s1, int token, int argc){
855 Operand ops[3];
856 Operand zero = {.type = OP_REG};
857 parse_operands(s1, &ops[0], argc-1);
858 if ( tok == ',') next(); else { expect(","); }
859 parse_branch_offset_operand(s1, &ops[argc-1]);
860
861 switch(token){
862 /* branch (RS1, RS2, IMM); B-format */
863 case TOK_ASM_beq:
864 asm_emit_b(token, 0x63 | (0 << 12), ops, ops + 1, ops + 2);
865 return;
866 case TOK_ASM_bne:
867 asm_emit_b(token, 0x63 | (1 << 12), ops, ops + 1, ops + 2);
868 return;
869 case TOK_ASM_blt:
870 asm_emit_b(token, 0x63 | (4 << 12), ops, ops + 1, ops + 2);
871 return;
872 case TOK_ASM_bge:
873 asm_emit_b(token, 0x63 | (5 << 12), ops, ops + 1, ops + 2);
874 return;
875 case TOK_ASM_bltu:
876 asm_emit_b(token, 0x63 | (6 << 12), ops, ops + 1, ops + 2);
877 return;
878 case TOK_ASM_bgeu:
879 asm_emit_b(token, 0x63 | (7 << 12), ops, ops + 1, ops + 2);
880 return;
881 /* related pseudoinstructions */
882 case TOK_ASM_bgt:
883 asm_emit_b(token, 0x63 | (4 << 12), ops + 1, ops, ops + 2);
884 return;
885 case TOK_ASM_ble:
886 asm_emit_b(token, 0x63 | (5 << 12), ops + 1, ops, ops + 2);
887 return;
888 case TOK_ASM_bgtu:
889 asm_emit_b(token, 0x63 | (6 << 12), ops + 1, ops, ops + 2);
890 return;
891 case TOK_ASM_bleu:
892 asm_emit_b(token, 0x63 | (7 << 12), ops + 1, ops, ops + 2);
893 return;
894 /* shorter pseudoinstructions */
895 case TOK_ASM_bnez:
896 /* bne rs, zero, offset */
897 asm_emit_b(token, 0x63 | (1 << 12), &ops[0], &zero, &ops[1]);
898 return;
899 case TOK_ASM_beqz:
900 /* bne rs, zero, offset */
901 asm_emit_b(token, 0x63 | (0 << 12), &ops[0], &zero, &ops[1]);
902 return;
903 case TOK_ASM_blez:
904 /* bge rs, zero, offset */
905 asm_emit_b(token, 0x63 | (5 << 12), &ops[0], &zero, &ops[1]);
906 return;
907 case TOK_ASM_bgez:
908 /* bge zero, rs, offset */
909 asm_emit_b(token, 0x63 | (5 << 12), &zero, &ops[0], &ops[1]);
910 return;
911 case TOK_ASM_bltz:
912 /* blt rs, zero, offset */
913 asm_emit_b(token, 0x63 | (4 << 12), &ops[0], &zero, &ops[1]);
914 return;
915 case TOK_ASM_bgtz:
916 /* blt zero, rs, offset */
917 asm_emit_b(token, 0x63 | (4 << 12), &zero, &ops[0], &ops[1]);
918 return;
919 }
920 }
921
922 static void asm_ternary_opcode(TCCState *s1, int token)
923 {
924 Operand ops[3];
925 parse_operands(s1, &ops[0], 3);
926
927 switch (token) {
928 case TOK_ASM_sll:
929 asm_emit_r(token, (0xC << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
930 return;
931 case TOK_ASM_slli:
932 asm_emit_i(token, (4 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
933 return;
934 case TOK_ASM_srl:
935 asm_emit_r(token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
936 return;
937 case TOK_ASM_srli:
938 asm_emit_i(token, (0x4 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
939 return;
940 case TOK_ASM_sra:
941 asm_emit_r(token, (0xC << 2) | 3 | (5 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]);
942 return;
943 case TOK_ASM_srai:
944 asm_emit_i(token, (0x4 << 2) | 3 | (5 << 12) | (16 << 26), &ops[0], &ops[1], &ops[2]);
945 return;
946 case TOK_ASM_sllw:
947 asm_emit_r(token, (0xE << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
948 return;
949 case TOK_ASM_slliw:
950 asm_emit_i(token, (6 << 2) | 3 | (1 << 12), &ops[0], &ops[1], &ops[2]);
951 return;
952 case TOK_ASM_srlw:
953 asm_emit_r(token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
954 return;
955 case TOK_ASM_srliw:
956 asm_emit_i(token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
957 return;
958 case TOK_ASM_sraw:
959 asm_emit_r(token, (0xE << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
960 return;
961 case TOK_ASM_sraiw:
962 asm_emit_i(token, (0x6 << 2) | 3 | (5 << 12), &ops[0], &ops[1], &ops[2]);
963 return;
964
965 // Arithmetic (RD,RS1,(RS2|IMM)); R-format, I-format or U-format
966
967 case TOK_ASM_add:
968 asm_emit_r(token, (0xC << 2) | 3, &ops[0], &ops[1], &ops[2]);
969 return;
970 case TOK_ASM_addi:
971 asm_emit_i(token, (4 << 2) | 3, &ops[0], &ops[1], &ops[2]);
972 return;
973 case TOK_ASM_sub:
974 asm_emit_r(token, (0xC << 2) | 3 | (32 << 25), &ops[0], &ops[1], &ops[2]);
975 return;
976 case TOK_ASM_addw:
977 asm_emit_r(token, (0xE << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]);
978 return;
979 case TOK_ASM_addiw: // 64 bit
980 asm_emit_i(token, (0x6 << 2) | 3 | (0 << 12), &ops[0], &ops[1], &ops[2]);
981 return;
982 case TOK_ASM_subw:
983 asm_emit_r(token, (0xE << 2) | 3 | (0 << 12) | (32 << 25), &ops[0], &ops[1], &ops[2]);
984 return;
985
986 // Logical (RD,RS1,(RS2|IMM)); R-format or I-format
987
988 case TOK_ASM_xor:
989 asm_emit_r(token, (0xC << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
990 return;
991 case TOK_ASM_xori:
992 asm_emit_i(token, (0x4 << 2) | 3 | (4 << 12), &ops[0], &ops[1], &ops[2]);
993 return;
994 case TOK_ASM_or:
995 asm_emit_r(token, (0xC << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]);
996 return;
997 case TOK_ASM_ori:
998 asm_emit_i(token, (0x4 << 2) | 3 | (6 << 12), &ops[0], &ops[1], &ops[2]);
999 return;
1000 case TOK_ASM_and:
1001 asm_emit_r(token, (0xC << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]);
1002 return;
1003 case TOK_ASM_andi:
1004 asm_emit_i(token, (0x4 << 2) | 3 | (7 << 12), &ops[0], &ops[1], &ops[2]);
1005 return;
1006
1007 // Compare (RD,RS1,(RS2|IMM)); R-format or I-format
1008
1009 case TOK_ASM_slt:
1010 asm_emit_r(token, (0xC << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]);
1011 return;
1012 case TOK_ASM_slti:
1013 asm_emit_i(token, (0x4 << 2) | 3 | (2 << 12), &ops[0], &ops[1], &ops[2]);
1014 return;
1015 case TOK_ASM_sltu:
1016 asm_emit_r(token, (0xC << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
1017 return;
1018 case TOK_ASM_sltiu:
1019 asm_emit_i(token, (0x4 << 2) | 3 | (3 << 12), &ops[0], &ops[1], &ops[2]);
1020 return;
1021
1022 /* M extension */
1023 case TOK_ASM_div:
1024 asm_emit_r(token, 0x33 | (4 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1025 return;
1026 case TOK_ASM_divu:
1027 asm_emit_r(token, 0x33 | (5 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1028 return;
1029 case TOK_ASM_divuw:
1030 asm_emit_r(token, 0x3b | (5 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1031 return;
1032 case TOK_ASM_divw:
1033 asm_emit_r(token, 0x3b | (4 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1034 return;
1035 case TOK_ASM_mul:
1036 asm_emit_r(token, 0x33 | (1 << 25), ops, ops + 1, ops + 2);
1037 return;
1038 case TOK_ASM_mulh:
1039 asm_emit_r(token, 0x33 | (1 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1040 return;
1041 case TOK_ASM_mulhsu:
1042 asm_emit_r(token, 0x33 | (2 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1043 return;
1044 case TOK_ASM_mulhu:
1045 asm_emit_r(token, 0x33 | (3 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1046 return;
1047 case TOK_ASM_mulw:
1048 asm_emit_r(token, 0x3b | (1 << 25), ops, ops + 1, ops + 2);
1049 return;
1050 case TOK_ASM_rem:
1051 asm_emit_r(token, 0x33 | (6 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1052 return;
1053 case TOK_ASM_remu:
1054 asm_emit_r(token, 0x33 | (7 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1055 return;
1056 case TOK_ASM_remuw:
1057 asm_emit_r(token, 0x3b | (7 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1058 return;
1059 case TOK_ASM_remw:
1060 asm_emit_r(token, 0x3b | (6 << 12) | (1 << 25), ops, ops + 1, ops + 2);
1061 return;
1062
1063 /* Zicsr extension; (rd, csr, rs/uimm) */
1064 case TOK_ASM_csrrc:
1065 asm_emit_i(token, 0x73 | (3 << 12), ops, ops + 2, ops + 1);
1066 return;
1067 case TOK_ASM_csrrci:
1068 /* using rs1 field for uimmm */
1069 ops[2].type = OP_REG;
1070 asm_emit_i(token, 0x73 | (7 << 12), ops, ops + 2, ops + 1);
1071 return;
1072 case TOK_ASM_csrrs:
1073 asm_emit_i(token, 0x73 | (2 << 12), ops, ops + 2, ops + 1);
1074 return;
1075 case TOK_ASM_csrrsi:
1076 ops[2].type = OP_REG;
1077 asm_emit_i(token, 0x73 | (6 << 12), ops, ops + 2, ops + 1);
1078 return;
1079 case TOK_ASM_csrrw:
1080 asm_emit_i(token, 0x73 | (1 << 12), ops, ops + 2, ops + 1);
1081 return;
1082 case TOK_ASM_csrrwi:
1083 ops[2].type = OP_REG;
1084 asm_emit_i(token, 0x73 | (5 << 12), ops, ops + 2, ops + 1);
1085 return;
1086
1087 /* C extension */
1088 /* register-based loads and stores (RD, RS1, IMM); CL-format */
1089 case TOK_ASM_c_fld:
1090 asm_emit_cl(token, 1 << 13, ops, ops + 1, ops + 2);
1091 return;
1092 case TOK_ASM_c_flw: /* RV32FC-only */
1093 asm_emit_cl(token, 3 << 13, ops, ops + 1, ops + 2);
1094 return;
1095 case TOK_ASM_c_fsd:
1096 asm_emit_cs(token, 5 << 13, ops, ops + 1, ops + 2);
1097 return;
1098 case TOK_ASM_c_fsw: /* RV32FC-only */
1099 asm_emit_cs(token, 7 << 13, ops, ops + 1, ops + 2);
1100 return;
1101 case TOK_ASM_c_ld:
1102 asm_emit_cl(token, 3 << 13, ops, ops + 1, ops + 2);
1103 return;
1104 case TOK_ASM_c_lw:
1105 asm_emit_cl(token, 2 << 13, ops, ops + 1, ops + 2);
1106 return;
1107 case TOK_ASM_c_sd:
1108 asm_emit_cs(token, 7 << 13, ops, ops + 1, ops + 2);
1109 return;
1110 case TOK_ASM_c_sw:
1111 asm_emit_cs(token, 6 << 13, ops, ops + 1, ops + 2);
1112 return;
1113
1114 default:
1115 expect("ternary instruction");
1116 }
1117 }
1118
1119 static void asm_atomic_opcode(TCCState *s1, int token)
1120 {
1121 static const Operand zero = {.type = OP_REG};
1122 Operand ops[3];
1123
1124 parse_operand(s1, &ops[0]);
1125 if ( tok == ',') next(); else expect("','");
1126
1127 if ( token <= TOK_ASM_lr_d_aqrl && token >= TOK_ASM_lr_w ) {
1128 ops[1] = zero;
1129 } else {
1130 parse_operand(s1, &ops[1]);
1131 if ( tok == ',') next(); else expect("','");
1132 }
1133
1134 if ( tok == '(') next(); else expect("'('");
1135 parse_operand(s1, &ops[2]);
1136 if ( tok == ')') next(); else expect("')'");
1137
1138 switch(token){
1139 case TOK_ASM_lr_w:
1140 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1141 break;
1142 case TOK_ASM_lr_w_aq:
1143 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1144 break;
1145 case TOK_ASM_lr_w_rl:
1146 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1147 break;
1148 case TOK_ASM_lr_w_aqrl:
1149 asm_emit_a(token, 0x2F | 0x2<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1150 break;
1151
1152 case TOK_ASM_lr_d:
1153 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1154 break;
1155 case TOK_ASM_lr_d_aq:
1156 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1157 break;
1158 case TOK_ASM_lr_d_rl:
1159 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1160 break;
1161 case TOK_ASM_lr_d_aqrl:
1162 asm_emit_a(token, 0x2F | 0x3<<12 | 0x2<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1163 break;
1164
1165 case TOK_ASM_sc_w:
1166 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1167 break;
1168 case TOK_ASM_sc_w_aq:
1169 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1170 break;
1171 case TOK_ASM_sc_w_rl:
1172 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1173 break;
1174 case TOK_ASM_sc_w_aqrl:
1175 asm_emit_a(token, 0x2F | 0x2<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1176 break;
1177
1178 case TOK_ASM_sc_d:
1179 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 0);
1180 break;
1181 case TOK_ASM_sc_d_aq:
1182 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 0);
1183 break;
1184 case TOK_ASM_sc_d_rl:
1185 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 0, 1);
1186 break;
1187 case TOK_ASM_sc_d_aqrl:
1188 asm_emit_a(token, 0x2F | 0x3<<12 | 0x3<<27, &ops[0], &ops[1], &ops[2], 1, 1);
1189 break;
1190 }
1191 }
1192
1193 /* caller: Add funct3 and func5 to opcode */
1194 static void asm_emit_a(int token, uint32_t opcode, const Operand *rd1, const Operand *rs2, const Operand *rs1, int aq, int rl)
1195 {
1196 if (rd1->type != OP_REG)
1197 tcc_error("'%s': Expected first destination operand that is a register", get_tok_str(token, NULL));
1198 if (rs2->type != OP_REG)
1199 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token, NULL));
1200 if (rs1->type != OP_REG)
1201 tcc_error("'%s': Expected third source operand that is a register", get_tok_str(token, NULL));
1202 /* A-type instruction:
1203 31...27 funct5
1204 26 aq
1205 25 rl
1206 24...20 rs2
1207 19...15 rs1
1208 14...11 funct3
1209 11...7 rd
1210 6...0 opcode
1211 opcode always fixed pos. */
1212 gen_le32(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ENCODE_RD(rd1->reg) | aq << 26 | rl << 25);
1213 }
1214
1215 /* caller: Add funct3 to opcode */
1216 static void asm_emit_s(int token, uint32_t opcode, const Operand* rs1, const Operand* rs2, const Operand* imm)
1217 {
1218 if (rs1->type != OP_REG) {
1219 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
1220 return;
1221 }
1222 if (rs2->type != OP_REG) {
1223 tcc_error("'%s': Expected second source operand that is a register", get_tok_str(token, NULL));
1224 return;
1225 }
1226 if (imm->type != OP_IM12S) {
1227 tcc_error("'%s': Expected third operand that is an immediate value between 0 and 8191", get_tok_str(token, NULL));
1228 return;
1229 }
1230 {
1231 uint16_t v = imm->e.v;
1232 /* S-type instruction:
1233 31...25 imm[11:5]
1234 24...20 rs2
1235 19...15 rs1
1236 14...12 funct3
1237 11...7 imm[4:0]
1238 6...0 opcode
1239 opcode always fixed pos. */
1240 gen_le32(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | ((v & 0x1F) << 7) | ((v >> 5) << 25));
1241 }
1242 }
1243
1244 static void asm_emit_b(int token, uint32_t opcode, const Operand *rs1, const Operand *rs2, const Operand *imm)
1245 {
1246 uint32_t offset;
1247
1248 if (rs1->type != OP_REG) {
1249 tcc_error("'%s': Expected first source operand that is a register", get_tok_str(token, NULL));
1250 return;
1251 }
1252 if (rs2->type != OP_REG) {
1253 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
1254 return;
1255 }
1256 if (imm->type != OP_IM12S) {
1257 tcc_error("'%s': Expected second source operand that is an immediate value between 0 and 8191", get_tok_str(token, NULL));
1258 return;
1259 }
1260
1261 offset = imm->e.v;
1262
1263 /* B-type instruction:
1264 31 imm[12]
1265 30...25 imm[10:5]
1266 24...20 rs2
1267 19...15 rs1
1268 14...12 funct3
1269 8...11 imm[4:1]
1270 7 imm[11]
1271 6...0 opcode */
1272 asm_emit_opcode(opcode | ENCODE_RS1(rs1->reg) | ENCODE_RS2(rs2->reg) | (((offset >> 1) & 0xF) << 8) | (((offset >> 5) & 0x1f) << 25) | (((offset >> 11) & 1) << 7) | (((offset >> 12) & 1) << 31));
1273 }
1274
1275 ST_FUNC void asm_opcode(TCCState *s1, int token)
1276 {
1277 switch (token) {
1278 case TOK_ASM_ebreak:
1279 case TOK_ASM_ecall:
1280 case TOK_ASM_fence_i:
1281 case TOK_ASM_hrts:
1282 case TOK_ASM_mrth:
1283 case TOK_ASM_mrts:
1284 case TOK_ASM_wfi:
1285 asm_nullary_opcode(s1, token);
1286 return;
1287
1288 case TOK_ASM_fence:
1289 asm_fence_opcode(s1, token);
1290 return;
1291
1292 case TOK_ASM_rdcycle:
1293 case TOK_ASM_rdcycleh:
1294 case TOK_ASM_rdtime:
1295 case TOK_ASM_rdtimeh:
1296 case TOK_ASM_rdinstret:
1297 case TOK_ASM_rdinstreth:
1298 asm_unary_opcode(s1, token);
1299 return;
1300
1301 case TOK_ASM_lui:
1302 case TOK_ASM_auipc:
1303 asm_binary_opcode(s1, token);
1304 return;
1305
1306 case TOK_ASM_lb:
1307 case TOK_ASM_lh:
1308 case TOK_ASM_lw:
1309 case TOK_ASM_ld:
1310 case TOK_ASM_lbu:
1311 case TOK_ASM_lhu:
1312 case TOK_ASM_lwu:
1313 case TOK_ASM_sb:
1314 case TOK_ASM_sh:
1315 case TOK_ASM_sw:
1316 case TOK_ASM_sd:
1317 asm_mem_access_opcode(s1, token);
1318 break;
1319
1320 case TOK_ASM_jalr:
1321 asm_jalr_opcode(s1, token); /* it can be a pseudo instruction too*/
1322 break;
1323 case TOK_ASM_j:
1324 asm_jal_opcode(s1, token); /* jal zero, offset*/
1325 return;
1326 case TOK_ASM_jal:
1327 asm_jal_opcode(s1, token); /* it can be a pseudo instruction too*/
1328 break;
1329
1330 case TOK_ASM_add:
1331 case TOK_ASM_addi:
1332 case TOK_ASM_addiw:
1333 case TOK_ASM_addw:
1334 case TOK_ASM_and:
1335 case TOK_ASM_andi:
1336 case TOK_ASM_or:
1337 case TOK_ASM_ori:
1338 case TOK_ASM_sll:
1339 case TOK_ASM_slli:
1340 case TOK_ASM_slliw:
1341 case TOK_ASM_sllw:
1342 case TOK_ASM_slt:
1343 case TOK_ASM_slti:
1344 case TOK_ASM_sltiu:
1345 case TOK_ASM_sltu:
1346 case TOK_ASM_sra:
1347 case TOK_ASM_srai:
1348 case TOK_ASM_sraiw:
1349 case TOK_ASM_sraw:
1350 case TOK_ASM_srl:
1351 case TOK_ASM_srli:
1352 case TOK_ASM_srliw:
1353 case TOK_ASM_srlw:
1354 case TOK_ASM_sub:
1355 case TOK_ASM_subw:
1356 case TOK_ASM_xor:
1357 case TOK_ASM_xori:
1358 /* M extension */
1359 case TOK_ASM_div:
1360 case TOK_ASM_divu:
1361 case TOK_ASM_divuw:
1362 case TOK_ASM_divw:
1363 case TOK_ASM_mul:
1364 case TOK_ASM_mulh:
1365 case TOK_ASM_mulhsu:
1366 case TOK_ASM_mulhu:
1367 case TOK_ASM_mulw:
1368 case TOK_ASM_rem:
1369 case TOK_ASM_remu:
1370 case TOK_ASM_remuw:
1371 case TOK_ASM_remw:
1372 /* Zicsr extension */
1373 case TOK_ASM_csrrc:
1374 case TOK_ASM_csrrci:
1375 case TOK_ASM_csrrs:
1376 case TOK_ASM_csrrsi:
1377 case TOK_ASM_csrrw:
1378 case TOK_ASM_csrrwi:
1379 asm_ternary_opcode(s1, token);
1380 return;
1381
1382 /* Branches */
1383 case TOK_ASM_beq:
1384 case TOK_ASM_bge:
1385 case TOK_ASM_bgeu:
1386 case TOK_ASM_blt:
1387 case TOK_ASM_bltu:
1388 case TOK_ASM_bne:
1389 asm_branch_opcode(s1, token, 3);
1390 break;
1391
1392 /* C extension */
1393 case TOK_ASM_c_ebreak:
1394 case TOK_ASM_c_nop:
1395 asm_nullary_opcode(s1, token);
1396 return;
1397
1398 case TOK_ASM_c_j:
1399 case TOK_ASM_c_jal:
1400 case TOK_ASM_c_jalr:
1401 case TOK_ASM_c_jr:
1402 asm_unary_opcode(s1, token);
1403 return;
1404
1405 case TOK_ASM_c_add:
1406 case TOK_ASM_c_addi16sp:
1407 case TOK_ASM_c_addi4spn:
1408 case TOK_ASM_c_addi:
1409 case TOK_ASM_c_addiw:
1410 case TOK_ASM_c_addw:
1411 case TOK_ASM_c_and:
1412 case TOK_ASM_c_andi:
1413 case TOK_ASM_c_beqz:
1414 case TOK_ASM_c_bnez:
1415 case TOK_ASM_c_fldsp:
1416 case TOK_ASM_c_flwsp:
1417 case TOK_ASM_c_fsdsp:
1418 case TOK_ASM_c_fswsp:
1419 case TOK_ASM_c_ldsp:
1420 case TOK_ASM_c_li:
1421 case TOK_ASM_c_lui:
1422 case TOK_ASM_c_lwsp:
1423 case TOK_ASM_c_mv:
1424 case TOK_ASM_c_or:
1425 case TOK_ASM_c_sdsp:
1426 case TOK_ASM_c_slli:
1427 case TOK_ASM_c_srai:
1428 case TOK_ASM_c_srli:
1429 case TOK_ASM_c_sub:
1430 case TOK_ASM_c_subw:
1431 case TOK_ASM_c_swsp:
1432 case TOK_ASM_c_xor:
1433 asm_binary_opcode(s1, token);
1434 return;
1435
1436 case TOK_ASM_c_fld:
1437 case TOK_ASM_c_flw:
1438 case TOK_ASM_c_fsd:
1439 case TOK_ASM_c_fsw:
1440 case TOK_ASM_c_ld:
1441 case TOK_ASM_c_lw:
1442 case TOK_ASM_c_sd:
1443 case TOK_ASM_c_sw:
1444 asm_ternary_opcode(s1, token);
1445 return;
1446
1447 /* pseudoinstructions */
1448 case TOK_ASM_nop:
1449 case TOK_ASM_ret:
1450 asm_nullary_opcode(s1, token);
1451 return;
1452
1453 case TOK_ASM_jr:
1454 case TOK_ASM_call:
1455 case TOK_ASM_tail:
1456 asm_unary_opcode(s1, token);
1457 return;
1458
1459 case TOK_ASM_la:
1460 case TOK_ASM_lla:
1461 case TOK_ASM_li:
1462 case TOK_ASM_jump:
1463 case TOK_ASM_seqz:
1464 case TOK_ASM_snez:
1465 case TOK_ASM_sltz:
1466 case TOK_ASM_sgtz:
1467 case TOK_ASM_mv:
1468 case TOK_ASM_not:
1469 case TOK_ASM_neg:
1470 case TOK_ASM_negw:
1471 asm_binary_opcode(s1, token);
1472 return;
1473
1474 case TOK_ASM_bnez:
1475 case TOK_ASM_beqz:
1476 case TOK_ASM_blez:
1477 case TOK_ASM_bgez:
1478 case TOK_ASM_bltz:
1479 case TOK_ASM_bgtz:
1480 asm_branch_opcode(s1, token, 2);
1481 return;
1482
1483 case TOK_ASM_bgt:
1484 case TOK_ASM_bgtu:
1485 case TOK_ASM_ble:
1486 case TOK_ASM_bleu:
1487 asm_branch_opcode(s1, token, 3);
1488 return;
1489
1490 /* Atomic operations */
1491 case TOK_ASM_lr_w:
1492 case TOK_ASM_lr_w_aq:
1493 case TOK_ASM_lr_w_rl:
1494 case TOK_ASM_lr_w_aqrl:
1495 case TOK_ASM_lr_d:
1496 case TOK_ASM_lr_d_aq:
1497 case TOK_ASM_lr_d_rl:
1498 case TOK_ASM_lr_d_aqrl:
1499 case TOK_ASM_sc_w:
1500 case TOK_ASM_sc_w_aq:
1501 case TOK_ASM_sc_w_rl:
1502 case TOK_ASM_sc_w_aqrl:
1503 case TOK_ASM_sc_d:
1504 case TOK_ASM_sc_d_aq:
1505 case TOK_ASM_sc_d_rl:
1506 case TOK_ASM_sc_d_aqrl:
1507 asm_atomic_opcode(s1, token);
1508 break;
1509
1510 default:
1511 expect("known instruction");
1512 }
1513 }
1514
1515 static int asm_parse_csrvar(int t)
1516 {
1517 switch (t) {
1518 case TOK_ASM_cycle:
1519 return 0xc00;
1520 case TOK_ASM_fcsr:
1521 return 3;
1522 case TOK_ASM_fflags:
1523 return 1;
1524 case TOK_ASM_frm:
1525 return 2;
1526 case TOK_ASM_instret:
1527 return 0xc02;
1528 case TOK_ASM_time:
1529 return 0xc01;
1530 case TOK_ASM_cycleh:
1531 return 0xc80;
1532 case TOK_ASM_instreth:
1533 return 0xc82;
1534 case TOK_ASM_timeh:
1535 return 0xc81;
1536 default:
1537 return -1;
1538 }
1539 }
1540
1541 ST_FUNC void subst_asm_operand(CString *add_str, SValue *sv, int modifier)
1542 {
1543 int r, reg, val;
1544 char buf[64];
1545
1546 r = sv->r;
1547 if ((r & VT_VALMASK) == VT_CONST) {
1548 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n' &&
1549 modifier != 'P') {
1550 //cstr_ccat(add_str, '#');
1551 }
1552 if (r & VT_SYM) {
1553 const char *name = get_tok_str(sv->sym->v, NULL);
1554 if (sv->sym->v >= SYM_FIRST_ANOM) {
1555 /* In case of anonymous symbols ("L.42", used
1556 for static data labels) we can't find them
1557 in the C symbol table when later looking up
1558 this name. So enter them now into the asm label
1559 list when we still know the symbol. */
1560 get_asm_sym(tok_alloc(name, strlen(name))->tok, sv->sym);
1561 }
1562 if (tcc_state->leading_underscore)
1563 cstr_ccat(add_str, '_');
1564 cstr_cat(add_str, name, -1);
1565 if ((uint32_t) sv->c.i == 0)
1566 goto no_offset;
1567 cstr_ccat(add_str, '+');
1568 }
1569 val = sv->c.i;
1570 if (modifier == 'n')
1571 val = -val;
1572 if (modifier == 'z' && sv->c.i == 0) {
1573 cstr_cat(add_str, "zero", -1);
1574 } else {
1575 snprintf(buf, sizeof(buf), "%d", (int) sv->c.i);
1576 cstr_cat(add_str, buf, -1);
1577 }
1578 no_offset:;
1579 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1580 snprintf(buf, sizeof(buf), "%d", (int) sv->c.i);
1581 cstr_cat(add_str, buf, -1);
1582 } else if (r & VT_LVAL) {
1583 reg = r & VT_VALMASK;
1584 if (reg >= VT_CONST)
1585 tcc_internal_error("");
1586 if ((sv->type.t & VT_BTYPE) == VT_FLOAT ||
1587 (sv->type.t & VT_BTYPE) == VT_DOUBLE) {
1588 /* floating point register */
1589 reg = TOK_ASM_f0 + reg;
1590 } else {
1591 /* general purpose register */
1592 reg = TOK_ASM_x0 + reg;
1593 }
1594 snprintf(buf, sizeof(buf), "%s", get_tok_str(reg, NULL));
1595 cstr_cat(add_str, buf, -1);
1596 } else {
1597 /* register case */
1598 reg = r & VT_VALMASK;
1599 if (reg >= VT_CONST)
1600 tcc_internal_error("");
1601 if ((sv->type.t & VT_BTYPE) == VT_FLOAT ||
1602 (sv->type.t & VT_BTYPE) == VT_DOUBLE) {
1603 /* floating point register */
1604 reg = TOK_ASM_f0 + reg;
1605 } else {
1606 /* general purpose register */
1607 reg = TOK_ASM_x0 + reg;
1608 }
1609 snprintf(buf, sizeof(buf), "%s", get_tok_str(reg, NULL));
1610 cstr_cat(add_str, buf, -1);
1611 }
1612 }
1613
1614 /* TCC does not use RISC-V register numbers internally, it uses 0-8 for
1615 * integers and 8-16 for floats instead */
1616 static int tcc_ireg(int r){
1617 return REG_VALUE(r) - 10;
1618 }
1619 static int tcc_freg(int r){
1620 return REG_VALUE(r) - 10 + 8;
1621 }
1622
1623 /* generate prolog and epilog code for asm statement */
1624 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1625 int nb_outputs, int is_output,
1626 uint8_t *clobber_regs,
1627 int out_reg)
1628 {
1629 uint8_t regs_allocated[NB_ASM_REGS];
1630 ASMOperand *op;
1631 int i, reg;
1632
1633 static const uint8_t reg_saved[] = {
1634 // General purpose regs
1635 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
1636 // Float regs
1637 40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59
1638 };
1639
1640 /* mark all used registers */
1641 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1642 for(i = 0; i < nb_operands; i++) {
1643 op = &operands[i];
1644 if (op->reg >= 0) {
1645 regs_allocated[op->reg] = 1;
1646 }
1647 }
1648
1649 if(!is_output) {
1650 /* generate reg save code */
1651 for(i = 0; i < sizeof(reg_saved)/sizeof(reg_saved[0]); i++) {
1652 reg = reg_saved[i];
1653 if (regs_allocated[reg]) {
1654 /* push */
1655 /* addi sp, sp, -offset */
1656 gen_le32((4 << 2) | 3 |
1657 ENCODE_RD(2) | ENCODE_RS1(2) | -8 << 20);
1658 if (REG_IS_FLOAT(reg)){
1659 /* fsd reg, offset(sp) */
1660 gen_le32( 0x27 | (3 << 12) |
1661 ENCODE_RS2(reg) | ENCODE_RS1(2) );
1662 } else {
1663 /* sd reg, offset(sp) */
1664 gen_le32((0x8 << 2) | 3 | (3 << 12) |
1665 ENCODE_RS2(reg) | ENCODE_RS1(2) );
1666 }
1667 }
1668 }
1669
1670 /* generate load code */
1671 for(i = 0; i < nb_operands; i++) {
1672 op = &operands[i];
1673 if (op->reg >= 0) {
1674 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1675 op->is_memory) {
1676 /* memory reference case (for both input and
1677 output cases) */
1678 SValue sv;
1679 sv = *op->vt;
1680 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL | VT_LVAL;
1681 sv.type.t = VT_PTR;
1682 load(tcc_ireg(op->reg), &sv);
1683 } else if (i >= nb_outputs || op->is_rw) {
1684 /* load value in register */
1685 if ((op->vt->type.t & VT_BTYPE) == VT_FLOAT ||
1686 (op->vt->type.t & VT_BTYPE) == VT_DOUBLE) {
1687 load(tcc_freg(op->reg), op->vt);
1688 } else {
1689 load(tcc_ireg(op->reg), op->vt);
1690 }
1691 if (op->is_llong) {
1692 tcc_error("long long not implemented");
1693 }
1694 }
1695 }
1696 }
1697 } else {
1698 /* generate save code */
1699 for(i = 0 ; i < nb_outputs; i++) {
1700 op = &operands[i];
1701 if (op->reg >= 0) {
1702 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1703 if (!op->is_memory) {
1704 SValue sv;
1705 sv = *op->vt;
1706 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1707 sv.type.t = VT_PTR;
1708 load(tcc_ireg(out_reg), &sv);
1709
1710 sv = *op->vt;
1711 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1712 store(tcc_ireg(op->reg), &sv);
1713 }
1714 } else {
1715 if ((op->vt->type.t & VT_BTYPE) == VT_FLOAT ||
1716 (op->vt->type.t & VT_BTYPE) == VT_DOUBLE) {
1717 store(tcc_freg(op->reg), op->vt);
1718 } else {
1719 store(tcc_ireg(op->reg), op->vt);
1720 }
1721 if (op->is_llong) {
1722 tcc_error("long long not implemented");
1723 }
1724 }
1725 }
1726 }
1727 /* generate reg restore code for floating point registers */
1728 for(i = sizeof(reg_saved)/sizeof(reg_saved[0]) - 1; i >= 0; i--) {
1729 reg = reg_saved[i];
1730 if (regs_allocated[reg]) {
1731 /* pop */
1732 if (REG_IS_FLOAT(reg)){
1733 /* fld reg, offset(sp) */
1734 gen_le32(7 | (3 << 12) |
1735 ENCODE_RD(reg) | ENCODE_RS1(2) | 0);
1736 } else {
1737 /* ld reg, offset(sp) */
1738 gen_le32(3 | (3 << 12) |
1739 ENCODE_RD(reg) | ENCODE_RS1(2) | 0);
1740 }
1741 /* addi sp, sp, offset */
1742 gen_le32((4 << 2) | 3 |
1743 ENCODE_RD(2) | ENCODE_RS1(2) | 8 << 20);
1744 }
1745 }
1746 }
1747 }
1748
1749 /* return the constraint priority (we allocate first the lowest
1750 numbered constraints) */
1751 static inline int constraint_priority(const char *str)
1752 {
1753 // TODO: How is this chosen??
1754 int priority, c, pr;
1755
1756 /* we take the lowest priority */
1757 priority = 0;
1758 for(;;) {
1759 c = *str;
1760 if (c == '\0')
1761 break;
1762 str++;
1763 switch(c) {
1764 case 'A': // address that is held in a general-purpose register.
1765 case 'S': // constraint that matches an absolute symbolic address.
1766 case 'f': // register [float]
1767 case 'r': // register [general]
1768 case 'p': // valid memory address for load,store [general]
1769 pr = 3;
1770 break;
1771 case 'I': // 12 bit signed immedate
1772 case 'i': // immediate integer operand, including symbolic constants [general]
1773 case 'm': // memory operand [general]
1774 case 'g': // general-purpose-register, memory, immediate integer [general]
1775 pr = 4;
1776 break;
1777 case 'v':
1778 tcc_error("unimp: vector constraints '%d'", c);
1779 pr = 0;
1780 break;
1781 default:
1782 tcc_error("unknown constraint '%d'", c);
1783 pr = 0;
1784 }
1785 if (pr > priority)
1786 priority = pr;
1787 }
1788 return priority;
1789 }
1790
1791 static const char *skip_constraint_modifiers(const char *p)
1792 {
1793 /* Constraint modifier:
1794 = Operand is written to by this instruction
1795 + Operand is both read and written to by this instruction
1796 % Instruction is commutative for this operand and the following operand.
1797
1798 Per-alternative constraint modifier:
1799 & Operand is clobbered before the instruction is done using the input operands
1800 */
1801 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1802 p++;
1803 return p;
1804 }
1805
1806 #define REG_OUT_MASK 0x01
1807 #define REG_IN_MASK 0x02
1808
1809 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1810
1811 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1812 int nb_operands, int nb_outputs,
1813 const uint8_t *clobber_regs,
1814 int *pout_reg)
1815 {
1816 /* TODO: Simple constraints
1817 whitespace ignored
1818 o memory operand that is offsetable
1819 V memory but not offsetable
1820 < memory operand with autodecrement addressing is allowed. Restrictions apply.
1821 > memory operand with autoincrement addressing is allowed. Restrictions apply.
1822 n immediate integer operand with a known numeric value
1823 E immediate floating operand (const_double) is allowed, but only if target=host
1824 F immediate floating operand (const_double or const_vector) is allowed
1825 s immediate integer operand whose value is not an explicit integer
1826 X any operand whatsoever
1827 0...9 (postfix); (can also be more than 1 digit number); an operand that matches the specified operand number is allowed
1828 */
1829
1830 /* TODO: RISCV constraints
1831 J The integer 0.
1832 K A 5-bit unsigned immediate for CSR access instructions.
1833 A An address that is held in a general-purpose register.
1834 S A constraint that matches an absolute symbolic address.
1835 vr A vector register (if available)..
1836 vd A vector register, excluding v0 (if available).
1837 vm A vector register, only v0 (if available).
1838 */
1839 ASMOperand *op;
1840 int sorted_op[MAX_ASM_OPERANDS];
1841 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1842 const char *str;
1843 uint8_t regs_allocated[NB_ASM_REGS];
1844
1845 /* init fields */
1846 for (i = 0; i < nb_operands; i++) {
1847 op = &operands[i];
1848 op->input_index = -1;
1849 op->ref_index = -1;
1850 op->reg = -1;
1851 op->is_memory = 0;
1852 op->is_rw = 0;
1853 }
1854 /* compute constraint priority and evaluate references to output
1855 constraints if input constraints */
1856 for (i = 0; i < nb_operands; i++) {
1857 op = &operands[i];
1858 str = op->constraint;
1859 str = skip_constraint_modifiers(str);
1860 if (isnum(*str) || *str == '[') {
1861 /* this is a reference to another constraint */
1862 k = find_constraint(operands, nb_operands, str, NULL);
1863 if ((unsigned) k >= i || i < nb_outputs)
1864 tcc_error("invalid reference in constraint %d ('%s')",
1865 i, str);
1866 op->ref_index = k;
1867 if (operands[k].input_index >= 0)
1868 tcc_error("cannot reference twice the same operand");
1869 operands[k].input_index = i;
1870 op->priority = 5;
1871 } else if ((op->vt->r & VT_VALMASK) == VT_LOCAL
1872 && op->vt->sym
1873 && (reg = op->vt->sym->r & VT_VALMASK) < VT_CONST) {
1874 op->priority = 1;
1875 op->reg = reg;
1876 } else {
1877 op->priority = constraint_priority(str);
1878 }
1879 }
1880
1881 /* sort operands according to their priority */
1882 for (i = 0; i < nb_operands; i++)
1883 sorted_op[i] = i;
1884 for (i = 0; i < nb_operands - 1; i++) {
1885 for (j = i + 1; j < nb_operands; j++) {
1886 p1 = operands[sorted_op[i]].priority;
1887 p2 = operands[sorted_op[j]].priority;
1888 if (p2 < p1) {
1889 tmp = sorted_op[i];
1890 sorted_op[i] = sorted_op[j];
1891 sorted_op[j] = tmp;
1892 }
1893 }
1894 }
1895
1896 for (i = 0; i < NB_ASM_REGS; i++) {
1897 if (clobber_regs[i])
1898 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1899 else
1900 regs_allocated[i] = 0;
1901 }
1902
1903 /* allocate registers and generate corresponding asm moves */
1904 for (i = 0; i < nb_operands; i++) {
1905 j = sorted_op[i];
1906 op = &operands[j];
1907 str = op->constraint;
1908 /* no need to allocate references */
1909 if (op->ref_index >= 0)
1910 continue;
1911 /* select if register is used for output, input or both */
1912 if (op->input_index >= 0) {
1913 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1914 } else if (j < nb_outputs) {
1915 reg_mask = REG_OUT_MASK;
1916 } else {
1917 reg_mask = REG_IN_MASK;
1918 }
1919 if (op->reg >= 0) {
1920 if (is_reg_allocated(op->reg))
1921 tcc_error
1922 ("asm regvar requests register that's taken already");
1923 reg = op->reg;
1924 }
1925 try_next:
1926 c = *str++;
1927 switch (c) {
1928 case '=': // Operand is written-to
1929 goto try_next;
1930 case '+': // Operand is both READ and written-to
1931 op->is_rw = 1;
1932 /* FALL THRU */
1933 case '&': // Operand is clobbered before the instruction is done using the input operands
1934 if (j >= nb_outputs)
1935 tcc_error("'%c' modifier can only be applied to outputs", c);
1936 reg_mask = REG_IN_MASK | REG_OUT_MASK;
1937 goto try_next;
1938 case 'r': // general-purpose register
1939 case 'p': // loadable/storable address
1940 /* any general register */
1941 /* From a0 to a7 */
1942 if ((reg = op->reg) >= 0)
1943 goto reg_found;
1944 else for (reg = 10; reg <= 18; reg++) {
1945 if (!is_reg_allocated(reg))
1946 goto reg_found;
1947 }
1948 goto try_next;
1949 reg_found:
1950 /* now we can reload in the register */
1951 op->is_llong = 0;
1952 op->reg = reg;
1953 regs_allocated[reg] |= reg_mask;
1954 break;
1955 case 'f': // floating pont register
1956 /* floating point register */
1957 /* From fa0 to fa7 */
1958 if ((reg = op->reg) >= 0)
1959 goto reg_found;
1960 else for (reg = 42; reg <= 50; reg++) {
1961 if (!is_reg_allocated(reg))
1962 goto reg_found;
1963 }
1964 goto try_next;
1965 case 'I': // I-Type 12 bit signed immediate
1966 case 'i': // immediate integer operand, including symbolic constants
1967 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1968 goto try_next;
1969 break;
1970 case 'm': // memory operand
1971 case 'g': // any register
1972 /* nothing special to do because the operand is already in
1973 memory, except if the pointer itself is stored in a
1974 memory variable (VT_LLOCAL case) */
1975 /* XXX: fix constant case */
1976 /* if it is a reference to a memory zone, it must lie
1977 in a register, so we reserve the register in the
1978 input registers and a load will be generated
1979 later */
1980 if (j < nb_outputs || c == 'm') {
1981 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1982 /* any general register: from a0 to a7 */
1983 for (reg = 10; reg <= 18; reg++) {
1984 if (!(regs_allocated[reg] & REG_IN_MASK))
1985 goto reg_found1;
1986 }
1987 goto try_next;
1988 reg_found1:
1989 /* now we can reload in the register */
1990 regs_allocated[reg] |= REG_IN_MASK;
1991 op->reg = reg;
1992 op->is_memory = 1;
1993 }
1994 }
1995 break;
1996 default:
1997 tcc_error("asm constraint %d ('%s') could not be satisfied",
1998 j, op->constraint);
1999 break;
2000 }
2001 /* if a reference is present for that operand, we assign it too */
2002 if (op->input_index >= 0) {
2003 operands[op->input_index].reg = op->reg;
2004 operands[op->input_index].is_llong = op->is_llong;
2005 }
2006 }
2007
2008 /* compute out_reg. It is used to store outputs registers to memory
2009 locations references by pointers (VT_LLOCAL case) */
2010 *pout_reg = -1;
2011 for (i = 0; i < nb_operands; i++) {
2012 op = &operands[i];
2013 if (op->reg >= 0 &&
2014 (op->vt->r & VT_VALMASK) == VT_LLOCAL && !op->is_memory) {
2015 if (REG_IS_FLOAT(op->reg)){
2016 /* From fa0 to fa7 */
2017 for (reg = 42; reg <= 50; reg++) {
2018 if (!(regs_allocated[reg] & REG_OUT_MASK))
2019 goto reg_found2;
2020 }
2021 } else {
2022 /* From a0 to a7 */
2023 for (reg = 10; reg <= 18; reg++) {
2024 if (!(regs_allocated[reg] & REG_OUT_MASK))
2025 goto reg_found2;
2026 }
2027 }
2028 tcc_error("could not find free output register for reloading");
2029 reg_found2:
2030 *pout_reg = reg;
2031 break;
2032 }
2033 }
2034
2035 /* print sorted constraints */
2036 #ifdef ASM_DEBUG
2037 for (i = 0; i < nb_operands; i++) {
2038 j = sorted_op[i];
2039 op = &operands[j];
2040 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
2041 j,
2042 op->id ? get_tok_str(op->id, NULL) : "",
2043 op->constraint, op->vt->r, op->reg);
2044 }
2045 if (*pout_reg >= 0)
2046 printf("out_reg=%d\n", *pout_reg);
2047 #endif
2048 }
2049
2050 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
2051 {
2052 int reg;
2053 TokenSym *ts;
2054
2055 if (!strcmp(str, "memory") ||
2056 !strcmp(str, "cc") ||
2057 !strcmp(str, "flags"))
2058 return;
2059 ts = tok_alloc(str, strlen(str));
2060 reg = asm_parse_regvar(ts->tok);
2061 if (reg == -1) {
2062 tcc_error("invalid clobber register '%s'", str);
2063 }
2064 clobber_regs[reg] = 1;
2065 }
2066
2067 ST_FUNC int asm_parse_regvar (int t)
2068 {
2069 /* PC register not implemented */
2070 if (t >= TOK_ASM_pc || t < TOK_ASM_x0)
2071 return -1;
2072
2073 if (t < TOK_ASM_f0)
2074 return t - TOK_ASM_x0;
2075
2076 if (t < TOK_ASM_zero)
2077 return t - TOK_ASM_f0 + 32; // Use higher 32 for floating point
2078
2079 /* ABI mnemonic */
2080 if (t < TOK_ASM_ft0)
2081 return t - TOK_ASM_zero;
2082
2083 return t - TOK_ASM_ft0 + 32; // Use higher 32 for floating point
2084 }
2085
2086 /*************************************************************/
2087 /* C extension */
2088
2089 /* caller: Add funct6, funct2 into opcode */
2090 static void asm_emit_ca(int token, uint16_t opcode, const Operand *rd, const Operand *rs2)
2091 {
2092 uint8_t dst, src;
2093
2094 if (rd->type != OP_REG) {
2095 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2096 return;
2097 }
2098
2099 if (rs2->type != OP_REG) {
2100 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2101 return;
2102 }
2103
2104 /* subtract index of x8 */
2105 dst = rd->reg - 8;
2106 src = rs2->reg - 8;
2107
2108 /* only registers {x,f}8 to {x,f}15 are valid (3-bit) */
2109 if (dst > 7) {
2110 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2111 return;
2112 }
2113
2114 if (src > 7) {
2115 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2116 return;
2117 }
2118
2119 /* CA-type instruction:
2120 15...10 funct6
2121 9...7 rd'/rs1'
2122 6..5 funct2
2123 4...2 rs2'
2124 1...0 opcode */
2125
2126 gen_le16(opcode | C_ENCODE_RS2(src) | C_ENCODE_RS1(dst));
2127 }
2128
2129 static void asm_emit_cb(int token, uint16_t opcode, const Operand *rs1, const Operand *imm)
2130 {
2131 uint32_t offset;
2132 uint8_t src;
2133
2134 if (rs1->type != OP_REG) {
2135 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2136 return;
2137 }
2138
2139 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2140 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2141 return;
2142 }
2143
2144 offset = imm->e.v;
2145
2146 if (offset & 1) {
2147 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token, NULL));
2148 return;
2149 }
2150
2151 src = rs1->reg - 8;
2152
2153 if (src > 7) {
2154 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2155 return;
2156 }
2157
2158 /* CB-type instruction:
2159 15...13 funct3
2160 12...10 offset
2161 9..7 rs1'
2162 6...2 offset
2163 1...0 opcode */
2164
2165 /* non-branch also using CB:
2166 15...13 funct3
2167 12 imm
2168 11..10 funct2
2169 9...7 rd'/rs1'
2170 6..2 imm
2171 1...0 opcode */
2172
2173 switch (token) {
2174 case TOK_ASM_c_beqz:
2175 case TOK_ASM_c_bnez:
2176 gen_le16(opcode | C_ENCODE_RS1(src) | ((NTH_BIT(offset, 5) | (((offset >> 1) & 3) << 1) | (((offset >> 6) & 3) << 3)) << 2) | ((((offset >> 3) & 3) | NTH_BIT(offset, 8)) << 10));
2177 return;
2178 default:
2179 gen_le16(opcode | C_ENCODE_RS1(src) | ((offset & 0x1f) << 2) | (NTH_BIT(offset, 5) << 12));
2180 return;
2181 }
2182 }
2183
2184 static void asm_emit_ci(int token, uint16_t opcode, const Operand *rd, const Operand *imm)
2185 {
2186 uint32_t immediate;
2187
2188 if (rd->type != OP_REG) {
2189 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2190 return;
2191 }
2192
2193 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2194 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2195 return;
2196 }
2197
2198 immediate = imm->e.v;
2199
2200 /* CI-type instruction:
2201 15...13 funct3
2202 12 imm
2203 11...7 rd/rs1
2204 6...2 imm
2205 1...0 opcode */
2206
2207 switch (token) {
2208 case TOK_ASM_c_addi:
2209 case TOK_ASM_c_addiw:
2210 case TOK_ASM_c_li:
2211 case TOK_ASM_c_slli:
2212 gen_le16(opcode | ((immediate & 0x1f) << 2) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 5) << 12));
2213 return;
2214 case TOK_ASM_c_addi16sp:
2215 gen_le16(opcode | NTH_BIT(immediate, 5) << 2 | (((immediate >> 7) & 3) << 3) | NTH_BIT(immediate, 6) << 5 | NTH_BIT(immediate, 4) << 6 | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 9) << 12));
2216 return;
2217 case TOK_ASM_c_lui:
2218 gen_le16(opcode | (((immediate >> 12) & 0x1f) << 2) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 17) << 12));
2219 return;
2220 case TOK_ASM_c_fldsp:
2221 case TOK_ASM_c_ldsp:
2222 gen_le16(opcode | (((immediate >> 6) & 7) << 2) | (((immediate >> 3) & 2) << 5) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 5) << 12));
2223 return;
2224 case TOK_ASM_c_flwsp:
2225 case TOK_ASM_c_lwsp:
2226 gen_le16(opcode | (((immediate >> 6) & 3) << 2) | (((immediate >> 2) & 7) << 4) | ENCODE_RD(rd->reg) | (NTH_BIT(immediate, 5) << 12));
2227 return;
2228 case TOK_ASM_c_nop:
2229 gen_le16(opcode);
2230 return;
2231 default:
2232 expect("known instruction");
2233 }
2234 }
2235
2236 /* caller: Add funct3 into opcode */
2237 static void asm_emit_ciw(int token, uint16_t opcode, const Operand *rd, const Operand *imm)
2238 {
2239 uint32_t nzuimm;
2240 uint8_t dst;
2241
2242 if (rd->type != OP_REG) {
2243 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2244 return;
2245 }
2246
2247 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2248 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2249 return;
2250 }
2251
2252 dst = rd->reg - 8;
2253
2254 if (dst > 7) {
2255 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2256 return;
2257 }
2258
2259 nzuimm = imm->e.v;
2260
2261 if (nzuimm > 0x3fc) {
2262 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0x3ff", get_tok_str(token, NULL));
2263 return;
2264 }
2265
2266 if (nzuimm & 3) {
2267 tcc_error("'%s': Expected source operand that is a non-zero immediate value divisible by 4", get_tok_str(token, NULL));
2268 return;
2269 }
2270
2271 /* CIW-type instruction:
2272 15...13 funct3
2273 12...5 imm
2274 4...2 rd'
2275 1...0 opcode */
2276
2277 gen_le16(opcode | ENCODE_RS2(rd->reg) | ((NTH_BIT(nzuimm, 3) | (NTH_BIT(nzuimm, 2) << 1) | (((nzuimm >> 6) & 0xf) << 2) | (((nzuimm >> 4) & 3) << 6)) << 5));
2278 }
2279
2280 /* caller: Add funct3 into opcode */
2281 static void asm_emit_cj(int token, uint16_t opcode, const Operand *imm)
2282 {
2283 uint32_t offset;
2284
2285 /* +-2 KiB range */
2286 if (imm->type != OP_IM12S) {
2287 tcc_error("'%s': Expected source operand that is a 12-bit immediate value", get_tok_str(token, NULL));
2288 return;
2289 }
2290
2291 offset = imm->e.v;
2292
2293 if (offset & 1) {
2294 tcc_error("'%s': Expected source operand that is an even immediate value", get_tok_str(token, NULL));
2295 return;
2296 }
2297
2298 /* CJ-type instruction:
2299 15...13 funct3
2300 12...2 offset[11|4|9:8|10|6|7|3:1|5]
2301 1...0 opcode */
2302
2303 gen_le16(opcode | (NTH_BIT(offset, 5) << 2) | (((offset >> 1) & 7) << 3) | (NTH_BIT(offset, 7) << 6) | (NTH_BIT(offset, 6) << 7) | (NTH_BIT(offset, 10) << 8) | (((offset >> 8) & 3) << 9) | (NTH_BIT(offset, 4) << 11) | (NTH_BIT(offset, 11) << 12));
2304 }
2305
2306 /* caller: Add funct3 into opcode */
2307 static void asm_emit_cl(int token, uint16_t opcode, const Operand *rd, const Operand *rs1, const Operand *imm)
2308 {
2309 uint32_t offset;
2310 uint8_t dst, src;
2311
2312 if (rd->type != OP_REG) {
2313 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2314 return;
2315 }
2316
2317 if (rs1->type != OP_REG) {
2318 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2319 return;
2320 }
2321
2322 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2323 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2324 return;
2325 }
2326
2327 dst = rd->reg - 8;
2328 src = rs1->reg - 8;
2329
2330 if (dst > 7) {
2331 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2332 return;
2333 }
2334
2335 if (src > 7) {
2336 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2337 return;
2338 }
2339
2340 offset = imm->e.v;
2341
2342 if (offset > 0xff) {
2343 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token, NULL));
2344 return;
2345 }
2346
2347 if (offset & 3) {
2348 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token, NULL));
2349 return;
2350 }
2351
2352 /* CL-type instruction:
2353 15...13 funct3
2354 12...10 imm
2355 9...7 rs1'
2356 6...5 imm
2357 4...2 rd'
2358 1...0 opcode */
2359
2360 switch (token) {
2361 /* imm variant 1 */
2362 case TOK_ASM_c_flw:
2363 case TOK_ASM_c_lw:
2364 gen_le16(opcode | C_ENCODE_RS2(dst) | C_ENCODE_RS1(src) | (NTH_BIT(offset, 6) << 5) | (NTH_BIT(offset, 2) << 6) | (((offset >> 3) & 7) << 10));
2365 return;
2366 /* imm variant 2 */
2367 case TOK_ASM_c_fld:
2368 case TOK_ASM_c_ld:
2369 gen_le16(opcode | C_ENCODE_RS2(dst) | C_ENCODE_RS1(src) | (((offset >> 6) & 3) << 5) | (((offset >> 3) & 7) << 10));
2370 return;
2371 default:
2372 expect("known instruction");
2373 }
2374 }
2375
2376 /* caller: Add funct4 into opcode */
2377 static void asm_emit_cr(int token, uint16_t opcode, const Operand *rd, const Operand *rs2)
2378 {
2379 if (rd->type != OP_REG) {
2380 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2381 return;
2382 }
2383
2384 if (rs2->type != OP_REG) {
2385 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2386 return;
2387 }
2388
2389 /* CR-type instruction:
2390 15...12 funct4
2391 11..7 rd/rs1
2392 6...2 rs2
2393 1...0 opcode */
2394
2395 gen_le16(opcode | C_ENCODE_RS1(rd->reg) | C_ENCODE_RS2(rs2->reg));
2396 }
2397
2398 /* caller: Add funct3 into opcode */
2399 static void asm_emit_cs(int token, uint16_t opcode, const Operand *rs2, const Operand *rs1, const Operand *imm)
2400 {
2401 uint32_t offset;
2402 uint8_t base, src;
2403
2404 if (rs2->type != OP_REG) {
2405 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2406 return;
2407 }
2408
2409 if (rs1->type != OP_REG) {
2410 tcc_error("'%s': Expected source operand that is a register", get_tok_str(token, NULL));
2411 return;
2412 }
2413
2414 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2415 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2416 return;
2417 }
2418
2419 base = rs1->reg - 8;
2420 src = rs2->reg - 8;
2421
2422 if (base > 7) {
2423 tcc_error("'%s': Expected destination operand that is a valid C-extension register", get_tok_str(token, NULL));
2424 return;
2425 }
2426
2427 if (src > 7) {
2428 tcc_error("'%s': Expected source operand that is a valid C-extension register", get_tok_str(token, NULL));
2429 return;
2430 }
2431
2432 offset = imm->e.v;
2433
2434 if (offset > 0xff) {
2435 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token, NULL));
2436 return;
2437 }
2438
2439 if (offset & 3) {
2440 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token, NULL));
2441 return;
2442 }
2443
2444 /* CS-type instruction:
2445 15...13 funct3
2446 12...10 imm
2447 9...7 rs1'
2448 6...5 imm
2449 4...2 rs2'
2450 1...0 opcode */
2451 switch (token) {
2452 /* imm variant 1 */
2453 case TOK_ASM_c_fsw:
2454 case TOK_ASM_c_sw:
2455 gen_le16(opcode | C_ENCODE_RS2(base) | C_ENCODE_RS1(src) | (NTH_BIT(offset, 6) << 5) | (NTH_BIT(offset, 2) << 6) | (((offset >> 3) & 7) << 10));
2456 return;
2457 /* imm variant 2 */
2458 case TOK_ASM_c_fsd:
2459 case TOK_ASM_c_sd:
2460 gen_le16(opcode | C_ENCODE_RS2(base) | C_ENCODE_RS1(src) | (((offset >> 6) & 3) << 5) | (((offset >> 3) & 7) << 10));
2461 return;
2462 default:
2463 expect("known instruction");
2464 }
2465 }
2466
2467 /* caller: Add funct3 into opcode */
2468 static void asm_emit_css(int token, uint16_t opcode, const Operand *rs2, const Operand *imm)
2469 {
2470 uint32_t offset;
2471
2472 if (rs2->type != OP_REG) {
2473 tcc_error("'%s': Expected destination operand that is a register", get_tok_str(token, NULL));
2474 return;
2475 }
2476
2477 if (imm->type != OP_IM12S && imm->type != OP_IM32) {
2478 tcc_error("'%s': Expected source operand that is an immediate value", get_tok_str(token, NULL));
2479 return;
2480 }
2481
2482 offset = imm->e.v;
2483
2484 if (offset > 0xff) {
2485 tcc_error("'%s': Expected source operand that is an immediate value between 0 and 0xff", get_tok_str(token, NULL));
2486 return;
2487 }
2488
2489 if (offset & 3) {
2490 tcc_error("'%s': Expected source operand that is an immediate value divisible by 4", get_tok_str(token, NULL));
2491 return;
2492 }
2493
2494 /* CSS-type instruction:
2495 15...13 funct3
2496 12...7 imm
2497 6...2 rs2
2498 1...0 opcode */
2499
2500 switch (token) {
2501 /* imm variant 1 */
2502 case TOK_ASM_c_fswsp:
2503 case TOK_ASM_c_swsp:
2504 gen_le16(opcode | ENCODE_RS2(rs2->reg) | (((offset >> 6) & 3) << 7) | (((offset >> 2) & 0xf) << 9));
2505 return;
2506 /* imm variant 2 */
2507 case TOK_ASM_c_fsdsp:
2508 case TOK_ASM_c_sdsp:
2509 gen_le16(opcode | ENCODE_RS2(rs2->reg) | (((offset >> 6) & 7) << 7) | (((offset >> 3) & 7) << 10));
2510 return;
2511 default:
2512 expect("known instruction");
2513 }
2514 }
2515
2516 /*************************************************************/
2517 #endif /* ndef TARGET_DEFS_ONLY */
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