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Import 409,410: ARM EABI by Daniel Glöckner
[tinycc.git] / i386-asm.c
blob3d65c009d5d5319103440fa2618474e243cdfadc
1 /*
2 * i386 specific functions for TCC assembler
3 *
4 * Copyright (c) 2001, 2002 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21 #define MAX_OPERANDS 3
22
23 typedef struct ASMInstr {
24 uint16_t sym;
25 uint16_t opcode;
26 uint16_t instr_type;
27 #define OPC_JMP 0x01 /* jmp operand */
28 #define OPC_B 0x02 /* only used zith OPC_WL */
29 #define OPC_WL 0x04 /* accepts w, l or no suffix */
30 #define OPC_BWL (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
31 #define OPC_REG 0x08 /* register is added to opcode */
32 #define OPC_MODRM 0x10 /* modrm encoding */
33 #define OPC_FWAIT 0x20 /* add fwait opcode */
34 #define OPC_TEST 0x40 /* test opcodes */
35 #define OPC_SHIFT 0x80 /* shift opcodes */
36 #define OPC_D16 0x0100 /* generate data16 prefix */
37 #define OPC_ARITH 0x0200 /* arithmetic opcodes */
38 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
39 #define OPC_FARITH 0x0800 /* FPU arithmetic opcodes */
40 #define OPC_GROUP_SHIFT 13
41
42 /* in order to compress the operand type, we use specific operands and
43 we or only with EA */
44 #define OPT_REG8 0 /* warning: value is hardcoded from TOK_ASM_xxx */
45 #define OPT_REG16 1 /* warning: value is hardcoded from TOK_ASM_xxx */
46 #define OPT_REG32 2 /* warning: value is hardcoded from TOK_ASM_xxx */
47 #define OPT_MMX 3 /* warning: value is hardcoded from TOK_ASM_xxx */
48 #define OPT_SSE 4 /* warning: value is hardcoded from TOK_ASM_xxx */
49 #define OPT_CR 5 /* warning: value is hardcoded from TOK_ASM_xxx */
50 #define OPT_TR 6 /* warning: value is hardcoded from TOK_ASM_xxx */
51 #define OPT_DB 7 /* warning: value is hardcoded from TOK_ASM_xxx */
52 #define OPT_SEG 8
53 #define OPT_ST 9
54 #define OPT_IM8 10
55 #define OPT_IM8S 11
56 #define OPT_IM16 12
57 #define OPT_IM32 13
58 #define OPT_EAX 14 /* %al, %ax or %eax register */
59 #define OPT_ST0 15 /* %st(0) register */
60 #define OPT_CL 16 /* %cl register */
61 #define OPT_DX 17 /* %dx register */
62 #define OPT_ADDR 18 /* OP_EA with only offset */
63 #define OPT_INDIR 19 /* *(expr) */
64
65 /* composite types */
66 #define OPT_COMPOSITE_FIRST 20
67 #define OPT_IM 20 /* IM8 | IM16 | IM32 */
68 #define OPT_REG 21 /* REG8 | REG16 | REG32 */
69 #define OPT_REGW 22 /* REG16 | REG32 */
70 #define OPT_IMW 23 /* IM16 | IM32 */
71
72 /* can be ored with any OPT_xxx */
73 #define OPT_EA 0x80
74
75 uint8_t nb_ops;
76 uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
77 } ASMInstr;
78
79 typedef struct Operand {
80 uint32_t type;
81 #define OP_REG8 (1 << OPT_REG8)
82 #define OP_REG16 (1 << OPT_REG16)
83 #define OP_REG32 (1 << OPT_REG32)
84 #define OP_MMX (1 << OPT_MMX)
85 #define OP_SSE (1 << OPT_SSE)
86 #define OP_CR (1 << OPT_CR)
87 #define OP_TR (1 << OPT_TR)
88 #define OP_DB (1 << OPT_DB)
89 #define OP_SEG (1 << OPT_SEG)
90 #define OP_ST (1 << OPT_ST)
91 #define OP_IM8 (1 << OPT_IM8)
92 #define OP_IM8S (1 << OPT_IM8S)
93 #define OP_IM16 (1 << OPT_IM16)
94 #define OP_IM32 (1 << OPT_IM32)
95 #define OP_EAX (1 << OPT_EAX)
96 #define OP_ST0 (1 << OPT_ST0)
97 #define OP_CL (1 << OPT_CL)
98 #define OP_DX (1 << OPT_DX)
99 #define OP_ADDR (1 << OPT_ADDR)
100 #define OP_INDIR (1 << OPT_INDIR)
101
102 #define OP_EA 0x40000000
103 #define OP_REG (OP_REG8 | OP_REG16 | OP_REG32)
104 #define OP_IM OP_IM32
105 int8_t reg; /* register, -1 if none */
106 int8_t reg2; /* second register, -1 if none */
107 uint8_t shift;
108 ExprValue e;
109 } Operand;
110
111 static const uint8_t reg_to_size[5] = {
112 [OP_REG8] = 0,
113 [OP_REG16] = 1,
114 [OP_REG32] = 2,
115 };
116
117 #define WORD_PREFIX_OPCODE 0x66
118
119 #define NB_TEST_OPCODES 30
120
121 static const uint8_t test_bits[NB_TEST_OPCODES] = {
122 0x00, /* o */
123 0x01, /* no */
124 0x02, /* b */
125 0x02, /* c */
126 0x02, /* nae */
127 0x03, /* nb */
128 0x03, /* nc */
129 0x03, /* ae */
130 0x04, /* e */
131 0x04, /* z */
132 0x05, /* ne */
133 0x05, /* nz */
134 0x06, /* be */
135 0x06, /* na */
136 0x07, /* nbe */
137 0x07, /* a */
138 0x08, /* s */
139 0x09, /* ns */
140 0x0a, /* p */
141 0x0a, /* pe */
142 0x0b, /* np */
143 0x0b, /* po */
144 0x0c, /* l */
145 0x0c, /* nge */
146 0x0d, /* nl */
147 0x0d, /* ge */
148 0x0e, /* le */
149 0x0e, /* ng */
150 0x0f, /* nle */
151 0x0f, /* g */
152 };
153
154 static const uint8_t segment_prefixes[] = {
155 0x26, /* es */
156 0x2e, /* cs */
157 0x36, /* ss */
158 0x3e, /* ds */
159 0x64, /* fs */
160 0x65 /* gs */
161 };
162
163 static const ASMInstr asm_instrs[] = {
164 #define ALT(x) x
165 #define DEF_ASM_OP0(name, opcode)
166 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
167 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
168 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
169 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
170 #include "i386-asm.h"
171
172 /* last operation */
173 { 0, },
174 };
175
176 static const uint16_t op0_codes[] = {
177 #define ALT(x)
178 #define DEF_ASM_OP0(x, opcode) opcode,
179 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
180 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
181 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
182 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
183 #include "i386-asm.h"
184 };
185
186 static inline int get_reg_shift(TCCState *s1)
187 {
188 int shift, v;
189
190 v = asm_int_expr(s1);
191 switch(v) {
192 case 1:
193 shift = 0;
194 break;
195 case 2:
196 shift = 1;
197 break;
198 case 4:
199 shift = 2;
200 break;
201 case 8:
202 shift = 3;
203 break;
204 default:
205 expect("1, 2, 4 or 8 constant");
206 shift = 0;
207 break;
208 }
209 return shift;
210 }
211
212 static int asm_parse_reg(void)
213 {
214 int reg;
215 if (tok != '%')
216 goto error_32;
217 next();
218 if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
219 reg = tok - TOK_ASM_eax;
220 next();
221 return reg;
222 } else {
223 error_32:
224 expect("32 bit register");
225 return 0;
226 }
227 }
228
229 static void parse_operand(TCCState *s1, Operand *op)
230 {
231 ExprValue e;
232 int reg, indir;
233 const char *p;
234
235 indir = 0;
236 if (tok == '*') {
237 next();
238 indir = OP_INDIR;
239 }
240
241 if (tok == '%') {
242 next();
243 if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
244 reg = tok - TOK_ASM_al;
245 op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
246 op->reg = reg & 7;
247 if ((op->type & OP_REG) && op->reg == TREG_EAX)
248 op->type |= OP_EAX;
249 else if (op->type == OP_REG8 && op->reg == TREG_ECX)
250 op->type |= OP_CL;
251 else if (op->type == OP_REG16 && op->reg == TREG_EDX)
252 op->type |= OP_DX;
253 } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
254 op->type = OP_DB;
255 op->reg = tok - TOK_ASM_dr0;
256 } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
257 op->type = OP_SEG;
258 op->reg = tok - TOK_ASM_es;
259 } else if (tok == TOK_ASM_st) {
260 op->type = OP_ST;
261 op->reg = 0;
262 next();
263 if (tok == '(') {
264 next();
265 if (tok != TOK_PPNUM)
266 goto reg_error;
267 p = tokc.cstr->data;
268 reg = p[0] - '0';
269 if ((unsigned)reg >= 8 || p[1] != '\0')
270 goto reg_error;
271 op->reg = reg;
272 next();
273 skip(')');
274 }
275 if (op->reg == 0)
276 op->type |= OP_ST0;
277 goto no_skip;
278 } else {
279 reg_error:
280 error("unknown register");
281 }
282 next();
283 no_skip: ;
284 } else if (tok == '$') {
285 /* constant value */
286 next();
287 asm_expr(s1, &e);
288 op->type = OP_IM32;
289 op->e.v = e.v;
290 op->e.sym = e.sym;
291 if (!op->e.sym) {
292 if (op->e.v == (uint8_t)op->e.v)
293 op->type |= OP_IM8;
294 if (op->e.v == (int8_t)op->e.v)
295 op->type |= OP_IM8S;
296 if (op->e.v == (uint16_t)op->e.v)
297 op->type |= OP_IM16;
298 }
299 } else {
300 /* address(reg,reg2,shift) with all variants */
301 op->type = OP_EA;
302 op->reg = -1;
303 op->reg2 = -1;
304 op->shift = 0;
305 if (tok != '(') {
306 asm_expr(s1, &e);
307 op->e.v = e.v;
308 op->e.sym = e.sym;
309 } else {
310 op->e.v = 0;
311 op->e.sym = NULL;
312 }
313 if (tok == '(') {
314 next();
315 if (tok != ',') {
316 op->reg = asm_parse_reg();
317 }
318 if (tok == ',') {
319 next();
320 if (tok != ',') {
321 op->reg2 = asm_parse_reg();
322 }
323 if (tok == ',') {
324 next();
325 op->shift = get_reg_shift(s1);
326 }
327 }
328 skip(')');
329 }
330 if (op->reg == -1 && op->reg2 == -1)
331 op->type |= OP_ADDR;
332 }
333 op->type |= indir;
334 }
335
336 /* XXX: unify with C code output ? */
337 static void gen_expr32(ExprValue *pe)
338 {
339 if (pe->sym)
340 greloc(cur_text_section, pe->sym, ind, R_386_32);
341 gen_le32(pe->v);
342 }
343
344 /* XXX: unify with C code output ? */
345 static void gen_disp32(ExprValue *pe)
346 {
347 Sym *sym;
348 sym = pe->sym;
349 if (sym) {
350 if (sym->r == cur_text_section->sh_num) {
351 /* same section: we can output an absolute value. Note
352 that the TCC compiler behaves differently here because
353 it always outputs a relocation to ease (future) code
354 elimination in the linker */
355 gen_le32(pe->v + (long)sym->next - ind - 4);
356 } else {
357 greloc(cur_text_section, sym, ind, R_386_PC32);
358 gen_le32(pe->v - 4);
359 }
360 } else {
361 /* put an empty PC32 relocation */
362 put_elf_reloc(symtab_section, cur_text_section,
363 ind, R_386_PC32, 0);
364 gen_le32(pe->v - 4);
365 }
366 }
367
368
369 static void gen_le16(int v)
370 {
371 g(v);
372 g(v >> 8);
373 }
374
375 /* generate the modrm operand */
376 static inline void asm_modrm(int reg, Operand *op)
377 {
378 int mod, reg1, reg2, sib_reg1;
379
380 if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
381 g(0xc0 + (reg << 3) + op->reg);
382 } else if (op->reg == -1 && op->reg2 == -1) {
383 /* displacement only */
384 g(0x05 + (reg << 3));
385 gen_expr32(&op->e);
386 } else {
387 sib_reg1 = op->reg;
388 /* fist compute displacement encoding */
389 if (sib_reg1 == -1) {
390 sib_reg1 = 5;
391 mod = 0x00;
392 } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
393 mod = 0x00;
394 } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
395 mod = 0x40;
396 } else {
397 mod = 0x80;
398 }
399 /* compute if sib byte needed */
400 reg1 = op->reg;
401 if (op->reg2 != -1)
402 reg1 = 4;
403 g(mod + (reg << 3) + reg1);
404 if (reg1 == 4) {
405 /* add sib byte */
406 reg2 = op->reg2;
407 if (reg2 == -1)
408 reg2 = 4; /* indicate no index */
409 g((op->shift << 6) + (reg2 << 3) + sib_reg1);
410 }
411
412 /* add offset */
413 if (mod == 0x40) {
414 g(op->e.v);
415 } else if (mod == 0x80 || op->reg == -1) {
416 gen_expr32(&op->e);
417 }
418 }
419 }
420
421 static void asm_opcode(TCCState *s1, int opcode)
422 {
423 const ASMInstr *pa;
424 int i, modrm_index, reg, v, op1, is_short_jmp, has_seg_prefix;
425 int nb_ops, s, ss;
426 Operand ops[MAX_OPERANDS], *pop, seg_prefix;
427 int op_type[3]; /* decoded op type */
428
429 /* get operands */
430 pop = ops;
431 nb_ops = 0;
432 has_seg_prefix = 0;
433 for(;;) {
434 if (tok == ';' || tok == TOK_LINEFEED)
435 break;
436 if (nb_ops >= MAX_OPERANDS) {
437 error("incorrect number of operands");
438 }
439 parse_operand(s1, pop);
440 if (tok == ':') {
441 if (pop->type != OP_SEG || has_seg_prefix) {
442 error("incorrect prefix");
443 }
444 seg_prefix = *pop;
445 has_seg_prefix = 1;
446 next();
447 parse_operand(s1, pop);
448 if (!(pop->type & OP_EA)) {
449 error("segment prefix must be followed by memory reference");
450 }
451 }
452 pop++;
453 nb_ops++;
454 if (tok != ',')
455 break;
456 next();
457 }
458
459 is_short_jmp = 0;
460 s = 0; /* avoid warning */
461
462 /* optimize matching by using a lookup table (no hashing is needed
463 !) */
464 for(pa = asm_instrs; pa->sym != 0; pa++) {
465 s = 0;
466 if (pa->instr_type & OPC_FARITH) {
467 v = opcode - pa->sym;
468 if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
469 continue;
470 } else if (pa->instr_type & OPC_ARITH) {
471 if (!(opcode >= pa->sym && opcode < pa->sym + 8 * 4))
472 continue;
473 goto compute_size;
474 } else if (pa->instr_type & OPC_SHIFT) {
475 if (!(opcode >= pa->sym && opcode < pa->sym + 7 * 4))
476 continue;
477 goto compute_size;
478 } else if (pa->instr_type & OPC_TEST) {
479 if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
480 continue;
481 } else if (pa->instr_type & OPC_B) {
482 if (!(opcode >= pa->sym && opcode <= pa->sym + 3))
483 continue;
484 compute_size:
485 s = (opcode - pa->sym) & 3;
486 } else if (pa->instr_type & OPC_WL) {
487 if (!(opcode >= pa->sym && opcode <= pa->sym + 2))
488 continue;
489 s = opcode - pa->sym + 1;
490 } else {
491 if (pa->sym != opcode)
492 continue;
493 }
494 if (pa->nb_ops != nb_ops)
495 continue;
496 /* now decode and check each operand */
497 for(i = 0; i < nb_ops; i++) {
498 int op1, op2;
499 op1 = pa->op_type[i];
500 op2 = op1 & 0x1f;
501 switch(op2) {
502 case OPT_IM:
503 v = OP_IM8 | OP_IM16 | OP_IM32;
504 break;
505 case OPT_REG:
506 v = OP_REG8 | OP_REG16 | OP_REG32;
507 break;
508 case OPT_REGW:
509 v = OP_REG16 | OP_REG32;
510 break;
511 case OPT_IMW:
512 v = OP_IM16 | OP_IM32;
513 break;
514 default:
515 v = 1 << op2;
516 break;
517 }
518 if (op1 & OPT_EA)
519 v |= OP_EA;
520 op_type[i] = v;
521 if ((ops[i].type & v) == 0)
522 goto next;
523 }
524 /* all is matching ! */
525 break;
526 next: ;
527 }
528 if (pa->sym == 0) {
529 if (opcode >= TOK_ASM_pusha && opcode <= TOK_ASM_emms) {
530 int b;
531 b = op0_codes[opcode - TOK_ASM_pusha];
532 if (b & 0xff00)
533 g(b >> 8);
534 g(b);
535 return;
536 } else {
537 error("unknown opcode '%s'",
538 get_tok_str(opcode, NULL));
539 }
540 }
541 /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
542 if (s == 3) {
543 for(i = 0; s == 3 && i < nb_ops; i++) {
544 if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
545 s = reg_to_size[ops[i].type & OP_REG];
546 }
547 if (s == 3) {
548 if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
549 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32)))
550 s = 2;
551 else
552 error("cannot infer opcode suffix");
553 }
554 }
555
556 /* generate data16 prefix if needed */
557 ss = s;
558 if (s == 1 || (pa->instr_type & OPC_D16))
559 g(WORD_PREFIX_OPCODE);
560 else if (s == 2)
561 s = 1;
562 /* now generates the operation */
563 if (pa->instr_type & OPC_FWAIT)
564 g(0x9b);
565 if (has_seg_prefix)
566 g(segment_prefixes[seg_prefix.reg]);
567
568 v = pa->opcode;
569 if (v == 0x69 || v == 0x69) {
570 /* kludge for imul $im, %reg */
571 nb_ops = 3;
572 ops[2] = ops[1];
573 } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
574 v--; /* int $3 case */
575 nb_ops = 0;
576 } else if ((v == 0x06 || v == 0x07)) {
577 if (ops[0].reg >= 4) {
578 /* push/pop %fs or %gs */
579 v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
580 } else {
581 v += ops[0].reg << 3;
582 }
583 nb_ops = 0;
584 } else if (v <= 0x05) {
585 /* arith case */
586 v += ((opcode - TOK_ASM_addb) >> 2) << 3;
587 } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
588 /* fpu arith case */
589 v += ((opcode - pa->sym) / 6) << 3;
590 }
591 if (pa->instr_type & OPC_REG) {
592 for(i = 0; i < nb_ops; i++) {
593 if (op_type[i] & (OP_REG | OP_ST)) {
594 v += ops[i].reg;
595 break;
596 }
597 }
598 /* mov $im, %reg case */
599 if (pa->opcode == 0xb0 && s >= 1)
600 v += 7;
601 }
602 if (pa->instr_type & OPC_B)
603 v += s;
604 if (pa->instr_type & OPC_TEST)
605 v += test_bits[opcode - pa->sym];
606 if (pa->instr_type & OPC_SHORTJMP) {
607 Sym *sym;
608 int jmp_disp;
609
610 /* see if we can really generate the jump with a byte offset */
611 sym = ops[0].e.sym;
612 if (!sym)
613 goto no_short_jump;
614 if (sym->r != cur_text_section->sh_num)
615 goto no_short_jump;
616 jmp_disp = ops[0].e.v + (long)sym->next - ind - 2;
617 if (jmp_disp == (int8_t)jmp_disp) {
618 /* OK to generate jump */
619 is_short_jmp = 1;
620 ops[0].e.v = jmp_disp;
621 } else {
622 no_short_jump:
623 if (pa->instr_type & OPC_JMP) {
624 /* long jump will be allowed. need to modify the
625 opcode slightly */
626 if (v == 0xeb)
627 v = 0xe9;
628 else
629 v += 0x0f10;
630 } else {
631 error("invalid displacement");
632 }
633 }
634 }
635 op1 = v >> 8;
636 if (op1)
637 g(op1);
638 g(v);
639
640 /* search which operand will used for modrm */
641 modrm_index = 0;
642 if (pa->instr_type & OPC_SHIFT) {
643 reg = (opcode - pa->sym) >> 2;
644 if (reg == 6)
645 reg = 7;
646 } else if (pa->instr_type & OPC_ARITH) {
647 reg = (opcode - pa->sym) >> 2;
648 } else if (pa->instr_type & OPC_FARITH) {
649 reg = (opcode - pa->sym) / 6;
650 } else {
651 reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
652 }
653 if (pa->instr_type & OPC_MODRM) {
654 /* first look for an ea operand */
655 for(i = 0;i < nb_ops; i++) {
656 if (op_type[i] & OP_EA)
657 goto modrm_found;
658 }
659 /* then if not found, a register or indirection (shift instructions) */
660 for(i = 0;i < nb_ops; i++) {
661 if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
662 goto modrm_found;
663 }
664 #ifdef ASM_DEBUG
665 error("bad op table");
666 #endif
667 modrm_found:
668 modrm_index = i;
669 /* if a register is used in another operand then it is
670 used instead of group */
671 for(i = 0;i < nb_ops; i++) {
672 v = op_type[i];
673 if (i != modrm_index &&
674 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
675 reg = ops[i].reg;
676 break;
677 }
678 }
679
680 asm_modrm(reg, &ops[modrm_index]);
681 }
682
683 /* emit constants */
684 if (pa->opcode == 0x9a || pa->opcode == 0xea) {
685 /* ljmp or lcall kludge */
686 gen_expr32(&ops[1].e);
687 if (ops[0].e.sym)
688 error("cannot relocate");
689 gen_le16(ops[0].e.v);
690 } else {
691 for(i = 0;i < nb_ops; i++) {
692 v = op_type[i];
693 if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM8S | OP_ADDR)) {
694 /* if multiple sizes are given it means we must look
695 at the op size */
696 if (v == (OP_IM8 | OP_IM16 | OP_IM32) ||
697 v == (OP_IM16 | OP_IM32)) {
698 if (ss == 0)
699 v = OP_IM8;
700 else if (ss == 1)
701 v = OP_IM16;
702 else
703 v = OP_IM32;
704 }
705 if (v & (OP_IM8 | OP_IM8S)) {
706 if (ops[i].e.sym)
707 goto error_relocate;
708 g(ops[i].e.v);
709 } else if (v & OP_IM16) {
710 if (ops[i].e.sym) {
711 error_relocate:
712 error("cannot relocate");
713 }
714 gen_le16(ops[i].e.v);
715 } else {
716 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
717 if (is_short_jmp)
718 g(ops[i].e.v);
719 else
720 gen_disp32(&ops[i].e);
721 } else {
722 gen_expr32(&ops[i].e);
723 }
724 }
725 }
726 }
727 }
728 }
729
730 #define NB_SAVED_REGS 3
731 #define NB_ASM_REGS 8
732
733 /* return the constraint priority (we allocate first the lowest
734 numbered constraints) */
735 static inline int constraint_priority(const char *str)
736 {
737 int priority, c, pr;
738
739 /* we take the lowest priority */
740 priority = 0;
741 for(;;) {
742 c = *str;
743 if (c == '\0')
744 break;
745 str++;
746 switch(c) {
747 case 'A':
748 pr = 0;
749 break;
750 case 'a':
751 case 'b':
752 case 'c':
753 case 'd':
754 case 'S':
755 case 'D':
756 pr = 1;
757 break;
758 case 'q':
759 pr = 2;
760 break;
761 case 'r':
762 pr = 3;
763 break;
764 case 'N':
765 case 'M':
766 case 'I':
767 case 'i':
768 case 'm':
769 case 'g':
770 pr = 4;
771 break;
772 default:
773 error("unknown constraint '%c'", c);
774 pr = 0;
775 }
776 if (pr > priority)
777 priority = pr;
778 }
779 return priority;
780 }
781
782 static const char *skip_constraint_modifiers(const char *p)
783 {
784 while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
785 p++;
786 return p;
787 }
788
789 #define REG_OUT_MASK 0x01
790 #define REG_IN_MASK 0x02
791
792 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
793
794 static void asm_compute_constraints(ASMOperand *operands,
795 int nb_operands, int nb_outputs,
796 const uint8_t *clobber_regs,
797 int *pout_reg)
798 {
799 ASMOperand *op;
800 int sorted_op[MAX_ASM_OPERANDS];
801 int i, j, k, p1, p2, tmp, reg, c, reg_mask;
802 const char *str;
803 uint8_t regs_allocated[NB_ASM_REGS];
804
805 /* init fields */
806 for(i=0;i<nb_operands;i++) {
807 op = &operands[i];
808 op->input_index = -1;
809 op->ref_index = -1;
810 op->reg = -1;
811 op->is_memory = 0;
812 op->is_rw = 0;
813 }
814 /* compute constraint priority and evaluate references to output
815 constraints if input constraints */
816 for(i=0;i<nb_operands;i++) {
817 op = &operands[i];
818 str = op->constraint;
819 str = skip_constraint_modifiers(str);
820 if (isnum(*str) || *str == '[') {
821 /* this is a reference to another constraint */
822 k = find_constraint(operands, nb_operands, str, NULL);
823 if ((unsigned)k >= i || i < nb_outputs)
824 error("invalid reference in constraint %d ('%s')",
825 i, str);
826 op->ref_index = k;
827 if (operands[k].input_index >= 0)
828 error("cannot reference twice the same operand");
829 operands[k].input_index = i;
830 op->priority = 5;
831 } else {
832 op->priority = constraint_priority(str);
833 }
834 }
835
836 /* sort operands according to their priority */
837 for(i=0;i<nb_operands;i++)
838 sorted_op[i] = i;
839 for(i=0;i<nb_operands - 1;i++) {
840 for(j=i+1;j<nb_operands;j++) {
841 p1 = operands[sorted_op[i]].priority;
842 p2 = operands[sorted_op[j]].priority;
843 if (p2 < p1) {
844 tmp = sorted_op[i];
845 sorted_op[i] = sorted_op[j];
846 sorted_op[j] = tmp;
847 }
848 }
849 }
850
851 for(i = 0;i < NB_ASM_REGS; i++) {
852 if (clobber_regs[i])
853 regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
854 else
855 regs_allocated[i] = 0;
856 }
857 /* esp cannot be used */
858 regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
859 /* ebp cannot be used yet */
860 regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
861
862 /* allocate registers and generate corresponding asm moves */
863 for(i=0;i<nb_operands;i++) {
864 j = sorted_op[i];
865 op = &operands[j];
866 str = op->constraint;
867 /* no need to allocate references */
868 if (op->ref_index >= 0)
869 continue;
870 /* select if register is used for output, input or both */
871 if (op->input_index >= 0) {
872 reg_mask = REG_IN_MASK | REG_OUT_MASK;
873 } else if (j < nb_outputs) {
874 reg_mask = REG_OUT_MASK;
875 } else {
876 reg_mask = REG_IN_MASK;
877 }
878 try_next:
879 c = *str++;
880 switch(c) {
881 case '=':
882 goto try_next;
883 case '+':
884 op->is_rw = 1;
885 /* FALL THRU */
886 case '&':
887 if (j >= nb_outputs)
888 error("'%c' modifier can only be applied to outputs", c);
889 reg_mask = REG_IN_MASK | REG_OUT_MASK;
890 goto try_next;
891 case 'A':
892 /* allocate both eax and edx */
893 if (is_reg_allocated(TREG_EAX) ||
894 is_reg_allocated(TREG_EDX))
895 goto try_next;
896 op->is_llong = 1;
897 op->reg = TREG_EAX;
898 regs_allocated[TREG_EAX] |= reg_mask;
899 regs_allocated[TREG_EDX] |= reg_mask;
900 break;
901 case 'a':
902 reg = TREG_EAX;
903 goto alloc_reg;
904 case 'b':
905 reg = 3;
906 goto alloc_reg;
907 case 'c':
908 reg = TREG_ECX;
909 goto alloc_reg;
910 case 'd':
911 reg = TREG_EDX;
912 goto alloc_reg;
913 case 'S':
914 reg = 6;
915 goto alloc_reg;
916 case 'D':
917 reg = 7;
918 alloc_reg:
919 if (is_reg_allocated(reg))
920 goto try_next;
921 goto reg_found;
922 case 'q':
923 /* eax, ebx, ecx or edx */
924 for(reg = 0; reg < 4; reg++) {
925 if (!is_reg_allocated(reg))
926 goto reg_found;
927 }
928 goto try_next;
929 case 'r':
930 /* any general register */
931 for(reg = 0; reg < 8; reg++) {
932 if (!is_reg_allocated(reg))
933 goto reg_found;
934 }
935 goto try_next;
936 reg_found:
937 /* now we can reload in the register */
938 op->is_llong = 0;
939 op->reg = reg;
940 regs_allocated[reg] |= reg_mask;
941 break;
942 case 'i':
943 if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
944 goto try_next;
945 break;
946 case 'I':
947 case 'N':
948 case 'M':
949 if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
950 goto try_next;
951 break;
952 case 'm':
953 case 'g':
954 /* nothing special to do because the operand is already in
955 memory, except if the pointer itself is stored in a
956 memory variable (VT_LLOCAL case) */
957 /* XXX: fix constant case */
958 /* if it is a reference to a memory zone, it must lie
959 in a register, so we reserve the register in the
960 input registers and a load will be generated
961 later */
962 if (j < nb_outputs || c == 'm') {
963 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
964 /* any general register */
965 for(reg = 0; reg < 8; reg++) {
966 if (!(regs_allocated[reg] & REG_IN_MASK))
967 goto reg_found1;
968 }
969 goto try_next;
970 reg_found1:
971 /* now we can reload in the register */
972 regs_allocated[reg] |= REG_IN_MASK;
973 op->reg = reg;
974 op->is_memory = 1;
975 }
976 }
977 break;
978 default:
979 error("asm constraint %d ('%s') could not be satisfied",
980 j, op->constraint);
981 break;
982 }
983 /* if a reference is present for that operand, we assign it too */
984 if (op->input_index >= 0) {
985 operands[op->input_index].reg = op->reg;
986 operands[op->input_index].is_llong = op->is_llong;
987 }
988 }
989
990 /* compute out_reg. It is used to store outputs registers to memory
991 locations references by pointers (VT_LLOCAL case) */
992 *pout_reg = -1;
993 for(i=0;i<nb_operands;i++) {
994 op = &operands[i];
995 if (op->reg >= 0 &&
996 (op->vt->r & VT_VALMASK) == VT_LLOCAL &&
997 !op->is_memory) {
998 for(reg = 0; reg < 8; reg++) {
999 if (!(regs_allocated[reg] & REG_OUT_MASK))
1000 goto reg_found2;
1001 }
1002 error("could not find free output register for reloading");
1003 reg_found2:
1004 *pout_reg = reg;
1005 break;
1006 }
1007 }
1008
1009 /* print sorted constraints */
1010 #ifdef ASM_DEBUG
1011 for(i=0;i<nb_operands;i++) {
1012 j = sorted_op[i];
1013 op = &operands[j];
1014 printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1015 j,
1016 op->id ? get_tok_str(op->id, NULL) : "",
1017 op->constraint,
1018 op->vt->r,
1019 op->reg);
1020 }
1021 if (*pout_reg >= 0)
1022 printf("out_reg=%d\n", *pout_reg);
1023 #endif
1024 }
1025
1026 static void subst_asm_operand(CString *add_str,
1027 SValue *sv, int modifier)
1028 {
1029 int r, reg, size, val;
1030 char buf[64];
1031
1032 r = sv->r;
1033 if ((r & VT_VALMASK) == VT_CONST) {
1034 if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1035 cstr_ccat(add_str, '$');
1036 if (r & VT_SYM) {
1037 cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1038 if (sv->c.i != 0) {
1039 cstr_ccat(add_str, '+');
1040 } else {
1041 return;
1042 }
1043 }
1044 val = sv->c.i;
1045 if (modifier == 'n')
1046 val = -val;
1047 snprintf(buf, sizeof(buf), "%d", sv->c.i);
1048 cstr_cat(add_str, buf);
1049 } else if ((r & VT_VALMASK) == VT_LOCAL) {
1050 snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1051 cstr_cat(add_str, buf);
1052 } else if (r & VT_LVAL) {
1053 reg = r & VT_VALMASK;
1054 if (reg >= VT_CONST)
1055 error("internal compiler error");
1056 snprintf(buf, sizeof(buf), "(%%%s)",
1057 get_tok_str(TOK_ASM_eax + reg, NULL));
1058 cstr_cat(add_str, buf);
1059 } else {
1060 /* register case */
1061 reg = r & VT_VALMASK;
1062 if (reg >= VT_CONST)
1063 error("internal compiler error");
1064
1065 /* choose register operand size */
1066 if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1067 size = 1;
1068 else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1069 size = 2;
1070 else
1071 size = 4;
1072 if (size == 1 && reg >= 4)
1073 size = 4;
1074
1075 if (modifier == 'b') {
1076 if (reg >= 4)
1077 error("cannot use byte register");
1078 size = 1;
1079 } else if (modifier == 'h') {
1080 if (reg >= 4)
1081 error("cannot use byte register");
1082 size = -1;
1083 } else if (modifier == 'w') {
1084 size = 2;
1085 }
1086
1087 switch(size) {
1088 case -1:
1089 reg = TOK_ASM_ah + reg;
1090 break;
1091 case 1:
1092 reg = TOK_ASM_al + reg;
1093 break;
1094 case 2:
1095 reg = TOK_ASM_ax + reg;
1096 break;
1097 default:
1098 reg = TOK_ASM_eax + reg;
1099 break;
1100 }
1101 snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1102 cstr_cat(add_str, buf);
1103 }
1104 }
1105
1106 /* generate prolog and epilog code for asm statment */
1107 static void asm_gen_code(ASMOperand *operands, int nb_operands,
1108 int nb_outputs, int is_output,
1109 uint8_t *clobber_regs,
1110 int out_reg)
1111 {
1112 uint8_t regs_allocated[NB_ASM_REGS];
1113 ASMOperand *op;
1114 int i, reg;
1115 static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1116
1117 /* mark all used registers */
1118 memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1119 for(i = 0; i < nb_operands;i++) {
1120 op = &operands[i];
1121 if (op->reg >= 0)
1122 regs_allocated[op->reg] = 1;
1123 }
1124 if (!is_output) {
1125 /* generate reg save code */
1126 for(i = 0; i < NB_SAVED_REGS; i++) {
1127 reg = reg_saved[i];
1128 if (regs_allocated[reg])
1129 g(0x50 + reg);
1130 }
1131
1132 /* generate load code */
1133 for(i = 0; i < nb_operands; i++) {
1134 op = &operands[i];
1135 if (op->reg >= 0) {
1136 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1137 op->is_memory) {
1138 /* memory reference case (for both input and
1139 output cases) */
1140 SValue sv;
1141 sv = *op->vt;
1142 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1143 load(op->reg, &sv);
1144 } else if (i >= nb_outputs || op->is_rw) {
1145 /* load value in register */
1146 load(op->reg, op->vt);
1147 if (op->is_llong) {
1148 SValue sv;
1149 sv = *op->vt;
1150 sv.c.ul += 4;
1151 load(TREG_EDX, &sv);
1152 }
1153 }
1154 }
1155 }
1156 } else {
1157 /* generate save code */
1158 for(i = 0 ; i < nb_outputs; i++) {
1159 op = &operands[i];
1160 if (op->reg >= 0) {
1161 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1162 if (!op->is_memory) {
1163 SValue sv;
1164 sv = *op->vt;
1165 sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1166 load(out_reg, &sv);
1167
1168 sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1169 store(op->reg, &sv);
1170 }
1171 } else {
1172 store(op->reg, op->vt);
1173 if (op->is_llong) {
1174 SValue sv;
1175 sv = *op->vt;
1176 sv.c.ul += 4;
1177 store(TREG_EDX, &sv);
1178 }
1179 }
1180 }
1181 }
1182 /* generate reg restore code */
1183 for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1184 reg = reg_saved[i];
1185 if (regs_allocated[reg])
1186 g(0x58 + reg);
1187 }
1188 }
1189 }
1190
1191 static void asm_clobber(uint8_t *clobber_regs, const char *str)
1192 {
1193 int reg;
1194 TokenSym *ts;
1195
1196 if (!strcmp(str, "memory") ||
1197 !strcmp(str, "cc"))
1198 return;
1199 ts = tok_alloc(str, strlen(str));
1200 reg = ts->tok;
1201 if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1202 reg -= TOK_ASM_eax;
1203 } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1204 reg -= TOK_ASM_ax;
1205 } else {
1206 error("invalid clobber register '%s'", str);
1207 }
1208 clobber_regs[reg] = 1;
1209 }
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