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arm64-gen.c: Better explanation of relocation choice.
[tinycc.git] / arm64-gen.c
blob814fa16505e6a4bd4c37ae712fd95ea73f717285
1 /*
2 * A64 code generator for TCC
3 *
4 * Copyright (c) 2014-2015 Edmund Grimley Evans
5 *
6 * Copying and distribution of this file, with or without modification,
7 * are permitted in any medium without royalty provided the copyright
8 * notice and this notice are preserved. This file is offered as-is,
9 * without any warranty.
10 */
11
12 #ifdef TARGET_DEFS_ONLY
13
14 // Number of registers available to allocator:
15 #define NB_REGS 28 // x0-x18, x30, v0-v7
16
17 #define TREG_R(x) (x) // x = 0..18
18 #define TREG_R30 19
19 #define TREG_F(x) (x + 20) // x = 0..7
20
21 // Register classes sorted from more general to more precise:
22 #define RC_INT (1 << 0)
23 #define RC_FLOAT (1 << 1)
24 #define RC_R(x) (1 << (2 + (x))) // x = 0..18
25 #define RC_R30 (1 << 21)
26 #define RC_F(x) (1 << (22 + (x))) // x = 0..7
27
28 #define RC_IRET (RC_R(0)) // int return register class
29 #define RC_FRET (RC_F(0)) // float return register class
30
31 #define REG_IRET (TREG_R(0)) // int return register number
32 #define REG_FRET (TREG_F(0)) // float return register number
33
34 #define PTR_SIZE 8
35
36 #define LDOUBLE_SIZE 16
37 #define LDOUBLE_ALIGN 16
38
39 #define MAX_ALIGN 16
40
41 #define CHAR_IS_UNSIGNED
42
43 /******************************************************/
44 /* ELF defines */
45
46 #define EM_TCC_TARGET EM_AARCH64
47
48 #define R_DATA_32 R_AARCH64_ABS32
49 #define R_DATA_PTR R_AARCH64_ABS64
50 #define R_JMP_SLOT R_AARCH64_JUMP_SLOT
51 #define R_COPY R_AARCH64_COPY
52
53 #define ELF_START_ADDR 0x00400000
54 #define ELF_PAGE_SIZE 0x1000
55
56 /******************************************************/
57 #else /* ! TARGET_DEFS_ONLY */
58 /******************************************************/
59 #include "tcc.h"
60 #include <assert.h>
61
62 ST_DATA const int reg_classes[NB_REGS] = {
63 RC_INT | RC_R(0),
64 RC_INT | RC_R(1),
65 RC_INT | RC_R(2),
66 RC_INT | RC_R(3),
67 RC_INT | RC_R(4),
68 RC_INT | RC_R(5),
69 RC_INT | RC_R(6),
70 RC_INT | RC_R(7),
71 RC_INT | RC_R(8),
72 RC_INT | RC_R(9),
73 RC_INT | RC_R(10),
74 RC_INT | RC_R(11),
75 RC_INT | RC_R(12),
76 RC_INT | RC_R(13),
77 RC_INT | RC_R(14),
78 RC_INT | RC_R(15),
79 RC_INT | RC_R(16),
80 RC_INT | RC_R(17),
81 RC_INT | RC_R(18),
82 RC_R30, // not in RC_INT as we make special use of x30
83 RC_FLOAT | RC_F(0),
84 RC_FLOAT | RC_F(1),
85 RC_FLOAT | RC_F(2),
86 RC_FLOAT | RC_F(3),
87 RC_FLOAT | RC_F(4),
88 RC_FLOAT | RC_F(5),
89 RC_FLOAT | RC_F(6),
90 RC_FLOAT | RC_F(7)
91 };
92
93 #define IS_FREG(x) ((x) >= TREG_F(0))
94
95 static uint32_t intr(int r)
96 {
97 assert(TREG_R(0) <= r && r <= TREG_R30);
98 return r < TREG_R30 ? r : 30;
99 }
100
101 static uint32_t fltr(int r)
102 {
103 assert(TREG_F(0) <= r && r <= TREG_F(7));
104 return r - TREG_F(0);
105 }
106
107 // Add an instruction to text section:
108 ST_FUNC void o(unsigned int c)
109 {
110 int ind1 = ind + 4;
111 if (ind1 > cur_text_section->data_allocated)
112 section_realloc(cur_text_section, ind1);
113 *(uint32_t *)(cur_text_section->data + ind) = c;
114 ind = ind1;
115 }
116
117 static int arm64_encode_bimm64(uint64_t x)
118 {
119 int neg = x & 1;
120 int rep, pos, len;
121
122 if (neg)
123 x = ~x;
124 if (!x)
125 return -1;
126
127 if (x >> 2 == (x & (((uint64_t)1 << (64 - 2)) - 1)))
128 rep = 2, x &= ((uint64_t)1 << 2) - 1;
129 else if (x >> 4 == (x & (((uint64_t)1 << (64 - 4)) - 1)))
130 rep = 4, x &= ((uint64_t)1 << 4) - 1;
131 else if (x >> 8 == (x & (((uint64_t)1 << (64 - 8)) - 1)))
132 rep = 8, x &= ((uint64_t)1 << 8) - 1;
133 else if (x >> 16 == (x & (((uint64_t)1 << (64 - 16)) - 1)))
134 rep = 16, x &= ((uint64_t)1 << 16) - 1;
135 else if (x >> 32 == (x & (((uint64_t)1 << (64 - 32)) - 1)))
136 rep = 32, x &= ((uint64_t)1 << 32) - 1;
137 else
138 rep = 64;
139
140 pos = 0;
141 if (!(x & (((uint64_t)1 << 32) - 1))) x >>= 32, pos += 32;
142 if (!(x & (((uint64_t)1 << 16) - 1))) x >>= 16, pos += 16;
143 if (!(x & (((uint64_t)1 << 8) - 1))) x >>= 8, pos += 8;
144 if (!(x & (((uint64_t)1 << 4) - 1))) x >>= 4, pos += 4;
145 if (!(x & (((uint64_t)1 << 2) - 1))) x >>= 2, pos += 2;
146 if (!(x & (((uint64_t)1 << 1) - 1))) x >>= 1, pos += 1;
147
148 len = 0;
149 if (!(~x & (((uint64_t)1 << 32) - 1))) x >>= 32, len += 32;
150 if (!(~x & (((uint64_t)1 << 16) - 1))) x >>= 16, len += 16;
151 if (!(~x & (((uint64_t)1 << 8) - 1))) x >>= 8, len += 8;
152 if (!(~x & (((uint64_t)1 << 4) - 1))) x >>= 4, len += 4;
153 if (!(~x & (((uint64_t)1 << 2) - 1))) x >>= 2, len += 2;
154 if (!(~x & (((uint64_t)1 << 1) - 1))) x >>= 1, len += 1;
155
156 if (x)
157 return -1;
158 if (neg) {
159 pos = (pos + len) & (rep - 1);
160 len = rep - len;
161 }
162 return ((0x1000 & rep << 6) | (((rep - 1) ^ 31) << 1 & 63) |
163 ((rep - pos) & (rep - 1)) << 6 | (len - 1));
164 }
165
166 static uint32_t arm64_movi(int r, uint64_t x)
167 {
168 uint64_t m = 0xffff;
169 int e;
170 if (!(x & ~m))
171 return 0x52800000 | r | x << 5; // movz w(r),#(x)
172 if (!(x & ~(m << 16)))
173 return 0x52a00000 | r | x >> 11; // movz w(r),#(x >> 16),lsl #16
174 if (!(x & ~(m << 32)))
175 return 0xd2c00000 | r | x >> 27; // movz x(r),#(x >> 32),lsl #32
176 if (!(x & ~(m << 48)))
177 return 0xd2e00000 | r | x >> 43; // movz x(r),#(x >> 48),lsl #48
178 if ((x & ~m) == m << 16)
179 return (0x12800000 | r |
180 (~x << 5 & 0x1fffe0)); // movn w(r),#(~x)
181 if ((x & ~(m << 16)) == m)
182 return (0x12a00000 | r |
183 (~x >> 11 & 0x1fffe0)); // movn w(r),#(~x >> 16),lsl #16
184 if (!~(x | m))
185 return (0x92800000 | r |
186 (~x << 5 & 0x1fffe0)); // movn x(r),#(~x)
187 if (!~(x | m << 16))
188 return (0x92a00000 | r |
189 (~x >> 11 & 0x1fffe0)); // movn x(r),#(~x >> 16),lsl #16
190 if (!~(x | m << 32))
191 return (0x92c00000 | r |
192 (~x >> 27 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
193 if (!~(x | m << 48))
194 return (0x92e00000 | r |
195 (~x >> 43 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
196 if (!(x >> 32) && (e = arm64_encode_bimm64(x | x << 32)) >= 0)
197 return 0x320003e0 | r | (uint32_t)e << 10; // movi w(r),#(x)
198 if ((e = arm64_encode_bimm64(x)) >= 0)
199 return 0xb20003e0 | r | (uint32_t)e << 10; // movi x(r),#(x)
200 return 0;
201 }
202
203 static void arm64_movimm(int r, uint64_t x)
204 {
205 uint32_t i;
206 if ((i = arm64_movi(r, x)))
207 o(i);
208 else {
209 // This could be improved:
210 o(0x52800000 | r | (x & 0xffff) << 5); // movz w(r),#(x & 0xffff)
211 for (i = 1; i < 4; i++)
212 if (x >> 16 * i & 0xffff) {
213 o(0xf2800000 | r | (x >> 16 * i & 0xffff) << 5 | i << 21);
214 // movk w(r),#(*),lsl #(*)
215 }
216
217 }
218 }
219
220 // Patch all branches in list pointed to by t to branch to a:
221 ST_FUNC void gsym_addr(int t_, int a_)
222 {
223 uint32_t t = t_;
224 uint32_t a = a_;
225 while (t) {
226 uint32_t *ptr = (uint32_t *)(cur_text_section->data + t);
227 uint32_t next = *ptr;
228 if (a - t + 0x8000000 >= 0x10000000)
229 tcc_error("branch out of range");
230 *ptr = (a - t == 4 ? 0xd503201f : // nop
231 0x14000000 | ((a - t) >> 2 & 0x3ffffff)); // b
232 t = next;
233 }
234 }
235
236 // Patch all branches in list pointed to by t to branch to current location:
237 ST_FUNC void gsym(int t)
238 {
239 gsym_addr(t, ind);
240 }
241
242 static int arm64_type_size(int t)
243 {
244 switch (t & VT_BTYPE) {
245 case VT_INT: return 2;
246 case VT_BYTE: return 0;
247 case VT_SHORT: return 1;
248 case VT_PTR: return 3;
249 case VT_ENUM: return 2;
250 case VT_FUNC: return 3;
251 case VT_FLOAT: return 2;
252 case VT_DOUBLE: return 3;
253 case VT_LDOUBLE: return 4;
254 case VT_BOOL: return 0;
255 case VT_LLONG: return 3;
256 }
257 assert(0);
258 return 0;
259 }
260
261 static void gen_stack_addr(int reg, uint64_t off)
262 {
263 arm64_movimm(30, off); // use x30 for offset
264 o(0x8b3e63e0 | reg);
265 }
266
267 static void gen_load(int sg, int sz, int dst, int bas, uint64_t off)
268 {
269 if (sz >= 2)
270 sg = 0;
271 if (!(off & ~(0xfff << sz)))
272 o(0x39400000 | dst | bas << 5 | off << (10 - sz) |
273 !!sg << 23 | sz << 30);
274 else if (off < 256 || -off <= 256)
275 o(0x38400000 | dst | bas << 5 | (off & 511) << 12 |
276 !!sg << 23 | sz << 30);
277 else {
278 arm64_movimm(30, off); // use x30 for offset
279 o(0x38206800 | dst | bas << 5 | 30 << 16 |
280 (!!sg + 1) << 22 | sz << 30);
281 }
282 }
283
284 static void gen_fload(int sz, int dst, int bas, uint64_t off)
285 {
286 if (!(off & ~(0xfff << sz)))
287 o(0x3d400000 | dst | bas << 5 | off << (10 - sz) |
288 (sz & 4) << 21 | (sz & 3) << 30);
289 else if (off < 256 || -off <= 256)
290 o(0x3c400000 | dst | bas << 5 | (off & 511) << 12 |
291 (sz & 4) << 21 | (sz & 3) << 30);
292 else {
293 arm64_movimm(30, off); // use x30 for offset
294 o(0x3c606800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
295 }
296 }
297
298 static void gen_sload(int reg, int size)
299 {
300 // Use x30 for intermediate value in some cases.
301 switch (size) {
302 default: assert(0); break;
303 case 1:
304 gen_load(0, 0, reg, reg, 0);
305 break;
306 case 2:
307 gen_load(0, 1, reg, reg, 0);
308 break;
309 case 3:
310 gen_load(0, 1, 30, reg, 0);
311 gen_load(0, 0, reg, reg, 2);
312 o(0x2a0043c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #16
313 break;
314 case 4:
315 gen_load(0, 2, reg, reg, 0);
316 break;
317 case 5:
318 gen_load(0, 2, 30, reg, 0);
319 gen_load(0, 0, reg, reg, 4);
320 o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
321 break;
322 case 6:
323 gen_load(0, 2, 30, reg, 0);
324 gen_load(0, 1, reg, reg, 4);
325 o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
326 break;
327 case 7:
328 gen_load(0, 2, 30, reg, 0);
329 gen_load(0, 2, reg, reg, 3);
330 o(0x53087c00 | reg | reg << 5); // lsr w(reg), w(reg), #8
331 o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
332 break;
333 case 8:
334 gen_load(0, 3, reg, reg, 0);
335 break;
336 case 9:
337 gen_load(0, 0, reg + 1, reg, 8);
338 gen_load(0, 3, reg, reg, 0);
339 break;
340 case 10:
341 gen_load(0, 1, reg + 1, reg, 8);
342 gen_load(0, 3, reg, reg, 0);
343 break;
344 case 11:
345 gen_load(0, 2, reg + 1, reg, 7);
346 o(0x53087c00 | (reg+1) | (reg+1) << 5); // lsr w(reg+1), w(reg+1), #8
347 gen_load(0, 3, reg, reg, 0);
348 break;
349 case 12:
350 gen_load(0, 2, reg + 1, reg, 8);
351 gen_load(0, 3, reg, reg, 0);
352 break;
353 case 13:
354 gen_load(0, 3, reg + 1, reg, 5);
355 o(0xd358fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #24
356 gen_load(0, 3, reg, reg, 0);
357 break;
358 case 14:
359 gen_load(0, 3, reg + 1, reg, 6);
360 o(0xd350fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #16
361 gen_load(0, 3, reg, reg, 0);
362 break;
363 case 15:
364 gen_load(0, 3, reg + 1, reg, 7);
365 o(0xd348fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #8
366 gen_load(0, 3, reg, reg, 0);
367 break;
368 case 16:
369 o(0xa9400000 | reg | (reg+1) << 10 | reg << 5);
370 // ldp x(reg),x(reg+1),[x(reg)]
371 break;
372 }
373 }
374
375 static void gen_store(int sz, int dst, int bas, uint64_t off)
376 {
377 if (!(off & ~(0xfff << sz)))
378 o(0x39000000 | dst | bas << 5 | off << (10 - sz) | sz << 30);
379 else if (off < 256 || -off <= 256)
380 o(0x38000000 | dst | bas << 5 | (off & 511) << 12 | sz << 30);
381 else {
382 arm64_movimm(30, off); // use x30 for offset
383 o(0x38206800 | dst | bas << 5 | 30 << 16 | sz << 30);
384 }
385 }
386
387 static void gen_fstore(int sz, int dst, int bas, uint64_t off)
388 {
389 if (!(off & ~(0xfff << sz)))
390 o(0x3d000000 | dst | bas << 5 | off << (10 - sz) |
391 (sz & 4) << 21 | (sz & 3) << 30);
392 else if (off < 256 || -off <= 256)
393 o(0x3c000000 | dst | bas << 5 | (off & 511) << 12 |
394 (sz & 4) << 21 | (sz & 3) << 30);
395 else {
396 arm64_movimm(30, off); // use x30 for offset
397 o(0x3c206800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
398 }
399 }
400
401 static void gen_addr(int r, Sym *sym, unsigned long addend)
402 {
403 // Currently TCC's linker does not generate COPY relocations for
404 // STT_OBJECTs when tcc is invoked with "-run". This typically
405 // results in "R_AARCH64_ADR_PREL_PG_HI21 relocation failed" when
406 // a program refers to stdin. A workaround is to avoid that
407 // relocation and use only relocations with unlimited range.
408 int avoid_adrp = 1;
409
410 if (avoid_adrp || (sym->type.t & VT_WEAK)) {
411 // (GCC uses a R_AARCH64_ABS64 in this case.)
412 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G0_NC, addend);
413 o(0xd2800000 | r); // mov x(rt),#0,lsl #0
414 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G1_NC, addend);
415 o(0xf2a00000 | r); // movk x(rt),#0,lsl #16
416 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G2_NC, addend);
417 o(0xf2c00000 | r); // movk x(rt),#0,lsl #32
418 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G3, addend);
419 o(0xf2e00000 | r); // movk x(rt),#0,lsl #48
420 }
421 else {
422 greloca(cur_text_section, sym, ind, R_AARCH64_ADR_PREL_PG_HI21, addend);
423 o(0x90000000 | r);
424 greloca(cur_text_section, sym, ind, R_AARCH64_ADD_ABS_LO12_NC, addend);
425 o(0x91000000 | r | r << 5);
426 }
427 }
428
429 ST_FUNC void load(int r, SValue *sv)
430 {
431 int svtt = sv->type.t;
432 int svr = sv->r & ~VT_LVAL_TYPE;
433 int svrv = svr & VT_VALMASK;
434 uint64_t svcul = (int32_t)sv->c.ul;
435
436 if (svr == (VT_LOCAL | VT_LVAL)) {
437 if (IS_FREG(r))
438 gen_fload(arm64_type_size(svtt), fltr(r), 29, svcul);
439 else
440 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
441 intr(r), 29, svcul);
442 return;
443 }
444
445 if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
446 if (IS_FREG(r))
447 gen_fload(arm64_type_size(svtt),
448 fltr(r), intr(svrv), 0);
449 else
450 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
451 intr(r), intr(svrv), 0);
452 return;
453 }
454
455 if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
456 gen_addr(30, sv->sym, svcul); // use x30 for address
457 if (IS_FREG(r))
458 gen_fload(arm64_type_size(svtt), fltr(r), 30, 0);
459 else
460 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
461 intr(r), 30, 0);
462 return;
463 }
464
465 if (svr == (VT_CONST | VT_SYM)) {
466 gen_addr(intr(r), sv->sym, svcul);
467 return;
468 }
469
470 if (svr == VT_CONST) {
471 if ((svtt & VT_BTYPE) != VT_VOID)
472 arm64_movimm(intr(r),
473 arm64_type_size(svtt) == 3 ? sv->c.ull : svcul);
474 return;
475 }
476
477 if (svr < VT_CONST) {
478 if (IS_FREG(r) && IS_FREG(svr))
479 if (svtt == VT_LDOUBLE)
480 o(0x4ea01c00 | fltr(r) | fltr(svr) << 5);
481 // mov v(r).16b,v(svr).16b
482 else
483 o(0x1e604000 | fltr(r) | fltr(svr) << 5); // fmov d(r),d(svr)
484 else if (!IS_FREG(r) && !IS_FREG(svr))
485 o(0xaa0003e0 | intr(r) | intr(svr) << 16); // mov x(r),x(svr)
486 else
487 assert(0);
488 return;
489 }
490
491 if (svr == VT_LOCAL) {
492 if (-svcul < 0x1000)
493 o(0xd10003a0 | intr(r) | -svcul << 10); // sub x(r),x29,#...
494 else {
495 arm64_movimm(30, -svcul); // use x30 for offset
496 o(0xcb0003a0 | intr(r) | 30 << 16); // sub x(r),x29,x30
497 }
498 return;
499 }
500
501 if (svr == VT_JMP || svr == VT_JMPI) {
502 int t = (svr == VT_JMPI);
503 arm64_movimm(intr(r), t);
504 o(0x14000002); // b .+8
505 gsym(svcul);
506 arm64_movimm(intr(r), t ^ 1);
507 return;
508 }
509
510 if (svr == (VT_LLOCAL | VT_LVAL)) {
511 gen_load(0, 3, 30, 29, svcul); // use x30 for offset
512 if (IS_FREG(r))
513 gen_fload(arm64_type_size(svtt), fltr(r), 30, 0);
514 else
515 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
516 intr(r), 30, 0);
517 return;
518 }
519
520 printf("load(%x, (%x, %x, %llx))\n", r, svtt, sv->r, (long long)svcul);
521 assert(0);
522 }
523
524 ST_FUNC void store(int r, SValue *sv)
525 {
526 int svtt = sv->type.t;
527 int svr = sv->r & ~VT_LVAL_TYPE;
528 int svrv = svr & VT_VALMASK;
529 uint64_t svcul = (int32_t)sv->c.ul;
530
531 if (svr == (VT_LOCAL | VT_LVAL)) {
532 if (IS_FREG(r))
533 gen_fstore(arm64_type_size(svtt), fltr(r), 29, svcul);
534 else
535 gen_store(arm64_type_size(svtt), intr(r), 29, svcul);
536 return;
537 }
538
539 if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
540 if (IS_FREG(r))
541 gen_fstore(arm64_type_size(svtt), fltr(r), intr(svrv), 0);
542 else
543 gen_store(arm64_type_size(svtt), intr(r), intr(svrv), 0);
544 return;
545 }
546
547 if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
548 gen_addr(30, sv->sym, svcul); // use x30 for address
549 if (IS_FREG(r))
550 gen_fstore(arm64_type_size(svtt), fltr(r), 30, 0);
551 else
552 gen_store(arm64_type_size(svtt), intr(r), 30, 0);
553 return;
554 }
555
556 printf("store(%x, (%x, %x, %llx))\n", r, svtt, sv->r, (long long)svcul);
557 assert(0);
558 }
559
560 static void arm64_gen_bl_or_b(int b)
561 {
562 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
563 assert(!b);
564 if (vtop->r & VT_SYM)
565 greloc(cur_text_section, vtop->sym, ind, R_AARCH64_CALL26);
566 else
567 assert(0);
568 o(0x94000000); // bl .
569 }
570 else
571 o(0xd61f0000 | !b << 21 | intr(gv(RC_R30)) << 5); // br/blr
572 }
573
574 static int arm64_hfa_aux(CType *type, int *fsize, int num)
575 {
576 if (is_float(type->t)) {
577 int a, n = type_size(type, &a);
578 if (num >= 4 || (*fsize && *fsize != n))
579 return -1;
580 *fsize = n;
581 return num + 1;
582 }
583 else if ((type->t & VT_BTYPE) == VT_STRUCT) {
584 int is_struct = 0; // rather than union
585 Sym *field;
586 for (field = type->ref->next; field; field = field->next)
587 if (field->c) {
588 is_struct = 1;
589 break;
590 }
591 if (is_struct) {
592 int num0 = num;
593 for (field = type->ref->next; field; field = field->next) {
594 if (field->c != (num - num0) * *fsize)
595 return -1;
596 num = arm64_hfa_aux(&field->type, fsize, num);
597 if (num == -1)
598 return -1;
599 }
600 if (type->ref->c != (num - num0) * *fsize)
601 return -1;
602 return num;
603 }
604 else { // union
605 int num0 = num;
606 for (field = type->ref->next; field; field = field->next) {
607 int num1 = arm64_hfa_aux(&field->type, fsize, num0);
608 if (num1 == -1)
609 return -1;
610 num = num1 < num ? num : num1;
611 }
612 if (type->ref->c != (num - num0) * *fsize)
613 return -1;
614 return num;
615 }
616 }
617 else if (type->t & VT_ARRAY) {
618 int num1;
619 if (!type->ref->c)
620 return num;
621 num1 = arm64_hfa_aux(&type->ref->type, fsize, num);
622 if (num1 == -1 || (num1 != num && type->ref->c > 4))
623 return -1;
624 num1 = num + type->ref->c * (num1 - num);
625 if (num1 > 4)
626 return -1;
627 return num1;
628 }
629 return -1;
630 }
631
632 static int arm64_hfa(CType *type, int *fsize)
633 {
634 if ((type->t & VT_BTYPE) == VT_STRUCT || (type->t & VT_ARRAY)) {
635 int sz = 0;
636 int n = arm64_hfa_aux(type, &sz, 0);
637 if (0 < n && n <= 4) {
638 if (fsize)
639 *fsize = sz;
640 return n;
641 }
642 }
643 return 0;
644 }
645
646 static unsigned long arm64_pcs_aux(int n, CType **type, unsigned long *a)
647 {
648 int nx = 0; // next integer register
649 int nv = 0; // next vector register
650 unsigned long ns = 32; // next stack offset
651 int i;
652
653 for (i = 0; i < n; i++) {
654 int hfa = arm64_hfa(type[i], 0);
655 int size, align;
656
657 if ((type[i]->t & VT_ARRAY) ||
658 (type[i]->t & VT_BTYPE) == VT_FUNC)
659 size = align = 8;
660 else
661 size = type_size(type[i], &align);
662
663 if (hfa)
664 // B.2
665 ;
666 else if (size > 16) {
667 // B.3: replace with pointer
668 if (nx < 8)
669 a[i] = nx++ << 1 | 1;
670 else {
671 ns = (ns + 7) & ~7;
672 a[i] = ns | 1;
673 ns += 8;
674 }
675 continue;
676 }
677 else if ((type[i]->t & VT_BTYPE) == VT_STRUCT)
678 // B.4
679 size = (size + 7) & ~7;
680
681 // C.1
682 if (is_float(type[i]->t) && nv < 8) {
683 a[i] = 16 + (nv++ << 1);
684 continue;
685 }
686
687 // C.2
688 if (hfa && nv + hfa <= 8) {
689 a[i] = 16 + (nv << 1);
690 nv += hfa;
691 continue;
692 }
693
694 // C.3
695 if (hfa) {
696 nv = 8;
697 size = (size + 7) & ~7;
698 }
699
700 // C.4
701 if (hfa || (type[i]->t & VT_BTYPE) == VT_LDOUBLE) {
702 ns = (ns + 7) & ~7;
703 ns = (ns + align - 1) & -align;
704 }
705
706 // C.5
707 if ((type[i]->t & VT_BTYPE) == VT_FLOAT)
708 size = 8;
709
710 // C.6
711 if (hfa || is_float(type[i]->t)) {
712 a[i] = ns;
713 ns += size;
714 continue;
715 }
716
717 // C.7
718 if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size <= 8 && nx < 8) {
719 a[i] = nx++ << 1;
720 continue;
721 }
722
723 // C.8
724 if (align == 16)
725 nx = (nx + 1) & ~1;
726
727 // C.9
728 if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size == 16 && nx < 7) {
729 a[i] = nx << 1;
730 nx += 2;
731 continue;
732 }
733
734 // C.10
735 if ((type[i]->t & VT_BTYPE) == VT_STRUCT && size <= (8 - nx) * 8) {
736 a[i] = nx << 1;
737 nx += (size + 7) >> 3;
738 continue;
739 }
740
741 // C.11
742 nx = 8;
743
744 // C.12
745 ns = (ns + 7) & ~7;
746 ns = (ns + align - 1) & -align;
747
748 // C.13
749 if ((type[i]->t & VT_BTYPE) == VT_STRUCT) {
750 a[i] = ns;
751 ns += size;
752 continue;
753 }
754
755 // C.14
756 if (size < 8)
757 size = 8;
758
759 // C.15
760 a[i] = ns;
761 ns += size;
762 }
763
764 return ns - 32;
765 }
766
767 static unsigned long arm64_pcs(int n, CType **type, unsigned long *a)
768 {
769 unsigned long stack;
770
771 // Return type:
772 if ((type[0]->t & VT_BTYPE) == VT_VOID)
773 a[0] = -1;
774 else {
775 arm64_pcs_aux(1, type, a);
776 assert(a[0] == 0 || a[0] == 1 || a[0] == 16);
777 }
778
779 // Argument types:
780 stack = arm64_pcs_aux(n, type + 1, a + 1);
781
782 if (0) {
783 int i;
784 for (i = 0; i <= n; i++) {
785 if (!i)
786 printf("arm64_pcs return: ");
787 else
788 printf("arm64_pcs arg %d: ", i);
789 if (a[i] == (unsigned long)-1)
790 printf("void\n");
791 else if (a[i] == 1 && !i)
792 printf("X8 pointer\n");
793 else if (a[i] < 16)
794 printf("X%lu%s\n", a[i] / 2, a[i] & 1 ? " pointer" : "");
795 else if (a[i] < 32)
796 printf("V%lu\n", a[i] / 2 - 8);
797 else
798 printf("stack %lu%s\n",
799 (a[i] - 32) & ~1, a[i] & 1 ? " pointer" : "");
800 }
801 }
802
803 return stack;
804 }
805
806 ST_FUNC void gfunc_call(int nb_args)
807 {
808 CType *return_type;
809 CType **t;
810 unsigned long *a, *a1;
811 unsigned long stack;
812 int i;
813
814 return_type = &vtop[-nb_args].type.ref->type;
815 if ((return_type->t & VT_BTYPE) == VT_STRUCT)
816 --nb_args;
817
818 t = tcc_malloc((nb_args + 1) * sizeof(*t));
819 a = tcc_malloc((nb_args + 1) * sizeof(*a));
820 a1 = tcc_malloc((nb_args + 1) * sizeof(*a1));
821
822 t[0] = return_type;
823 for (i = 0; i < nb_args; i++)
824 t[nb_args - i] = &vtop[-i].type;
825
826 stack = arm64_pcs(nb_args, t, a);
827
828 // Allocate space for structs replaced by pointer:
829 for (i = nb_args; i; i--)
830 if (a[i] & 1) {
831 SValue *arg = &vtop[i - nb_args];
832 int align, size = type_size(&arg->type, &align);
833 assert((arg->type.t & VT_BTYPE) == VT_STRUCT);
834 stack = (stack + align - 1) & -align;
835 a1[i] = stack;
836 stack += size;
837 }
838
839 stack = (stack + 15) >> 4 << 4;
840
841 assert(stack < 0x1000);
842 if (stack)
843 o(0xd10003ff | stack << 10); // sub sp,sp,#(n)
844
845 // First pass: set all values on stack
846 for (i = nb_args; i; i--) {
847 vpushv(vtop - nb_args + i);
848
849 if (a[i] & 1) {
850 // struct replaced by pointer
851 int r = get_reg(RC_INT);
852 gen_stack_addr(intr(r), a1[i]);
853 vset(&vtop->type, r | VT_LVAL, 0);
854 vswap();
855 vstore();
856 if (a[i] >= 32) {
857 // pointer on stack
858 r = get_reg(RC_INT);
859 gen_stack_addr(intr(r), a1[i]);
860 gen_store(3, intr(r), 31, (a[i] - 32) >> 1 << 1);
861 }
862 }
863 else if (a[i] >= 32) {
864 // value on stack
865 if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
866 int r = get_reg(RC_INT);
867 gen_stack_addr(intr(r), a[i] - 32);
868 vset(&vtop->type, r | VT_LVAL, 0);
869 vswap();
870 vstore();
871 }
872 else if (is_float(vtop->type.t)) {
873 gv(RC_FLOAT);
874 gen_fstore(arm64_type_size(vtop[0].type.t),
875 fltr(vtop[0].r), 31, a[i] - 32);
876 }
877 else {
878 gv(RC_INT);
879 gen_store(arm64_type_size(vtop[0].type.t),
880 intr(vtop[0].r), 31, a[i] - 32);
881 }
882 }
883
884 --vtop;
885 }
886
887 // Second pass: assign values to registers
888 for (i = nb_args; i; i--, vtop--) {
889 if (a[i] < 16 && !(a[i] & 1)) {
890 // value in general-purpose registers
891 if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
892 int align, size = type_size(&vtop->type, &align);
893 vtop->type.t = VT_PTR;
894 gaddrof();
895 gv(RC_R(a[i] / 2));
896 gen_sload(a[i] / 2, size);
897 }
898 else
899 gv(RC_R(a[i] / 2));
900 }
901 else if (a[i] < 16)
902 // struct replaced by pointer in register
903 gen_stack_addr(a[i] / 2, a1[i]);
904 else if (a[i] < 32) {
905 // value in floating-point registers
906 if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
907 int j, sz, n = arm64_hfa(&vtop->type, &sz);
908 vtop->type.t = VT_PTR;
909 gaddrof();
910 gv(RC_R30);
911 for (j = 0; j < n; j++)
912 o(0x3d4003c0 |
913 (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
914 (a[i] / 2 - 8 + j) |
915 j << 10); // ldr ([sdq])(*),[x30,#(j * sz)]
916 }
917 else
918 gv(RC_F(a[i] / 2 - 8));
919 }
920 }
921
922 if ((return_type->t & VT_BTYPE) == VT_STRUCT) {
923 if (a[0] == 1) {
924 // indirect return: set x8 and discard the stack value
925 gv(RC_R(8));
926 --vtop;
927 }
928 else
929 // return in registers: keep the address for after the call
930 vswap();
931 }
932
933 save_regs(0);
934 arm64_gen_bl_or_b(0);
935 --vtop;
936 if (stack)
937 o(0x910003ff | stack << 10); // add sp,sp,#(n)
938
939 {
940 int rt = return_type->t;
941 int bt = rt & VT_BTYPE;
942 if (bt == VT_BYTE || bt == VT_SHORT)
943 // Promote small integers:
944 o(0x13001c00 | (bt == VT_SHORT) << 13 |
945 !!(rt & VT_UNSIGNED) << 30); // [su]xt[bh] w0,w0
946 else if (bt == VT_STRUCT && !(a[0] & 1)) {
947 // A struct was returned in registers, so write it out:
948 gv(RC_R(8));
949 --vtop;
950 if (a[0] == 0) {
951 int align, size = type_size(return_type, &align);
952 assert(size <= 16);
953 if (size > 8)
954 o(0xa9000500); // stp x0,x1,[x8]
955 else if (size)
956 gen_store(size > 4 ? 3 : size > 2 ? 2 : size > 1,
957 0, 8, 0);
958
959 }
960 else if (a[0] == 16) {
961 int j, sz, n = arm64_hfa(return_type, &sz);
962 for (j = 0; j < n; j++)
963 o(0x3d000100 |
964 (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
965 (a[i] / 2 - 8 + j) |
966 j << 10); // str ([sdq])(*),[x8,#(j * sz)]
967 }
968 }
969 }
970
971 tcc_free(a1);
972 tcc_free(a);
973 tcc_free(t);
974 }
975
976 static unsigned long arm64_func_va_list_stack;
977 static int arm64_func_va_list_gr_offs;
978 static int arm64_func_va_list_vr_offs;
979 static int arm64_func_sub_sp_offset;
980
981 ST_FUNC void gfunc_prolog(CType *func_type)
982 {
983 int n = 0;
984 int i = 0;
985 Sym *sym;
986 CType **t;
987 unsigned long *a;
988
989 // Why doesn't the caller (gen_function) set func_vt?
990 func_vt = func_type->ref->type;
991 func_vc = 144; // offset of where x8 is stored
992
993 for (sym = func_type->ref; sym; sym = sym->next)
994 ++n;
995 t = tcc_malloc(n * sizeof(*t));
996 a = tcc_malloc(n * sizeof(*a));
997
998 for (sym = func_type->ref; sym; sym = sym->next)
999 t[i++] = &sym->type;
1000
1001 arm64_func_va_list_stack = arm64_pcs(n - 1, t, a);
1002
1003 o(0xa9b27bfd); // stp x29,x30,[sp,#-224]!
1004 o(0xad0087e0); // stp q0,q1,[sp,#16]
1005 o(0xad018fe2); // stp q2,q3,[sp,#48]
1006 o(0xad0297e4); // stp q4,q5,[sp,#80]
1007 o(0xad039fe6); // stp q6,q7,[sp,#112]
1008 o(0xa90923e8); // stp x8,x8,[sp,#144]
1009 o(0xa90a07e0); // stp x0,x1,[sp,#160]
1010 o(0xa90b0fe2); // stp x2,x3,[sp,#176]
1011 o(0xa90c17e4); // stp x4,x5,[sp,#192]
1012 o(0xa90d1fe6); // stp x6,x7,[sp,#208]
1013
1014 arm64_func_va_list_gr_offs = -64;
1015 arm64_func_va_list_vr_offs = -128;
1016
1017 for (i = 1, sym = func_type->ref->next; sym; i++, sym = sym->next) {
1018 int off = (a[i] < 16 ? 160 + a[i] / 2 * 8 :
1019 a[i] < 32 ? 16 + (a[i] - 16) / 2 * 16 :
1020 224 + ((a[i] - 32) >> 1 << 1));
1021 sym_push(sym->v & ~SYM_FIELD, &sym->type,
1022 (a[i] & 1 ? VT_LLOCAL : VT_LOCAL) | lvalue_type(sym->type.t),
1023 off);
1024
1025 if (a[i] < 16) {
1026 int align, size = type_size(&sym->type, &align);
1027 arm64_func_va_list_gr_offs = (a[i] / 2 - 7 +
1028 (!(a[i] & 1) && size > 8)) * 8;
1029 }
1030 else if (a[i] < 32) {
1031 int hfa = arm64_hfa(&sym->type, 0);
1032 arm64_func_va_list_vr_offs = (a[i] / 2 - 16 +
1033 (hfa ? hfa : 1)) * 16;
1034 }
1035
1036 // HFAs of float and double need to be written differently:
1037 if (16 <= a[i] && a[i] < 32 && (sym->type.t & VT_BTYPE) == VT_STRUCT) {
1038 int j, sz, k = arm64_hfa(&sym->type, &sz);
1039 if (sz < 16)
1040 for (j = 0; j < k; j++) {
1041 o(0x3d0003e0 | -(sz & 8) << 27 | (sz & 4) << 29 |
1042 ((a[i] - 16) / 2 + j) | (off / sz + j) << 10);
1043 // str ([sdq])(*),[sp,#(j * sz)]
1044 }
1045 }
1046 }
1047
1048 tcc_free(a);
1049 tcc_free(t);
1050
1051 o(0x910003fd); // mov x29,sp
1052 arm64_func_sub_sp_offset = ind;
1053 // In gfunc_epilog these will be replaced with code to decrement SP:
1054 o(0xd503201f); // nop
1055 o(0xd503201f); // nop
1056 loc = 0;
1057 }
1058
1059 ST_FUNC void gen_va_start(void)
1060 {
1061 int r;
1062 --vtop; // we don't need the "arg"
1063 gaddrof();
1064 r = intr(gv(RC_INT));
1065
1066 if (arm64_func_va_list_stack) {
1067 //xx could use add (immediate) here
1068 arm64_movimm(30, arm64_func_va_list_stack + 224);
1069 o(0x8b1e03be); // add x30,x29,x30
1070 }
1071 else
1072 o(0x910383be); // add x30,x29,#224
1073 o(0xf900001e | r << 5); // str x30,[x(r)]
1074
1075 if (arm64_func_va_list_gr_offs) {
1076 if (arm64_func_va_list_stack)
1077 o(0x910383be); // add x30,x29,#224
1078 o(0xf900041e | r << 5); // str x30,[x(r),#8]
1079 }
1080
1081 if (arm64_func_va_list_vr_offs) {
1082 o(0x910243be); // add x30,x29,#144
1083 o(0xf900081e | r << 5); // str x30,[x(r),#16]
1084 }
1085
1086 arm64_movimm(30, arm64_func_va_list_gr_offs);
1087 o(0xb900181e | r << 5); // str w30,[x(r),#24]
1088
1089 arm64_movimm(30, arm64_func_va_list_vr_offs);
1090 o(0xb9001c1e | r << 5); // str w30,[x(r),#28]
1091
1092 --vtop;
1093 }
1094
1095 ST_FUNC void gen_va_arg(CType *t)
1096 {
1097 int align, size = type_size(t, &align);
1098 int fsize, hfa = arm64_hfa(t, &fsize);
1099 uint32_t r0, r1;
1100
1101 if (is_float(t->t)) {
1102 hfa = 1;
1103 fsize = size;
1104 }
1105
1106 gaddrof();
1107 r0 = intr(gv(RC_INT));
1108 r1 = get_reg(RC_INT);
1109 vtop[0].r = r1 | lvalue_type(t->t);
1110 r1 = intr(r1);
1111
1112 if (!hfa) {
1113 uint32_t n = size > 16 ? 8 : (size + 7) & -8;
1114 o(0xb940181e | r0 << 5); // ldr w30,[x(r0),#24] // __gr_offs
1115 if (align == 16) {
1116 assert(0); // this path untested but needed for __uint128_t
1117 o(0x11003fde); // add w30,w30,#15
1118 o(0x121c6fde); // and w30,w30,#-16
1119 }
1120 o(0x310003c0 | r1 | n << 10); // adds w(r1),w30,#(n)
1121 o(0x540000ad); // b.le .+20
1122 o(0xf9400000 | r1 | r0 << 5); // ldr x(r1),[x(r0)] // __stack
1123 o(0x9100001e | r1 << 5 | n << 10); // add x30,x(r1),#(n)
1124 o(0xf900001e | r0 << 5); // str x30,[x(r0)] // __stack
1125 o(0x14000004); // b .+16
1126 o(0xb9001800 | r1 | r0 << 5); // str w(r1),[x(r0),#24] // __gr_offs
1127 o(0xf9400400 | r1 | r0 << 5); // ldr x(r1),[x(r0),#8] // __gr_top
1128 o(0x8b3ec000 | r1 | r1 << 5); // add x(r1),x(r1),w30,sxtw
1129 if (size > 16)
1130 o(0xf9400000 | r1 | r1 << 5); // ldr x(r1),[x(r1)]
1131 }
1132 else {
1133 uint32_t rsz = hfa << 4;
1134 uint32_t ssz = (size + 7) & -(uint32_t)8;
1135 uint32_t b1, b2;
1136 o(0xb9401c1e | r0 << 5); // ldr w30,[x(r0),#28] // __vr_offs
1137 o(0x310003c0 | r1 | rsz << 10); // adds w(r1),w30,#(rsz)
1138 b1 = ind; o(0x5400000d); // b.le lab1
1139 o(0xf9400000 | r1 | r0 << 5); // ldr x(r1),[x(r0)] // __stack
1140 if (fsize == 16) {
1141 o(0x91003c00 | r1 | r1 << 5); // add x(r1),x(r1),#15
1142 o(0x927cec00 | r1 | r1 << 5); // and x(r1),x(r1),#-16
1143 }
1144 o(0x9100001e | r1 << 5 | ssz << 10); // add x30,x(r1),#(ssz)
1145 o(0xf900001e | r0 << 5); // str x30,[x(r0)] // __stack
1146 b2 = ind; o(0x14000000); // b lab2
1147 // lab1:
1148 *(uint32_t *)(cur_text_section->data + b1) =
1149 (0x5400000d | (ind - b1) << 3);
1150 o(0xb9001c00 | r1 | r0 << 5); // str w(r1),[x(r0),#28] // __vr_offs
1151 o(0xf9400800 | r1 | r0 << 5); // ldr x(r1),[x(r0),#16] // __vr_top
1152 if (hfa == 1 || fsize == 16)
1153 o(0x8b3ec000 | r1 | r1 << 5); // add x(r1),x(r1),w30,sxtw
1154 else {
1155 // We need to change the layout of this HFA.
1156 // Get some space on the stack using global variable "loc":
1157 loc = (loc - size) & -(uint32_t)align;
1158 o(0x8b3ec000 | 30 | r1 << 5); // add x30,x(r1),w30,sxtw
1159 arm64_movimm(r1, loc);
1160 o(0x8b0003a0 | r1 | r1 << 16); // add x(r1),x29,x(r1)
1161 o(0x4c402bdc | (uint32_t)fsize << 7 |
1162 (uint32_t)(hfa == 2) << 15 |
1163 (uint32_t)(hfa == 3) << 14); // ld1 {v28.(4s|2d),...},[x30]
1164 o(0x0d00801c | r1 << 5 | (fsize == 8) << 10 |
1165 (uint32_t)(hfa != 2) << 13 |
1166 (uint32_t)(hfa != 3) << 21); // st(hfa) {v28.(s|d),...}[0],[x(r1)]
1167 }
1168 // lab2:
1169 *(uint32_t *)(cur_text_section->data + b2) =
1170 (0x14000000 | (ind - b2) >> 2);
1171 }
1172 }
1173
1174 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *align)
1175 {
1176 return 0;
1177 }
1178
1179 ST_FUNC void greturn(void)
1180 {
1181 CType *t = &func_vt;
1182 unsigned long a;
1183
1184 arm64_pcs(0, &t, &a);
1185 switch (a) {
1186 case -1:
1187 break;
1188 case 0:
1189 if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
1190 int align, size = type_size(&func_vt, &align);
1191 gaddrof();
1192 gv(RC_R(0));
1193 gen_sload(0, size);
1194 }
1195 else
1196 gv(RC_IRET);
1197 break;
1198 case 1: {
1199 CType type = func_vt;
1200 mk_pointer(&type);
1201 vset(&type, VT_LOCAL | VT_LVAL, func_vc);
1202 indir();
1203 vswap();
1204 vstore();
1205 break;
1206 }
1207 case 16:
1208 if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
1209 int j, sz, n = arm64_hfa(&vtop->type, &sz);
1210 gaddrof();
1211 gv(RC_R(0));
1212 for (j = 0; j < n; j++)
1213 o(0x3d400000 |
1214 (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
1215 j | j << 10); // ldr ([sdq])(*),[x0,#(j * sz)]
1216 }
1217 else
1218 gv(RC_FRET);
1219 break;
1220 default:
1221 assert(0);
1222 }
1223 }
1224
1225 ST_FUNC void gfunc_epilog(void)
1226 {
1227 if (loc) {
1228 // Insert instructions to subtract size of stack frame from SP.
1229 uint32_t *ptr =
1230 (uint32_t *)(cur_text_section->data + arm64_func_sub_sp_offset);
1231 uint64_t diff = (-loc + 15) & ~15;
1232 if (!(diff >> 24)) {
1233 if (diff & 0xfff) // sub sp,sp,#(diff & 0xfff)
1234 ptr[0] = 0xd10003ff | (diff & 0xfff) << 10;
1235 if (diff >> 12) // sub sp,sp,#(diff >> 12),lsl #12
1236 ptr[1] = 0xd14003ff | (diff >> 12) << 10;
1237 }
1238 else {
1239 // In this case we may subtract more than necessary,
1240 // but always less than 17/16 of what we were aiming for.
1241 int i = 0;
1242 int j = 0;
1243 while (diff >> 20) {
1244 diff = (diff + 0xffff) >> 16;
1245 ++i;
1246 }
1247 while (diff >> 16) {
1248 diff = (diff + 1) >> 1;
1249 ++j;
1250 }
1251 ptr[0] = 0xd2800010 | diff << 5 | i << 21;
1252 // mov x16,#(diff),lsl #(16 * i)
1253 ptr[1] = 0xcb3063ff | j << 10;
1254 // sub sp,sp,x16,lsl #(j)
1255 }
1256 }
1257 o(0x910003bf); // mov sp,x29
1258 o(0xa8ce7bfd); // ldp x29,x30,[sp],#224
1259
1260 o(0xd65f03c0); // ret
1261 }
1262
1263 // Generate forward branch to label:
1264 ST_FUNC int gjmp(int t)
1265 {
1266 int r = ind;
1267 o(t);
1268 return r;
1269 }
1270
1271 // Generate branch to known address:
1272 ST_FUNC void gjmp_addr(int a)
1273 {
1274 assert(a - ind + 0x8000000 < 0x10000000);
1275 o(0x14000000 | ((a - ind) >> 2 & 0x3ffffff));
1276 }
1277
1278 ST_FUNC int gtst(int inv, int t)
1279 {
1280 int bt = vtop->type.t & VT_BTYPE;
1281 if (bt == VT_LDOUBLE) {
1282 int a, b, f = fltr(gv(RC_FLOAT));
1283 a = get_reg(RC_INT);
1284 vpushi(0);
1285 vtop[0].r = a;
1286 b = get_reg(RC_INT);
1287 a = intr(a);
1288 b = intr(b);
1289 o(0x4e083c00 | a | f << 5); // mov x(a),v(f).d[0]
1290 o(0x4e183c00 | b | f << 5); // mov x(b),v(f).d[1]
1291 o(0xaa000400 | a | a << 5 | b << 16); // orr x(a),x(a),x(b),lsl #1
1292 o(0xb4000040 | a | !!inv << 24); // cbz/cbnz x(a),.+8
1293 --vtop;
1294 }
1295 else if (bt == VT_FLOAT || bt == VT_DOUBLE) {
1296 int a = fltr(gv(RC_FLOAT));
1297 o(0x1e202008 | a << 5 | (bt != VT_FLOAT) << 22); // fcmp
1298 o(0x54000040 | !!inv); // b.eq/b.ne .+8
1299 }
1300 else {
1301 int ll = (bt == VT_PTR || bt == VT_LLONG);
1302 int a = intr(gv(RC_INT));
1303 o(0x34000040 | a | !!inv << 24 | ll << 31); // cbz/cbnz wA,.+8
1304 }
1305 --vtop;
1306 return gjmp(t);
1307 }
1308
1309 static void arm64_gen_opil(int op, int l)
1310 {
1311 int x, a, b;
1312 gv2(RC_INT, RC_INT);
1313 assert(vtop[-1].r < VT_CONST && vtop[0].r < VT_CONST);
1314 a = intr(vtop[-1].r);
1315 b = intr(vtop[0].r);
1316 vtop -= 2;
1317 x = get_reg(RC_INT);
1318 ++vtop;
1319 vtop[0].r = x;
1320 x = intr(x);
1321
1322 switch (op) {
1323 case '%':
1324 // Use x30 for quotient:
1325 o(0x1ac00c00 | l << 31 | 30 | a << 5 | b << 16); // sdiv
1326 o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
1327 break;
1328 case '&':
1329 o(0x0a000000 | l << 31 | x | a << 5 | b << 16); // and
1330 break;
1331 case '*':
1332 o(0x1b007c00 | l << 31 | x | a << 5 | b << 16); // mul
1333 break;
1334 case '+':
1335 o(0x0b000000 | l << 31 | x | a << 5 | b << 16); // add
1336 break;
1337 case '-':
1338 o(0x4b000000 | l << 31 | x | a << 5 | b << 16); // sub
1339 break;
1340 case '/':
1341 o(0x1ac00c00 | l << 31 | x | a << 5 | b << 16); // sdiv
1342 break;
1343 case '^':
1344 o(0x4a000000 | l << 31 | x | a << 5 | b << 16); // eor
1345 break;
1346 case '|':
1347 o(0x2a000000 | l << 31 | x | a << 5 | b << 16); // orr
1348 break;
1349 case TOK_EQ:
1350 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1351 o(0x1a9f17e0 | x); // cset wA,eq
1352 break;
1353 case TOK_GE:
1354 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1355 o(0x1a9fb7e0 | x); // cset wA,ge
1356 break;
1357 case TOK_GT:
1358 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1359 o(0x1a9fd7e0 | x); // cset wA,gt
1360 break;
1361 case TOK_LE:
1362 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1363 o(0x1a9fc7e0 | x); // cset wA,le
1364 break;
1365 case TOK_LT:
1366 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1367 o(0x1a9fa7e0 | x); // cset wA,lt
1368 break;
1369 case TOK_NE:
1370 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1371 o(0x1a9f07e0 | x); // cset wA,ne
1372 break;
1373 case TOK_SAR:
1374 o(0x1ac02800 | l << 31 | x | a << 5 | b << 16); // asr
1375 break;
1376 case TOK_SHL:
1377 o(0x1ac02000 | l << 31 | x | a << 5 | b << 16); // lsl
1378 break;
1379 case TOK_SHR:
1380 o(0x1ac02400 | l << 31 | x | a << 5 | b << 16); // lsr
1381 break;
1382 case TOK_UDIV:
1383 case TOK_PDIV:
1384 o(0x1ac00800 | l << 31 | x | a << 5 | b << 16); // udiv
1385 break;
1386 case TOK_UGE:
1387 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1388 o(0x1a9f37e0 | x); // cset wA,cs
1389 break;
1390 case TOK_UGT:
1391 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1392 o(0x1a9f97e0 | x); // cset wA,hi
1393 break;
1394 case TOK_ULT:
1395 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1396 o(0x1a9f27e0 | x); // cset wA,cc
1397 break;
1398 case TOK_ULE:
1399 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1400 o(0x1a9f87e0 | x); // cset wA,ls
1401 break;
1402 case TOK_UMOD:
1403 // Use x30 for quotient:
1404 o(0x1ac00800 | l << 31 | 30 | a << 5 | b << 16); // udiv
1405 o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
1406 break;
1407 default:
1408 assert(0);
1409 }
1410 }
1411
1412 ST_FUNC void gen_opi(int op)
1413 {
1414 arm64_gen_opil(op, 0);
1415 }
1416
1417 ST_FUNC void gen_opl(int op)
1418 {
1419 arm64_gen_opil(op, 1);
1420 }
1421
1422 ST_FUNC void gen_opf(int op)
1423 {
1424 int x, a, b, dbl;
1425
1426 if (vtop[0].type.t == VT_LDOUBLE) {
1427 CType type = vtop[0].type;
1428 int func = 0;
1429 int cond = -1;
1430 switch (op) {
1431 case '*': func = TOK___multf3; break;
1432 case '+': func = TOK___addtf3; break;
1433 case '-': func = TOK___subtf3; break;
1434 case '/': func = TOK___divtf3; break;
1435 case TOK_EQ: func = TOK___eqtf2; cond = 1; break;
1436 case TOK_NE: func = TOK___netf2; cond = 0; break;
1437 case TOK_LT: func = TOK___lttf2; cond = 10; break;
1438 case TOK_GE: func = TOK___getf2; cond = 11; break;
1439 case TOK_LE: func = TOK___letf2; cond = 12; break;
1440 case TOK_GT: func = TOK___gttf2; cond = 13; break;
1441 default: assert(0); break;
1442 }
1443 vpush_global_sym(&func_old_type, func);
1444 vrott(3);
1445 gfunc_call(2);
1446 vpushi(0);
1447 vtop->r = cond < 0 ? REG_FRET : REG_IRET;
1448 if (cond < 0)
1449 vtop->type = type;
1450 else {
1451 o(0x7100001f); // cmp w0,#0
1452 o(0x1a9f07e0 | cond << 12); // cset w0,(cond)
1453 }
1454 return;
1455 }
1456
1457 dbl = vtop[0].type.t != VT_FLOAT;
1458 gv2(RC_FLOAT, RC_FLOAT);
1459 assert(vtop[-1].r < VT_CONST && vtop[0].r < VT_CONST);
1460 a = fltr(vtop[-1].r);
1461 b = fltr(vtop[0].r);
1462 vtop -= 2;
1463 switch (op) {
1464 case TOK_EQ: case TOK_NE:
1465 case TOK_LT: case TOK_GE: case TOK_LE: case TOK_GT:
1466 x = get_reg(RC_INT);
1467 ++vtop;
1468 vtop[0].r = x;
1469 x = intr(x);
1470 break;
1471 default:
1472 x = get_reg(RC_FLOAT);
1473 ++vtop;
1474 vtop[0].r = x;
1475 x = fltr(x);
1476 break;
1477 }
1478
1479 switch (op) {
1480 case '*':
1481 o(0x1e200800 | dbl << 22 | x | a << 5 | b << 16); // fmul
1482 break;
1483 case '+':
1484 o(0x1e202800 | dbl << 22 | x | a << 5 | b << 16); // fadd
1485 break;
1486 case '-':
1487 o(0x1e203800 | dbl << 22 | x | a << 5 | b << 16); // fsub
1488 break;
1489 case '/':
1490 o(0x1e201800 | dbl << 22 | x | a << 5 | b << 16); // fdiv
1491 break;
1492 case TOK_EQ:
1493 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1494 o(0x1a9f17e0 | x); // cset w(x),eq
1495 break;
1496 case TOK_GE:
1497 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1498 o(0x1a9fb7e0 | x); // cset w(x),ge
1499 break;
1500 case TOK_GT:
1501 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1502 o(0x1a9fd7e0 | x); // cset w(x),gt
1503 break;
1504 case TOK_LE:
1505 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1506 o(0x1a9f87e0 | x); // cset w(x),ls
1507 break;
1508 case TOK_LT:
1509 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1510 o(0x1a9f57e0 | x); // cset w(x),mi
1511 break;
1512 case TOK_NE:
1513 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1514 o(0x1a9f07e0 | x); // cset w(x),ne
1515 break;
1516 default:
1517 assert(0);
1518 }
1519 }
1520
1521 // Generate sign extension from 32 to 64 bits:
1522 ST_FUNC void gen_cvt_sxtw(void)
1523 {
1524 int r = intr(gv(RC_INT));
1525 o(0x93407c00 | r | r << 5); // sxtw x(r),w(r)
1526 }
1527
1528 ST_FUNC void gen_cvt_itof(int t)
1529 {
1530 if (t == VT_LDOUBLE) {
1531 int f = vtop->type.t;
1532 int func = (f & VT_BTYPE) == VT_LLONG ?
1533 (f & VT_UNSIGNED ? TOK___floatunditf : TOK___floatditf) :
1534 (f & VT_UNSIGNED ? TOK___floatunsitf : TOK___floatsitf);
1535 vpush_global_sym(&func_old_type, func);
1536 vrott(2);
1537 gfunc_call(1);
1538 vpushi(0);
1539 vtop->type.t = t;
1540 vtop->r = REG_FRET;
1541 return;
1542 }
1543 else {
1544 int d, n = intr(gv(RC_INT));
1545 int s = !(vtop->type.t & VT_UNSIGNED);
1546 int l = ((vtop->type.t & VT_BTYPE) == VT_LLONG);
1547 --vtop;
1548 d = get_reg(RC_FLOAT);
1549 ++vtop;
1550 vtop[0].r = d;
1551 o(0x1e220000 | !s << 16 | (t != VT_FLOAT) << 22 | fltr(d) |
1552 l << 31 | n << 5); // [us]cvtf [sd](d),[wx](n)
1553 }
1554 }
1555
1556 ST_FUNC void gen_cvt_ftoi(int t)
1557 {
1558 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1559 int func = (t & VT_BTYPE) == VT_LLONG ?
1560 (t & VT_UNSIGNED ? TOK___fixunstfdi : TOK___fixtfdi) :
1561 (t & VT_UNSIGNED ? TOK___fixunstfsi : TOK___fixtfsi);
1562 vpush_global_sym(&func_old_type, func);
1563 vrott(2);
1564 gfunc_call(1);
1565 vpushi(0);
1566 vtop->type.t = t;
1567 vtop->r = REG_IRET;
1568 return;
1569 }
1570 else {
1571 int d, n = fltr(gv(RC_FLOAT));
1572 int l = ((vtop->type.t & VT_BTYPE) != VT_FLOAT);
1573 --vtop;
1574 d = get_reg(RC_INT);
1575 ++vtop;
1576 vtop[0].r = d;
1577 o(0x1e380000 |
1578 !!(t & VT_UNSIGNED) << 16 |
1579 ((t & VT_BTYPE) == VT_LLONG) << 31 | intr(d) |
1580 l << 22 | n << 5); // fcvtz[su] [wx](d),[sd](n)
1581 }
1582 }
1583
1584 ST_FUNC void gen_cvt_ftof(int t)
1585 {
1586 int f = vtop[0].type.t;
1587 assert(t == VT_FLOAT || t == VT_DOUBLE || t == VT_LDOUBLE);
1588 assert(f == VT_FLOAT || f == VT_DOUBLE || f == VT_LDOUBLE);
1589 if (t == f)
1590 return;
1591
1592 if (t == VT_LDOUBLE || f == VT_LDOUBLE) {
1593 int func = (t == VT_LDOUBLE) ?
1594 (f == VT_FLOAT ? TOK___extendsftf2 : TOK___extenddftf2) :
1595 (t == VT_FLOAT ? TOK___trunctfsf2 : TOK___trunctfdf2);
1596 vpush_global_sym(&func_old_type, func);
1597 vrott(2);
1598 gfunc_call(1);
1599 vpushi(0);
1600 vtop->type.t = t;
1601 vtop->r = REG_FRET;
1602 }
1603 else {
1604 int x, a;
1605 gv(RC_FLOAT);
1606 assert(vtop[0].r < VT_CONST);
1607 a = fltr(vtop[0].r);
1608 --vtop;
1609 x = get_reg(RC_FLOAT);
1610 ++vtop;
1611 vtop[0].r = x;
1612 x = fltr(x);
1613
1614 if (f == VT_FLOAT)
1615 o(0x1e22c000 | x | a << 5); // fcvt d(x),s(a)
1616 else
1617 o(0x1e624000 | x | a << 5); // fcvt s(x),d(a)
1618 }
1619 }
1620
1621 ST_FUNC void ggoto(void)
1622 {
1623 arm64_gen_bl_or_b(1);
1624 --vtop;
1625 }
1626
1627 ST_FUNC void gen_vla_sp_save(int addr) {
1628 tcc_error("variable length arrays unsupported for this target");
1629 }
1630
1631 ST_FUNC void gen_vla_sp_restore(int addr) {
1632 tcc_error("variable length arrays unsupported for this target");
1633 }
1634
1635 ST_FUNC void gen_vla_alloc(CType *type, int align) {
1636 tcc_error("variable length arrays unsupported for this target");
1637 }
1638
1639 /* end of A64 code generator */
1640 /*************************************************************/
1641 #endif
1642 /*************************************************************/
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