?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
arm64: Improve constant generation, with tests.
[tinycc.git] / arm64-gen.c
blobd64be1ae5bfe5068c0d3e2e262a9dbb7ba26e05f
1 /*
2 * A64 code generator for TCC
3 *
4 * Copyright (c) 2014-2015 Edmund Grimley Evans
5 *
6 * Copying and distribution of this file, with or without modification,
7 * are permitted in any medium without royalty provided the copyright
8 * notice and this notice are preserved. This file is offered as-is,
9 * without any warranty.
10 */
11
12 #ifdef TARGET_DEFS_ONLY
13
14 // Number of registers available to allocator:
15 #define NB_REGS 28 // x0-x18, x30, v0-v7
16
17 #define TREG_R(x) (x) // x = 0..18
18 #define TREG_R30 19
19 #define TREG_F(x) (x + 20) // x = 0..7
20
21 // Register classes sorted from more general to more precise:
22 #define RC_INT (1 << 0)
23 #define RC_FLOAT (1 << 1)
24 #define RC_R(x) (1 << (2 + (x))) // x = 0..18
25 #define RC_R30 (1 << 21)
26 #define RC_F(x) (1 << (22 + (x))) // x = 0..7
27
28 #define RC_IRET (RC_R(0)) // int return register class
29 #define RC_FRET (RC_F(0)) // float return register class
30
31 #define REG_IRET (TREG_R(0)) // int return register number
32 #define REG_FRET (TREG_F(0)) // float return register number
33
34 #define PTR_SIZE 8
35
36 #define LDOUBLE_SIZE 16
37 #define LDOUBLE_ALIGN 16
38
39 #define MAX_ALIGN 16
40
41 #define CHAR_IS_UNSIGNED
42
43 /******************************************************/
44 /* ELF defines */
45
46 #define EM_TCC_TARGET EM_AARCH64
47
48 #define R_DATA_32 R_AARCH64_ABS32
49 #define R_DATA_PTR R_AARCH64_ABS64
50 #define R_JMP_SLOT R_AARCH64_JUMP_SLOT
51 #define R_COPY R_AARCH64_COPY
52
53 #define ELF_START_ADDR 0x00400000
54 #define ELF_PAGE_SIZE 0x1000
55
56 /******************************************************/
57 #else /* ! TARGET_DEFS_ONLY */
58 /******************************************************/
59 #include "tcc.h"
60 #include <assert.h>
61
62 ST_DATA const int reg_classes[NB_REGS] = {
63 RC_INT | RC_R(0),
64 RC_INT | RC_R(1),
65 RC_INT | RC_R(2),
66 RC_INT | RC_R(3),
67 RC_INT | RC_R(4),
68 RC_INT | RC_R(5),
69 RC_INT | RC_R(6),
70 RC_INT | RC_R(7),
71 RC_INT | RC_R(8),
72 RC_INT | RC_R(9),
73 RC_INT | RC_R(10),
74 RC_INT | RC_R(11),
75 RC_INT | RC_R(12),
76 RC_INT | RC_R(13),
77 RC_INT | RC_R(14),
78 RC_INT | RC_R(15),
79 RC_INT | RC_R(16),
80 RC_INT | RC_R(17),
81 RC_INT | RC_R(18),
82 RC_R30, // not in RC_INT as we make special use of x30
83 RC_FLOAT | RC_F(0),
84 RC_FLOAT | RC_F(1),
85 RC_FLOAT | RC_F(2),
86 RC_FLOAT | RC_F(3),
87 RC_FLOAT | RC_F(4),
88 RC_FLOAT | RC_F(5),
89 RC_FLOAT | RC_F(6),
90 RC_FLOAT | RC_F(7)
91 };
92
93 #define IS_FREG(x) ((x) >= TREG_F(0))
94
95 static uint32_t intr(int r)
96 {
97 assert(TREG_R(0) <= r && r <= TREG_R30);
98 return r < TREG_R30 ? r : 30;
99 }
100
101 static uint32_t fltr(int r)
102 {
103 assert(TREG_F(0) <= r && r <= TREG_F(7));
104 return r - TREG_F(0);
105 }
106
107 // Add an instruction to text section:
108 ST_FUNC void o(unsigned int c)
109 {
110 int ind1 = ind + 4;
111 if (ind1 > cur_text_section->data_allocated)
112 section_realloc(cur_text_section, ind1);
113 *(uint32_t *)(cur_text_section->data + ind) = c;
114 ind = ind1;
115 }
116
117 static int arm64_encode_bimm64(uint64_t x)
118 {
119 int neg = x & 1;
120 int rep, pos, len;
121
122 if (neg)
123 x = ~x;
124 if (!x)
125 return -1;
126
127 if (x >> 2 == (x & (((uint64_t)1 << (64 - 2)) - 1)))
128 rep = 2, x &= ((uint64_t)1 << 2) - 1;
129 else if (x >> 4 == (x & (((uint64_t)1 << (64 - 4)) - 1)))
130 rep = 4, x &= ((uint64_t)1 << 4) - 1;
131 else if (x >> 8 == (x & (((uint64_t)1 << (64 - 8)) - 1)))
132 rep = 8, x &= ((uint64_t)1 << 8) - 1;
133 else if (x >> 16 == (x & (((uint64_t)1 << (64 - 16)) - 1)))
134 rep = 16, x &= ((uint64_t)1 << 16) - 1;
135 else if (x >> 32 == (x & (((uint64_t)1 << (64 - 32)) - 1)))
136 rep = 32, x &= ((uint64_t)1 << 32) - 1;
137 else
138 rep = 64;
139
140 pos = 0;
141 if (!(x & (((uint64_t)1 << 32) - 1))) x >>= 32, pos += 32;
142 if (!(x & (((uint64_t)1 << 16) - 1))) x >>= 16, pos += 16;
143 if (!(x & (((uint64_t)1 << 8) - 1))) x >>= 8, pos += 8;
144 if (!(x & (((uint64_t)1 << 4) - 1))) x >>= 4, pos += 4;
145 if (!(x & (((uint64_t)1 << 2) - 1))) x >>= 2, pos += 2;
146 if (!(x & (((uint64_t)1 << 1) - 1))) x >>= 1, pos += 1;
147
148 len = 0;
149 if (!(~x & (((uint64_t)1 << 32) - 1))) x >>= 32, len += 32;
150 if (!(~x & (((uint64_t)1 << 16) - 1))) x >>= 16, len += 16;
151 if (!(~x & (((uint64_t)1 << 8) - 1))) x >>= 8, len += 8;
152 if (!(~x & (((uint64_t)1 << 4) - 1))) x >>= 4, len += 4;
153 if (!(~x & (((uint64_t)1 << 2) - 1))) x >>= 2, len += 2;
154 if (!(~x & (((uint64_t)1 << 1) - 1))) x >>= 1, len += 1;
155
156 if (x)
157 return -1;
158 if (neg) {
159 pos = (pos + len) & (rep - 1);
160 len = rep - len;
161 }
162 return ((0x1000 & rep << 6) | (((rep - 1) ^ 31) << 1 & 63) |
163 ((rep - pos) & (rep - 1)) << 6 | (len - 1));
164 }
165
166 static uint32_t arm64_movi(int r, uint64_t x)
167 {
168 uint64_t m = 0xffff;
169 int e;
170 if (!(x & ~m))
171 return 0x52800000 | r | x << 5; // movz w(r),#(x)
172 if (!(x & ~(m << 16)))
173 return 0x52a00000 | r | x >> 11; // movz w(r),#(x >> 16),lsl #16
174 if (!(x & ~(m << 32)))
175 return 0xd2c00000 | r | x >> 27; // movz x(r),#(x >> 32),lsl #32
176 if (!(x & ~(m << 48)))
177 return 0xd2e00000 | r | x >> 43; // movz x(r),#(x >> 48),lsl #48
178 if ((x & ~m) == m << 16)
179 return (0x12800000 | r |
180 (~x << 5 & 0x1fffe0)); // movn w(r),#(~x)
181 if ((x & ~(m << 16)) == m)
182 return (0x12a00000 | r |
183 (~x >> 11 & 0x1fffe0)); // movn w(r),#(~x >> 16),lsl #16
184 if (!~(x | m))
185 return (0x92800000 | r |
186 (~x << 5 & 0x1fffe0)); // movn x(r),#(~x)
187 if (!~(x | m << 16))
188 return (0x92a00000 | r |
189 (~x >> 11 & 0x1fffe0)); // movn x(r),#(~x >> 16),lsl #16
190 if (!~(x | m << 32))
191 return (0x92c00000 | r |
192 (~x >> 27 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
193 if (!~(x | m << 48))
194 return (0x92e00000 | r |
195 (~x >> 43 & 0x1fffe0)); // movn x(r),#(~x >> 32),lsl #32
196 if (!(x >> 32) && (e = arm64_encode_bimm64(x | x << 32)) >= 0)
197 return 0x320003e0 | r | (uint32_t)e << 10; // movi w(r),#(x)
198 if ((e = arm64_encode_bimm64(x)) >= 0)
199 return 0xb20003e0 | r | (uint32_t)e << 10; // movi x(r),#(x)
200 return 0;
201 }
202
203 static void arm64_movimm(int r, uint64_t x)
204 {
205 uint32_t i;
206 if ((i = arm64_movi(r, x)))
207 o(i); // a single MOV
208 else {
209 // MOVZ/MOVN and 1-3 MOVKs
210 int z = 0, m = 0;
211 uint32_t mov1 = 0xd2800000; // movz
212 uint64_t x1 = x;
213 for (i = 0; i < 64; i += 16) {
214 z += !(x >> i & 0xffff);
215 m += !(~x >> i & 0xffff);
216 }
217 if (m > z) {
218 x1 = ~x;
219 mov1 = 0x92800000; // movn
220 }
221 for (i = 0; i < 64; i += 16)
222 if (x1 >> i & 0xffff) {
223 o(mov1 | r | (x1 >> i & 0xffff) << 5 | i << 17);
224 // movz/movn x(r),#(*),lsl #(i)
225 break;
226 }
227 for (i += 16; i < 64; i += 16)
228 if (x1 >> i & 0xffff)
229 o(0xf2800000 | r | (x >> i & 0xffff) << 5 | i << 17);
230 // movk x(r),#(*),lsl #(i)
231 }
232 }
233
234 // Patch all branches in list pointed to by t to branch to a:
235 ST_FUNC void gsym_addr(int t_, int a_)
236 {
237 uint32_t t = t_;
238 uint32_t a = a_;
239 while (t) {
240 uint32_t *ptr = (uint32_t *)(cur_text_section->data + t);
241 uint32_t next = *ptr;
242 if (a - t + 0x8000000 >= 0x10000000)
243 tcc_error("branch out of range");
244 *ptr = (a - t == 4 ? 0xd503201f : // nop
245 0x14000000 | ((a - t) >> 2 & 0x3ffffff)); // b
246 t = next;
247 }
248 }
249
250 // Patch all branches in list pointed to by t to branch to current location:
251 ST_FUNC void gsym(int t)
252 {
253 gsym_addr(t, ind);
254 }
255
256 static int arm64_type_size(int t)
257 {
258 switch (t & VT_BTYPE) {
259 case VT_INT: return 2;
260 case VT_BYTE: return 0;
261 case VT_SHORT: return 1;
262 case VT_PTR: return 3;
263 case VT_ENUM: return 2;
264 case VT_FUNC: return 3;
265 case VT_FLOAT: return 2;
266 case VT_DOUBLE: return 3;
267 case VT_LDOUBLE: return 4;
268 case VT_BOOL: return 0;
269 case VT_LLONG: return 3;
270 }
271 assert(0);
272 return 0;
273 }
274
275 static void gen_stack_addr(int reg, uint64_t off)
276 {
277 arm64_movimm(30, off); // use x30 for offset
278 o(0x8b3e63e0 | reg);
279 }
280
281 static void gen_load(int sg, int sz, int dst, int bas, uint64_t off)
282 {
283 if (sz >= 2)
284 sg = 0;
285 if (!(off & ~(0xfff << sz)))
286 o(0x39400000 | dst | bas << 5 | off << (10 - sz) |
287 !!sg << 23 | sz << 30);
288 else if (off < 256 || -off <= 256)
289 o(0x38400000 | dst | bas << 5 | (off & 511) << 12 |
290 !!sg << 23 | sz << 30);
291 else {
292 arm64_movimm(30, off); // use x30 for offset
293 o(0x38206800 | dst | bas << 5 | 30 << 16 |
294 (!!sg + 1) << 22 | sz << 30);
295 }
296 }
297
298 static void gen_fload(int sz, int dst, int bas, uint64_t off)
299 {
300 if (!(off & ~(0xfff << sz)))
301 o(0x3d400000 | dst | bas << 5 | off << (10 - sz) |
302 (sz & 4) << 21 | (sz & 3) << 30);
303 else if (off < 256 || -off <= 256)
304 o(0x3c400000 | dst | bas << 5 | (off & 511) << 12 |
305 (sz & 4) << 21 | (sz & 3) << 30);
306 else {
307 arm64_movimm(30, off); // use x30 for offset
308 o(0x3c606800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
309 }
310 }
311
312 static void gen_sload(int reg, int size)
313 {
314 // Use x30 for intermediate value in some cases.
315 switch (size) {
316 default: assert(0); break;
317 case 1:
318 gen_load(0, 0, reg, reg, 0);
319 break;
320 case 2:
321 gen_load(0, 1, reg, reg, 0);
322 break;
323 case 3:
324 gen_load(0, 1, 30, reg, 0);
325 gen_load(0, 0, reg, reg, 2);
326 o(0x2a0043c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #16
327 break;
328 case 4:
329 gen_load(0, 2, reg, reg, 0);
330 break;
331 case 5:
332 gen_load(0, 2, 30, reg, 0);
333 gen_load(0, 0, reg, reg, 4);
334 o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
335 break;
336 case 6:
337 gen_load(0, 2, 30, reg, 0);
338 gen_load(0, 1, reg, reg, 4);
339 o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
340 break;
341 case 7:
342 gen_load(0, 2, 30, reg, 0);
343 gen_load(0, 2, reg, reg, 3);
344 o(0x53087c00 | reg | reg << 5); // lsr w(reg), w(reg), #8
345 o(0xaa0083c0 | reg | reg << 16); // orr x(reg),x30,x(reg),lsl #32
346 break;
347 case 8:
348 gen_load(0, 3, reg, reg, 0);
349 break;
350 case 9:
351 gen_load(0, 0, reg + 1, reg, 8);
352 gen_load(0, 3, reg, reg, 0);
353 break;
354 case 10:
355 gen_load(0, 1, reg + 1, reg, 8);
356 gen_load(0, 3, reg, reg, 0);
357 break;
358 case 11:
359 gen_load(0, 2, reg + 1, reg, 7);
360 o(0x53087c00 | (reg+1) | (reg+1) << 5); // lsr w(reg+1), w(reg+1), #8
361 gen_load(0, 3, reg, reg, 0);
362 break;
363 case 12:
364 gen_load(0, 2, reg + 1, reg, 8);
365 gen_load(0, 3, reg, reg, 0);
366 break;
367 case 13:
368 gen_load(0, 3, reg + 1, reg, 5);
369 o(0xd358fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #24
370 gen_load(0, 3, reg, reg, 0);
371 break;
372 case 14:
373 gen_load(0, 3, reg + 1, reg, 6);
374 o(0xd350fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #16
375 gen_load(0, 3, reg, reg, 0);
376 break;
377 case 15:
378 gen_load(0, 3, reg + 1, reg, 7);
379 o(0xd348fc00 | (reg+1) | (reg+1) << 5); // lsr x(reg+1), x(reg+1), #8
380 gen_load(0, 3, reg, reg, 0);
381 break;
382 case 16:
383 o(0xa9400000 | reg | (reg+1) << 10 | reg << 5);
384 // ldp x(reg),x(reg+1),[x(reg)]
385 break;
386 }
387 }
388
389 static void gen_store(int sz, int dst, int bas, uint64_t off)
390 {
391 if (!(off & ~(0xfff << sz)))
392 o(0x39000000 | dst | bas << 5 | off << (10 - sz) | sz << 30);
393 else if (off < 256 || -off <= 256)
394 o(0x38000000 | dst | bas << 5 | (off & 511) << 12 | sz << 30);
395 else {
396 arm64_movimm(30, off); // use x30 for offset
397 o(0x38206800 | dst | bas << 5 | 30 << 16 | sz << 30);
398 }
399 }
400
401 static void gen_fstore(int sz, int dst, int bas, uint64_t off)
402 {
403 if (!(off & ~(0xfff << sz)))
404 o(0x3d000000 | dst | bas << 5 | off << (10 - sz) |
405 (sz & 4) << 21 | (sz & 3) << 30);
406 else if (off < 256 || -off <= 256)
407 o(0x3c000000 | dst | bas << 5 | (off & 511) << 12 |
408 (sz & 4) << 21 | (sz & 3) << 30);
409 else {
410 arm64_movimm(30, off); // use x30 for offset
411 o(0x3c206800 | dst | bas << 5 | 30 << 16 | sz << 30 | (sz & 4) << 21);
412 }
413 }
414
415 static void gen_addr(int r, Sym *sym, unsigned long addend)
416 {
417 // Currently TCC's linker does not generate COPY relocations for
418 // STT_OBJECTs when tcc is invoked with "-run". This typically
419 // results in "R_AARCH64_ADR_PREL_PG_HI21 relocation failed" when
420 // a program refers to stdin. A workaround is to avoid that
421 // relocation and use only relocations with unlimited range.
422 int avoid_adrp = 1;
423
424 if (avoid_adrp || (sym->type.t & VT_WEAK)) {
425 // (GCC uses a R_AARCH64_ABS64 in this case.)
426 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G0_NC, addend);
427 o(0xd2800000 | r); // mov x(rt),#0,lsl #0
428 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G1_NC, addend);
429 o(0xf2a00000 | r); // movk x(rt),#0,lsl #16
430 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G2_NC, addend);
431 o(0xf2c00000 | r); // movk x(rt),#0,lsl #32
432 greloca(cur_text_section, sym, ind, R_AARCH64_MOVW_UABS_G3, addend);
433 o(0xf2e00000 | r); // movk x(rt),#0,lsl #48
434 }
435 else {
436 greloca(cur_text_section, sym, ind, R_AARCH64_ADR_PREL_PG_HI21, addend);
437 o(0x90000000 | r);
438 greloca(cur_text_section, sym, ind, R_AARCH64_ADD_ABS_LO12_NC, addend);
439 o(0x91000000 | r | r << 5);
440 }
441 }
442
443 ST_FUNC void load(int r, SValue *sv)
444 {
445 int svtt = sv->type.t;
446 int svr = sv->r & ~VT_LVAL_TYPE;
447 int svrv = svr & VT_VALMASK;
448 uint64_t svcul = (int32_t)sv->c.ul;
449
450 if (svr == (VT_LOCAL | VT_LVAL)) {
451 if (IS_FREG(r))
452 gen_fload(arm64_type_size(svtt), fltr(r), 29, svcul);
453 else
454 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
455 intr(r), 29, svcul);
456 return;
457 }
458
459 if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
460 if (IS_FREG(r))
461 gen_fload(arm64_type_size(svtt),
462 fltr(r), intr(svrv), 0);
463 else
464 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
465 intr(r), intr(svrv), 0);
466 return;
467 }
468
469 if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
470 gen_addr(30, sv->sym, svcul); // use x30 for address
471 if (IS_FREG(r))
472 gen_fload(arm64_type_size(svtt), fltr(r), 30, 0);
473 else
474 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
475 intr(r), 30, 0);
476 return;
477 }
478
479 if (svr == (VT_CONST | VT_SYM)) {
480 gen_addr(intr(r), sv->sym, svcul);
481 return;
482 }
483
484 if (svr == VT_CONST) {
485 if ((svtt & VT_BTYPE) != VT_VOID)
486 arm64_movimm(intr(r),
487 arm64_type_size(svtt) == 3 ? sv->c.ull : svcul);
488 return;
489 }
490
491 if (svr < VT_CONST) {
492 if (IS_FREG(r) && IS_FREG(svr))
493 if (svtt == VT_LDOUBLE)
494 o(0x4ea01c00 | fltr(r) | fltr(svr) << 5);
495 // mov v(r).16b,v(svr).16b
496 else
497 o(0x1e604000 | fltr(r) | fltr(svr) << 5); // fmov d(r),d(svr)
498 else if (!IS_FREG(r) && !IS_FREG(svr))
499 o(0xaa0003e0 | intr(r) | intr(svr) << 16); // mov x(r),x(svr)
500 else
501 assert(0);
502 return;
503 }
504
505 if (svr == VT_LOCAL) {
506 if (-svcul < 0x1000)
507 o(0xd10003a0 | intr(r) | -svcul << 10); // sub x(r),x29,#...
508 else {
509 arm64_movimm(30, -svcul); // use x30 for offset
510 o(0xcb0003a0 | intr(r) | 30 << 16); // sub x(r),x29,x30
511 }
512 return;
513 }
514
515 if (svr == VT_JMP || svr == VT_JMPI) {
516 int t = (svr == VT_JMPI);
517 arm64_movimm(intr(r), t);
518 o(0x14000002); // b .+8
519 gsym(svcul);
520 arm64_movimm(intr(r), t ^ 1);
521 return;
522 }
523
524 if (svr == (VT_LLOCAL | VT_LVAL)) {
525 gen_load(0, 3, 30, 29, svcul); // use x30 for offset
526 if (IS_FREG(r))
527 gen_fload(arm64_type_size(svtt), fltr(r), 30, 0);
528 else
529 gen_load(!(svtt & VT_UNSIGNED), arm64_type_size(svtt),
530 intr(r), 30, 0);
531 return;
532 }
533
534 printf("load(%x, (%x, %x, %llx))\n", r, svtt, sv->r, (long long)svcul);
535 assert(0);
536 }
537
538 ST_FUNC void store(int r, SValue *sv)
539 {
540 int svtt = sv->type.t;
541 int svr = sv->r & ~VT_LVAL_TYPE;
542 int svrv = svr & VT_VALMASK;
543 uint64_t svcul = (int32_t)sv->c.ul;
544
545 if (svr == (VT_LOCAL | VT_LVAL)) {
546 if (IS_FREG(r))
547 gen_fstore(arm64_type_size(svtt), fltr(r), 29, svcul);
548 else
549 gen_store(arm64_type_size(svtt), intr(r), 29, svcul);
550 return;
551 }
552
553 if ((svr & ~VT_VALMASK) == VT_LVAL && svrv < VT_CONST) {
554 if (IS_FREG(r))
555 gen_fstore(arm64_type_size(svtt), fltr(r), intr(svrv), 0);
556 else
557 gen_store(arm64_type_size(svtt), intr(r), intr(svrv), 0);
558 return;
559 }
560
561 if (svr == (VT_CONST | VT_LVAL | VT_SYM)) {
562 gen_addr(30, sv->sym, svcul); // use x30 for address
563 if (IS_FREG(r))
564 gen_fstore(arm64_type_size(svtt), fltr(r), 30, 0);
565 else
566 gen_store(arm64_type_size(svtt), intr(r), 30, 0);
567 return;
568 }
569
570 printf("store(%x, (%x, %x, %llx))\n", r, svtt, sv->r, (long long)svcul);
571 assert(0);
572 }
573
574 static void arm64_gen_bl_or_b(int b)
575 {
576 if ((vtop->r & (VT_VALMASK | VT_LVAL)) == VT_CONST) {
577 assert(!b);
578 if (vtop->r & VT_SYM)
579 greloc(cur_text_section, vtop->sym, ind, R_AARCH64_CALL26);
580 else
581 assert(0);
582 o(0x94000000); // bl .
583 }
584 else
585 o(0xd61f0000 | !b << 21 | intr(gv(RC_R30)) << 5); // br/blr
586 }
587
588 static int arm64_hfa_aux(CType *type, int *fsize, int num)
589 {
590 if (is_float(type->t)) {
591 int a, n = type_size(type, &a);
592 if (num >= 4 || (*fsize && *fsize != n))
593 return -1;
594 *fsize = n;
595 return num + 1;
596 }
597 else if ((type->t & VT_BTYPE) == VT_STRUCT) {
598 int is_struct = 0; // rather than union
599 Sym *field;
600 for (field = type->ref->next; field; field = field->next)
601 if (field->c) {
602 is_struct = 1;
603 break;
604 }
605 if (is_struct) {
606 int num0 = num;
607 for (field = type->ref->next; field; field = field->next) {
608 if (field->c != (num - num0) * *fsize)
609 return -1;
610 num = arm64_hfa_aux(&field->type, fsize, num);
611 if (num == -1)
612 return -1;
613 }
614 if (type->ref->c != (num - num0) * *fsize)
615 return -1;
616 return num;
617 }
618 else { // union
619 int num0 = num;
620 for (field = type->ref->next; field; field = field->next) {
621 int num1 = arm64_hfa_aux(&field->type, fsize, num0);
622 if (num1 == -1)
623 return -1;
624 num = num1 < num ? num : num1;
625 }
626 if (type->ref->c != (num - num0) * *fsize)
627 return -1;
628 return num;
629 }
630 }
631 else if (type->t & VT_ARRAY) {
632 int num1;
633 if (!type->ref->c)
634 return num;
635 num1 = arm64_hfa_aux(&type->ref->type, fsize, num);
636 if (num1 == -1 || (num1 != num && type->ref->c > 4))
637 return -1;
638 num1 = num + type->ref->c * (num1 - num);
639 if (num1 > 4)
640 return -1;
641 return num1;
642 }
643 return -1;
644 }
645
646 static int arm64_hfa(CType *type, int *fsize)
647 {
648 if ((type->t & VT_BTYPE) == VT_STRUCT || (type->t & VT_ARRAY)) {
649 int sz = 0;
650 int n = arm64_hfa_aux(type, &sz, 0);
651 if (0 < n && n <= 4) {
652 if (fsize)
653 *fsize = sz;
654 return n;
655 }
656 }
657 return 0;
658 }
659
660 static unsigned long arm64_pcs_aux(int n, CType **type, unsigned long *a)
661 {
662 int nx = 0; // next integer register
663 int nv = 0; // next vector register
664 unsigned long ns = 32; // next stack offset
665 int i;
666
667 for (i = 0; i < n; i++) {
668 int hfa = arm64_hfa(type[i], 0);
669 int size, align;
670
671 if ((type[i]->t & VT_ARRAY) ||
672 (type[i]->t & VT_BTYPE) == VT_FUNC)
673 size = align = 8;
674 else
675 size = type_size(type[i], &align);
676
677 if (hfa)
678 // B.2
679 ;
680 else if (size > 16) {
681 // B.3: replace with pointer
682 if (nx < 8)
683 a[i] = nx++ << 1 | 1;
684 else {
685 ns = (ns + 7) & ~7;
686 a[i] = ns | 1;
687 ns += 8;
688 }
689 continue;
690 }
691 else if ((type[i]->t & VT_BTYPE) == VT_STRUCT)
692 // B.4
693 size = (size + 7) & ~7;
694
695 // C.1
696 if (is_float(type[i]->t) && nv < 8) {
697 a[i] = 16 + (nv++ << 1);
698 continue;
699 }
700
701 // C.2
702 if (hfa && nv + hfa <= 8) {
703 a[i] = 16 + (nv << 1);
704 nv += hfa;
705 continue;
706 }
707
708 // C.3
709 if (hfa) {
710 nv = 8;
711 size = (size + 7) & ~7;
712 }
713
714 // C.4
715 if (hfa || (type[i]->t & VT_BTYPE) == VT_LDOUBLE) {
716 ns = (ns + 7) & ~7;
717 ns = (ns + align - 1) & -align;
718 }
719
720 // C.5
721 if ((type[i]->t & VT_BTYPE) == VT_FLOAT)
722 size = 8;
723
724 // C.6
725 if (hfa || is_float(type[i]->t)) {
726 a[i] = ns;
727 ns += size;
728 continue;
729 }
730
731 // C.7
732 if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size <= 8 && nx < 8) {
733 a[i] = nx++ << 1;
734 continue;
735 }
736
737 // C.8
738 if (align == 16)
739 nx = (nx + 1) & ~1;
740
741 // C.9
742 if ((type[i]->t & VT_BTYPE) != VT_STRUCT && size == 16 && nx < 7) {
743 a[i] = nx << 1;
744 nx += 2;
745 continue;
746 }
747
748 // C.10
749 if ((type[i]->t & VT_BTYPE) == VT_STRUCT && size <= (8 - nx) * 8) {
750 a[i] = nx << 1;
751 nx += (size + 7) >> 3;
752 continue;
753 }
754
755 // C.11
756 nx = 8;
757
758 // C.12
759 ns = (ns + 7) & ~7;
760 ns = (ns + align - 1) & -align;
761
762 // C.13
763 if ((type[i]->t & VT_BTYPE) == VT_STRUCT) {
764 a[i] = ns;
765 ns += size;
766 continue;
767 }
768
769 // C.14
770 if (size < 8)
771 size = 8;
772
773 // C.15
774 a[i] = ns;
775 ns += size;
776 }
777
778 return ns - 32;
779 }
780
781 static unsigned long arm64_pcs(int n, CType **type, unsigned long *a)
782 {
783 unsigned long stack;
784
785 // Return type:
786 if ((type[0]->t & VT_BTYPE) == VT_VOID)
787 a[0] = -1;
788 else {
789 arm64_pcs_aux(1, type, a);
790 assert(a[0] == 0 || a[0] == 1 || a[0] == 16);
791 }
792
793 // Argument types:
794 stack = arm64_pcs_aux(n, type + 1, a + 1);
795
796 if (0) {
797 int i;
798 for (i = 0; i <= n; i++) {
799 if (!i)
800 printf("arm64_pcs return: ");
801 else
802 printf("arm64_pcs arg %d: ", i);
803 if (a[i] == (unsigned long)-1)
804 printf("void\n");
805 else if (a[i] == 1 && !i)
806 printf("X8 pointer\n");
807 else if (a[i] < 16)
808 printf("X%lu%s\n", a[i] / 2, a[i] & 1 ? " pointer" : "");
809 else if (a[i] < 32)
810 printf("V%lu\n", a[i] / 2 - 8);
811 else
812 printf("stack %lu%s\n",
813 (a[i] - 32) & ~1, a[i] & 1 ? " pointer" : "");
814 }
815 }
816
817 return stack;
818 }
819
820 ST_FUNC void gfunc_call(int nb_args)
821 {
822 CType *return_type;
823 CType **t;
824 unsigned long *a, *a1;
825 unsigned long stack;
826 int i;
827
828 return_type = &vtop[-nb_args].type.ref->type;
829 if ((return_type->t & VT_BTYPE) == VT_STRUCT)
830 --nb_args;
831
832 t = tcc_malloc((nb_args + 1) * sizeof(*t));
833 a = tcc_malloc((nb_args + 1) * sizeof(*a));
834 a1 = tcc_malloc((nb_args + 1) * sizeof(*a1));
835
836 t[0] = return_type;
837 for (i = 0; i < nb_args; i++)
838 t[nb_args - i] = &vtop[-i].type;
839
840 stack = arm64_pcs(nb_args, t, a);
841
842 // Allocate space for structs replaced by pointer:
843 for (i = nb_args; i; i--)
844 if (a[i] & 1) {
845 SValue *arg = &vtop[i - nb_args];
846 int align, size = type_size(&arg->type, &align);
847 assert((arg->type.t & VT_BTYPE) == VT_STRUCT);
848 stack = (stack + align - 1) & -align;
849 a1[i] = stack;
850 stack += size;
851 }
852
853 stack = (stack + 15) >> 4 << 4;
854
855 assert(stack < 0x1000);
856 if (stack)
857 o(0xd10003ff | stack << 10); // sub sp,sp,#(n)
858
859 // First pass: set all values on stack
860 for (i = nb_args; i; i--) {
861 vpushv(vtop - nb_args + i);
862
863 if (a[i] & 1) {
864 // struct replaced by pointer
865 int r = get_reg(RC_INT);
866 gen_stack_addr(intr(r), a1[i]);
867 vset(&vtop->type, r | VT_LVAL, 0);
868 vswap();
869 vstore();
870 if (a[i] >= 32) {
871 // pointer on stack
872 r = get_reg(RC_INT);
873 gen_stack_addr(intr(r), a1[i]);
874 gen_store(3, intr(r), 31, (a[i] - 32) >> 1 << 1);
875 }
876 }
877 else if (a[i] >= 32) {
878 // value on stack
879 if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
880 int r = get_reg(RC_INT);
881 gen_stack_addr(intr(r), a[i] - 32);
882 vset(&vtop->type, r | VT_LVAL, 0);
883 vswap();
884 vstore();
885 }
886 else if (is_float(vtop->type.t)) {
887 gv(RC_FLOAT);
888 gen_fstore(arm64_type_size(vtop[0].type.t),
889 fltr(vtop[0].r), 31, a[i] - 32);
890 }
891 else {
892 gv(RC_INT);
893 gen_store(arm64_type_size(vtop[0].type.t),
894 intr(vtop[0].r), 31, a[i] - 32);
895 }
896 }
897
898 --vtop;
899 }
900
901 // Second pass: assign values to registers
902 for (i = nb_args; i; i--, vtop--) {
903 if (a[i] < 16 && !(a[i] & 1)) {
904 // value in general-purpose registers
905 if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
906 int align, size = type_size(&vtop->type, &align);
907 vtop->type.t = VT_PTR;
908 gaddrof();
909 gv(RC_R(a[i] / 2));
910 gen_sload(a[i] / 2, size);
911 }
912 else
913 gv(RC_R(a[i] / 2));
914 }
915 else if (a[i] < 16)
916 // struct replaced by pointer in register
917 gen_stack_addr(a[i] / 2, a1[i]);
918 else if (a[i] < 32) {
919 // value in floating-point registers
920 if ((vtop->type.t & VT_BTYPE) == VT_STRUCT) {
921 int j, sz, n = arm64_hfa(&vtop->type, &sz);
922 vtop->type.t = VT_PTR;
923 gaddrof();
924 gv(RC_R30);
925 for (j = 0; j < n; j++)
926 o(0x3d4003c0 |
927 (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
928 (a[i] / 2 - 8 + j) |
929 j << 10); // ldr ([sdq])(*),[x30,#(j * sz)]
930 }
931 else
932 gv(RC_F(a[i] / 2 - 8));
933 }
934 }
935
936 if ((return_type->t & VT_BTYPE) == VT_STRUCT) {
937 if (a[0] == 1) {
938 // indirect return: set x8 and discard the stack value
939 gv(RC_R(8));
940 --vtop;
941 }
942 else
943 // return in registers: keep the address for after the call
944 vswap();
945 }
946
947 save_regs(0);
948 arm64_gen_bl_or_b(0);
949 --vtop;
950 if (stack)
951 o(0x910003ff | stack << 10); // add sp,sp,#(n)
952
953 {
954 int rt = return_type->t;
955 int bt = rt & VT_BTYPE;
956 if (bt == VT_BYTE || bt == VT_SHORT)
957 // Promote small integers:
958 o(0x13001c00 | (bt == VT_SHORT) << 13 |
959 !!(rt & VT_UNSIGNED) << 30); // [su]xt[bh] w0,w0
960 else if (bt == VT_STRUCT && !(a[0] & 1)) {
961 // A struct was returned in registers, so write it out:
962 gv(RC_R(8));
963 --vtop;
964 if (a[0] == 0) {
965 int align, size = type_size(return_type, &align);
966 assert(size <= 16);
967 if (size > 8)
968 o(0xa9000500); // stp x0,x1,[x8]
969 else if (size)
970 gen_store(size > 4 ? 3 : size > 2 ? 2 : size > 1,
971 0, 8, 0);
972
973 }
974 else if (a[0] == 16) {
975 int j, sz, n = arm64_hfa(return_type, &sz);
976 for (j = 0; j < n; j++)
977 o(0x3d000100 |
978 (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
979 (a[i] / 2 - 8 + j) |
980 j << 10); // str ([sdq])(*),[x8,#(j * sz)]
981 }
982 }
983 }
984
985 tcc_free(a1);
986 tcc_free(a);
987 tcc_free(t);
988 }
989
990 static unsigned long arm64_func_va_list_stack;
991 static int arm64_func_va_list_gr_offs;
992 static int arm64_func_va_list_vr_offs;
993 static int arm64_func_sub_sp_offset;
994
995 ST_FUNC void gfunc_prolog(CType *func_type)
996 {
997 int n = 0;
998 int i = 0;
999 Sym *sym;
1000 CType **t;
1001 unsigned long *a;
1002
1003 // Why doesn't the caller (gen_function) set func_vt?
1004 func_vt = func_type->ref->type;
1005 func_vc = 144; // offset of where x8 is stored
1006
1007 for (sym = func_type->ref; sym; sym = sym->next)
1008 ++n;
1009 t = tcc_malloc(n * sizeof(*t));
1010 a = tcc_malloc(n * sizeof(*a));
1011
1012 for (sym = func_type->ref; sym; sym = sym->next)
1013 t[i++] = &sym->type;
1014
1015 arm64_func_va_list_stack = arm64_pcs(n - 1, t, a);
1016
1017 o(0xa9b27bfd); // stp x29,x30,[sp,#-224]!
1018 o(0xad0087e0); // stp q0,q1,[sp,#16]
1019 o(0xad018fe2); // stp q2,q3,[sp,#48]
1020 o(0xad0297e4); // stp q4,q5,[sp,#80]
1021 o(0xad039fe6); // stp q6,q7,[sp,#112]
1022 o(0xa90923e8); // stp x8,x8,[sp,#144]
1023 o(0xa90a07e0); // stp x0,x1,[sp,#160]
1024 o(0xa90b0fe2); // stp x2,x3,[sp,#176]
1025 o(0xa90c17e4); // stp x4,x5,[sp,#192]
1026 o(0xa90d1fe6); // stp x6,x7,[sp,#208]
1027
1028 arm64_func_va_list_gr_offs = -64;
1029 arm64_func_va_list_vr_offs = -128;
1030
1031 for (i = 1, sym = func_type->ref->next; sym; i++, sym = sym->next) {
1032 int off = (a[i] < 16 ? 160 + a[i] / 2 * 8 :
1033 a[i] < 32 ? 16 + (a[i] - 16) / 2 * 16 :
1034 224 + ((a[i] - 32) >> 1 << 1));
1035 sym_push(sym->v & ~SYM_FIELD, &sym->type,
1036 (a[i] & 1 ? VT_LLOCAL : VT_LOCAL) | lvalue_type(sym->type.t),
1037 off);
1038
1039 if (a[i] < 16) {
1040 int align, size = type_size(&sym->type, &align);
1041 arm64_func_va_list_gr_offs = (a[i] / 2 - 7 +
1042 (!(a[i] & 1) && size > 8)) * 8;
1043 }
1044 else if (a[i] < 32) {
1045 int hfa = arm64_hfa(&sym->type, 0);
1046 arm64_func_va_list_vr_offs = (a[i] / 2 - 16 +
1047 (hfa ? hfa : 1)) * 16;
1048 }
1049
1050 // HFAs of float and double need to be written differently:
1051 if (16 <= a[i] && a[i] < 32 && (sym->type.t & VT_BTYPE) == VT_STRUCT) {
1052 int j, sz, k = arm64_hfa(&sym->type, &sz);
1053 if (sz < 16)
1054 for (j = 0; j < k; j++) {
1055 o(0x3d0003e0 | -(sz & 8) << 27 | (sz & 4) << 29 |
1056 ((a[i] - 16) / 2 + j) | (off / sz + j) << 10);
1057 // str ([sdq])(*),[sp,#(j * sz)]
1058 }
1059 }
1060 }
1061
1062 tcc_free(a);
1063 tcc_free(t);
1064
1065 o(0x910003fd); // mov x29,sp
1066 arm64_func_sub_sp_offset = ind;
1067 // In gfunc_epilog these will be replaced with code to decrement SP:
1068 o(0xd503201f); // nop
1069 o(0xd503201f); // nop
1070 loc = 0;
1071 }
1072
1073 ST_FUNC void gen_va_start(void)
1074 {
1075 int r;
1076 --vtop; // we don't need the "arg"
1077 gaddrof();
1078 r = intr(gv(RC_INT));
1079
1080 if (arm64_func_va_list_stack) {
1081 //xx could use add (immediate) here
1082 arm64_movimm(30, arm64_func_va_list_stack + 224);
1083 o(0x8b1e03be); // add x30,x29,x30
1084 }
1085 else
1086 o(0x910383be); // add x30,x29,#224
1087 o(0xf900001e | r << 5); // str x30,[x(r)]
1088
1089 if (arm64_func_va_list_gr_offs) {
1090 if (arm64_func_va_list_stack)
1091 o(0x910383be); // add x30,x29,#224
1092 o(0xf900041e | r << 5); // str x30,[x(r),#8]
1093 }
1094
1095 if (arm64_func_va_list_vr_offs) {
1096 o(0x910243be); // add x30,x29,#144
1097 o(0xf900081e | r << 5); // str x30,[x(r),#16]
1098 }
1099
1100 arm64_movimm(30, arm64_func_va_list_gr_offs);
1101 o(0xb900181e | r << 5); // str w30,[x(r),#24]
1102
1103 arm64_movimm(30, arm64_func_va_list_vr_offs);
1104 o(0xb9001c1e | r << 5); // str w30,[x(r),#28]
1105
1106 --vtop;
1107 }
1108
1109 ST_FUNC void gen_va_arg(CType *t)
1110 {
1111 int align, size = type_size(t, &align);
1112 int fsize, hfa = arm64_hfa(t, &fsize);
1113 uint32_t r0, r1;
1114
1115 if (is_float(t->t)) {
1116 hfa = 1;
1117 fsize = size;
1118 }
1119
1120 gaddrof();
1121 r0 = intr(gv(RC_INT));
1122 r1 = get_reg(RC_INT);
1123 vtop[0].r = r1 | lvalue_type(t->t);
1124 r1 = intr(r1);
1125
1126 if (!hfa) {
1127 uint32_t n = size > 16 ? 8 : (size + 7) & -8;
1128 o(0xb940181e | r0 << 5); // ldr w30,[x(r0),#24] // __gr_offs
1129 if (align == 16) {
1130 assert(0); // this path untested but needed for __uint128_t
1131 o(0x11003fde); // add w30,w30,#15
1132 o(0x121c6fde); // and w30,w30,#-16
1133 }
1134 o(0x310003c0 | r1 | n << 10); // adds w(r1),w30,#(n)
1135 o(0x540000ad); // b.le .+20
1136 o(0xf9400000 | r1 | r0 << 5); // ldr x(r1),[x(r0)] // __stack
1137 o(0x9100001e | r1 << 5 | n << 10); // add x30,x(r1),#(n)
1138 o(0xf900001e | r0 << 5); // str x30,[x(r0)] // __stack
1139 o(0x14000004); // b .+16
1140 o(0xb9001800 | r1 | r0 << 5); // str w(r1),[x(r0),#24] // __gr_offs
1141 o(0xf9400400 | r1 | r0 << 5); // ldr x(r1),[x(r0),#8] // __gr_top
1142 o(0x8b3ec000 | r1 | r1 << 5); // add x(r1),x(r1),w30,sxtw
1143 if (size > 16)
1144 o(0xf9400000 | r1 | r1 << 5); // ldr x(r1),[x(r1)]
1145 }
1146 else {
1147 uint32_t rsz = hfa << 4;
1148 uint32_t ssz = (size + 7) & -(uint32_t)8;
1149 uint32_t b1, b2;
1150 o(0xb9401c1e | r0 << 5); // ldr w30,[x(r0),#28] // __vr_offs
1151 o(0x310003c0 | r1 | rsz << 10); // adds w(r1),w30,#(rsz)
1152 b1 = ind; o(0x5400000d); // b.le lab1
1153 o(0xf9400000 | r1 | r0 << 5); // ldr x(r1),[x(r0)] // __stack
1154 if (fsize == 16) {
1155 o(0x91003c00 | r1 | r1 << 5); // add x(r1),x(r1),#15
1156 o(0x927cec00 | r1 | r1 << 5); // and x(r1),x(r1),#-16
1157 }
1158 o(0x9100001e | r1 << 5 | ssz << 10); // add x30,x(r1),#(ssz)
1159 o(0xf900001e | r0 << 5); // str x30,[x(r0)] // __stack
1160 b2 = ind; o(0x14000000); // b lab2
1161 // lab1:
1162 *(uint32_t *)(cur_text_section->data + b1) =
1163 (0x5400000d | (ind - b1) << 3);
1164 o(0xb9001c00 | r1 | r0 << 5); // str w(r1),[x(r0),#28] // __vr_offs
1165 o(0xf9400800 | r1 | r0 << 5); // ldr x(r1),[x(r0),#16] // __vr_top
1166 if (hfa == 1 || fsize == 16)
1167 o(0x8b3ec000 | r1 | r1 << 5); // add x(r1),x(r1),w30,sxtw
1168 else {
1169 // We need to change the layout of this HFA.
1170 // Get some space on the stack using global variable "loc":
1171 loc = (loc - size) & -(uint32_t)align;
1172 o(0x8b3ec000 | 30 | r1 << 5); // add x30,x(r1),w30,sxtw
1173 arm64_movimm(r1, loc);
1174 o(0x8b0003a0 | r1 | r1 << 16); // add x(r1),x29,x(r1)
1175 o(0x4c402bdc | (uint32_t)fsize << 7 |
1176 (uint32_t)(hfa == 2) << 15 |
1177 (uint32_t)(hfa == 3) << 14); // ld1 {v28.(4s|2d),...},[x30]
1178 o(0x0d00801c | r1 << 5 | (fsize == 8) << 10 |
1179 (uint32_t)(hfa != 2) << 13 |
1180 (uint32_t)(hfa != 3) << 21); // st(hfa) {v28.(s|d),...}[0],[x(r1)]
1181 }
1182 // lab2:
1183 *(uint32_t *)(cur_text_section->data + b2) =
1184 (0x14000000 | (ind - b2) >> 2);
1185 }
1186 }
1187
1188 ST_FUNC int gfunc_sret(CType *vt, int variadic, CType *ret, int *align)
1189 {
1190 return 0;
1191 }
1192
1193 ST_FUNC void greturn(void)
1194 {
1195 CType *t = &func_vt;
1196 unsigned long a;
1197
1198 arm64_pcs(0, &t, &a);
1199 switch (a) {
1200 case -1:
1201 break;
1202 case 0:
1203 if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
1204 int align, size = type_size(&func_vt, &align);
1205 gaddrof();
1206 gv(RC_R(0));
1207 gen_sload(0, size);
1208 }
1209 else
1210 gv(RC_IRET);
1211 break;
1212 case 1: {
1213 CType type = func_vt;
1214 mk_pointer(&type);
1215 vset(&type, VT_LOCAL | VT_LVAL, func_vc);
1216 indir();
1217 vswap();
1218 vstore();
1219 break;
1220 }
1221 case 16:
1222 if ((func_vt.t & VT_BTYPE) == VT_STRUCT) {
1223 int j, sz, n = arm64_hfa(&vtop->type, &sz);
1224 gaddrof();
1225 gv(RC_R(0));
1226 for (j = 0; j < n; j++)
1227 o(0x3d400000 |
1228 (sz & 16) << 19 | -(sz & 8) << 27 | (sz & 4) << 29 |
1229 j | j << 10); // ldr ([sdq])(*),[x0,#(j * sz)]
1230 }
1231 else
1232 gv(RC_FRET);
1233 break;
1234 default:
1235 assert(0);
1236 }
1237 }
1238
1239 ST_FUNC void gfunc_epilog(void)
1240 {
1241 if (loc) {
1242 // Insert instructions to subtract size of stack frame from SP.
1243 uint32_t *ptr =
1244 (uint32_t *)(cur_text_section->data + arm64_func_sub_sp_offset);
1245 uint64_t diff = (-loc + 15) & ~15;
1246 if (!(diff >> 24)) {
1247 if (diff & 0xfff) // sub sp,sp,#(diff & 0xfff)
1248 ptr[0] = 0xd10003ff | (diff & 0xfff) << 10;
1249 if (diff >> 12) // sub sp,sp,#(diff >> 12),lsl #12
1250 ptr[1] = 0xd14003ff | (diff >> 12) << 10;
1251 }
1252 else {
1253 // In this case we may subtract more than necessary,
1254 // but always less than 17/16 of what we were aiming for.
1255 int i = 0;
1256 int j = 0;
1257 while (diff >> 20) {
1258 diff = (diff + 0xffff) >> 16;
1259 ++i;
1260 }
1261 while (diff >> 16) {
1262 diff = (diff + 1) >> 1;
1263 ++j;
1264 }
1265 ptr[0] = 0xd2800010 | diff << 5 | i << 21;
1266 // mov x16,#(diff),lsl #(16 * i)
1267 ptr[1] = 0xcb3063ff | j << 10;
1268 // sub sp,sp,x16,lsl #(j)
1269 }
1270 }
1271 o(0x910003bf); // mov sp,x29
1272 o(0xa8ce7bfd); // ldp x29,x30,[sp],#224
1273
1274 o(0xd65f03c0); // ret
1275 }
1276
1277 // Generate forward branch to label:
1278 ST_FUNC int gjmp(int t)
1279 {
1280 int r = ind;
1281 o(t);
1282 return r;
1283 }
1284
1285 // Generate branch to known address:
1286 ST_FUNC void gjmp_addr(int a)
1287 {
1288 assert(a - ind + 0x8000000 < 0x10000000);
1289 o(0x14000000 | ((a - ind) >> 2 & 0x3ffffff));
1290 }
1291
1292 ST_FUNC int gtst(int inv, int t)
1293 {
1294 int bt = vtop->type.t & VT_BTYPE;
1295 if (bt == VT_LDOUBLE) {
1296 int a, b, f = fltr(gv(RC_FLOAT));
1297 a = get_reg(RC_INT);
1298 vpushi(0);
1299 vtop[0].r = a;
1300 b = get_reg(RC_INT);
1301 a = intr(a);
1302 b = intr(b);
1303 o(0x4e083c00 | a | f << 5); // mov x(a),v(f).d[0]
1304 o(0x4e183c00 | b | f << 5); // mov x(b),v(f).d[1]
1305 o(0xaa000400 | a | a << 5 | b << 16); // orr x(a),x(a),x(b),lsl #1
1306 o(0xb4000040 | a | !!inv << 24); // cbz/cbnz x(a),.+8
1307 --vtop;
1308 }
1309 else if (bt == VT_FLOAT || bt == VT_DOUBLE) {
1310 int a = fltr(gv(RC_FLOAT));
1311 o(0x1e202008 | a << 5 | (bt != VT_FLOAT) << 22); // fcmp
1312 o(0x54000040 | !!inv); // b.eq/b.ne .+8
1313 }
1314 else {
1315 int ll = (bt == VT_PTR || bt == VT_LLONG);
1316 int a = intr(gv(RC_INT));
1317 o(0x34000040 | a | !!inv << 24 | ll << 31); // cbz/cbnz wA,.+8
1318 }
1319 --vtop;
1320 return gjmp(t);
1321 }
1322
1323 static void arm64_gen_opil(int op, int l)
1324 {
1325 int x, a, b;
1326 gv2(RC_INT, RC_INT);
1327 assert(vtop[-1].r < VT_CONST && vtop[0].r < VT_CONST);
1328 a = intr(vtop[-1].r);
1329 b = intr(vtop[0].r);
1330 vtop -= 2;
1331 x = get_reg(RC_INT);
1332 ++vtop;
1333 vtop[0].r = x;
1334 x = intr(x);
1335
1336 switch (op) {
1337 case '%':
1338 // Use x30 for quotient:
1339 o(0x1ac00c00 | l << 31 | 30 | a << 5 | b << 16); // sdiv
1340 o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
1341 break;
1342 case '&':
1343 o(0x0a000000 | l << 31 | x | a << 5 | b << 16); // and
1344 break;
1345 case '*':
1346 o(0x1b007c00 | l << 31 | x | a << 5 | b << 16); // mul
1347 break;
1348 case '+':
1349 o(0x0b000000 | l << 31 | x | a << 5 | b << 16); // add
1350 break;
1351 case '-':
1352 o(0x4b000000 | l << 31 | x | a << 5 | b << 16); // sub
1353 break;
1354 case '/':
1355 o(0x1ac00c00 | l << 31 | x | a << 5 | b << 16); // sdiv
1356 break;
1357 case '^':
1358 o(0x4a000000 | l << 31 | x | a << 5 | b << 16); // eor
1359 break;
1360 case '|':
1361 o(0x2a000000 | l << 31 | x | a << 5 | b << 16); // orr
1362 break;
1363 case TOK_EQ:
1364 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1365 o(0x1a9f17e0 | x); // cset wA,eq
1366 break;
1367 case TOK_GE:
1368 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1369 o(0x1a9fb7e0 | x); // cset wA,ge
1370 break;
1371 case TOK_GT:
1372 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1373 o(0x1a9fd7e0 | x); // cset wA,gt
1374 break;
1375 case TOK_LE:
1376 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1377 o(0x1a9fc7e0 | x); // cset wA,le
1378 break;
1379 case TOK_LT:
1380 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1381 o(0x1a9fa7e0 | x); // cset wA,lt
1382 break;
1383 case TOK_NE:
1384 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1385 o(0x1a9f07e0 | x); // cset wA,ne
1386 break;
1387 case TOK_SAR:
1388 o(0x1ac02800 | l << 31 | x | a << 5 | b << 16); // asr
1389 break;
1390 case TOK_SHL:
1391 o(0x1ac02000 | l << 31 | x | a << 5 | b << 16); // lsl
1392 break;
1393 case TOK_SHR:
1394 o(0x1ac02400 | l << 31 | x | a << 5 | b << 16); // lsr
1395 break;
1396 case TOK_UDIV:
1397 case TOK_PDIV:
1398 o(0x1ac00800 | l << 31 | x | a << 5 | b << 16); // udiv
1399 break;
1400 case TOK_UGE:
1401 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1402 o(0x1a9f37e0 | x); // cset wA,cs
1403 break;
1404 case TOK_UGT:
1405 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1406 o(0x1a9f97e0 | x); // cset wA,hi
1407 break;
1408 case TOK_ULT:
1409 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1410 o(0x1a9f27e0 | x); // cset wA,cc
1411 break;
1412 case TOK_ULE:
1413 o(0x6b00001f | l << 31 | a << 5 | b << 16); // cmp
1414 o(0x1a9f87e0 | x); // cset wA,ls
1415 break;
1416 case TOK_UMOD:
1417 // Use x30 for quotient:
1418 o(0x1ac00800 | l << 31 | 30 | a << 5 | b << 16); // udiv
1419 o(0x1b008000 | l << 31 | x | 30 << 5 | b << 16 | a << 10); // msub
1420 break;
1421 default:
1422 assert(0);
1423 }
1424 }
1425
1426 ST_FUNC void gen_opi(int op)
1427 {
1428 arm64_gen_opil(op, 0);
1429 }
1430
1431 ST_FUNC void gen_opl(int op)
1432 {
1433 arm64_gen_opil(op, 1);
1434 }
1435
1436 ST_FUNC void gen_opf(int op)
1437 {
1438 int x, a, b, dbl;
1439
1440 if (vtop[0].type.t == VT_LDOUBLE) {
1441 CType type = vtop[0].type;
1442 int func = 0;
1443 int cond = -1;
1444 switch (op) {
1445 case '*': func = TOK___multf3; break;
1446 case '+': func = TOK___addtf3; break;
1447 case '-': func = TOK___subtf3; break;
1448 case '/': func = TOK___divtf3; break;
1449 case TOK_EQ: func = TOK___eqtf2; cond = 1; break;
1450 case TOK_NE: func = TOK___netf2; cond = 0; break;
1451 case TOK_LT: func = TOK___lttf2; cond = 10; break;
1452 case TOK_GE: func = TOK___getf2; cond = 11; break;
1453 case TOK_LE: func = TOK___letf2; cond = 12; break;
1454 case TOK_GT: func = TOK___gttf2; cond = 13; break;
1455 default: assert(0); break;
1456 }
1457 vpush_global_sym(&func_old_type, func);
1458 vrott(3);
1459 gfunc_call(2);
1460 vpushi(0);
1461 vtop->r = cond < 0 ? REG_FRET : REG_IRET;
1462 if (cond < 0)
1463 vtop->type = type;
1464 else {
1465 o(0x7100001f); // cmp w0,#0
1466 o(0x1a9f07e0 | cond << 12); // cset w0,(cond)
1467 }
1468 return;
1469 }
1470
1471 dbl = vtop[0].type.t != VT_FLOAT;
1472 gv2(RC_FLOAT, RC_FLOAT);
1473 assert(vtop[-1].r < VT_CONST && vtop[0].r < VT_CONST);
1474 a = fltr(vtop[-1].r);
1475 b = fltr(vtop[0].r);
1476 vtop -= 2;
1477 switch (op) {
1478 case TOK_EQ: case TOK_NE:
1479 case TOK_LT: case TOK_GE: case TOK_LE: case TOK_GT:
1480 x = get_reg(RC_INT);
1481 ++vtop;
1482 vtop[0].r = x;
1483 x = intr(x);
1484 break;
1485 default:
1486 x = get_reg(RC_FLOAT);
1487 ++vtop;
1488 vtop[0].r = x;
1489 x = fltr(x);
1490 break;
1491 }
1492
1493 switch (op) {
1494 case '*':
1495 o(0x1e200800 | dbl << 22 | x | a << 5 | b << 16); // fmul
1496 break;
1497 case '+':
1498 o(0x1e202800 | dbl << 22 | x | a << 5 | b << 16); // fadd
1499 break;
1500 case '-':
1501 o(0x1e203800 | dbl << 22 | x | a << 5 | b << 16); // fsub
1502 break;
1503 case '/':
1504 o(0x1e201800 | dbl << 22 | x | a << 5 | b << 16); // fdiv
1505 break;
1506 case TOK_EQ:
1507 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1508 o(0x1a9f17e0 | x); // cset w(x),eq
1509 break;
1510 case TOK_GE:
1511 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1512 o(0x1a9fb7e0 | x); // cset w(x),ge
1513 break;
1514 case TOK_GT:
1515 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1516 o(0x1a9fd7e0 | x); // cset w(x),gt
1517 break;
1518 case TOK_LE:
1519 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1520 o(0x1a9f87e0 | x); // cset w(x),ls
1521 break;
1522 case TOK_LT:
1523 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1524 o(0x1a9f57e0 | x); // cset w(x),mi
1525 break;
1526 case TOK_NE:
1527 o(0x1e202000 | dbl << 22 | a << 5 | b << 16); // fcmp
1528 o(0x1a9f07e0 | x); // cset w(x),ne
1529 break;
1530 default:
1531 assert(0);
1532 }
1533 }
1534
1535 // Generate sign extension from 32 to 64 bits:
1536 ST_FUNC void gen_cvt_sxtw(void)
1537 {
1538 int r = intr(gv(RC_INT));
1539 o(0x93407c00 | r | r << 5); // sxtw x(r),w(r)
1540 }
1541
1542 ST_FUNC void gen_cvt_itof(int t)
1543 {
1544 if (t == VT_LDOUBLE) {
1545 int f = vtop->type.t;
1546 int func = (f & VT_BTYPE) == VT_LLONG ?
1547 (f & VT_UNSIGNED ? TOK___floatunditf : TOK___floatditf) :
1548 (f & VT_UNSIGNED ? TOK___floatunsitf : TOK___floatsitf);
1549 vpush_global_sym(&func_old_type, func);
1550 vrott(2);
1551 gfunc_call(1);
1552 vpushi(0);
1553 vtop->type.t = t;
1554 vtop->r = REG_FRET;
1555 return;
1556 }
1557 else {
1558 int d, n = intr(gv(RC_INT));
1559 int s = !(vtop->type.t & VT_UNSIGNED);
1560 int l = ((vtop->type.t & VT_BTYPE) == VT_LLONG);
1561 --vtop;
1562 d = get_reg(RC_FLOAT);
1563 ++vtop;
1564 vtop[0].r = d;
1565 o(0x1e220000 | !s << 16 | (t != VT_FLOAT) << 22 | fltr(d) |
1566 l << 31 | n << 5); // [us]cvtf [sd](d),[wx](n)
1567 }
1568 }
1569
1570 ST_FUNC void gen_cvt_ftoi(int t)
1571 {
1572 if ((vtop->type.t & VT_BTYPE) == VT_LDOUBLE) {
1573 int func = (t & VT_BTYPE) == VT_LLONG ?
1574 (t & VT_UNSIGNED ? TOK___fixunstfdi : TOK___fixtfdi) :
1575 (t & VT_UNSIGNED ? TOK___fixunstfsi : TOK___fixtfsi);
1576 vpush_global_sym(&func_old_type, func);
1577 vrott(2);
1578 gfunc_call(1);
1579 vpushi(0);
1580 vtop->type.t = t;
1581 vtop->r = REG_IRET;
1582 return;
1583 }
1584 else {
1585 int d, n = fltr(gv(RC_FLOAT));
1586 int l = ((vtop->type.t & VT_BTYPE) != VT_FLOAT);
1587 --vtop;
1588 d = get_reg(RC_INT);
1589 ++vtop;
1590 vtop[0].r = d;
1591 o(0x1e380000 |
1592 !!(t & VT_UNSIGNED) << 16 |
1593 ((t & VT_BTYPE) == VT_LLONG) << 31 | intr(d) |
1594 l << 22 | n << 5); // fcvtz[su] [wx](d),[sd](n)
1595 }
1596 }
1597
1598 ST_FUNC void gen_cvt_ftof(int t)
1599 {
1600 int f = vtop[0].type.t;
1601 assert(t == VT_FLOAT || t == VT_DOUBLE || t == VT_LDOUBLE);
1602 assert(f == VT_FLOAT || f == VT_DOUBLE || f == VT_LDOUBLE);
1603 if (t == f)
1604 return;
1605
1606 if (t == VT_LDOUBLE || f == VT_LDOUBLE) {
1607 int func = (t == VT_LDOUBLE) ?
1608 (f == VT_FLOAT ? TOK___extendsftf2 : TOK___extenddftf2) :
1609 (t == VT_FLOAT ? TOK___trunctfsf2 : TOK___trunctfdf2);
1610 vpush_global_sym(&func_old_type, func);
1611 vrott(2);
1612 gfunc_call(1);
1613 vpushi(0);
1614 vtop->type.t = t;
1615 vtop->r = REG_FRET;
1616 }
1617 else {
1618 int x, a;
1619 gv(RC_FLOAT);
1620 assert(vtop[0].r < VT_CONST);
1621 a = fltr(vtop[0].r);
1622 --vtop;
1623 x = get_reg(RC_FLOAT);
1624 ++vtop;
1625 vtop[0].r = x;
1626 x = fltr(x);
1627
1628 if (f == VT_FLOAT)
1629 o(0x1e22c000 | x | a << 5); // fcvt d(x),s(a)
1630 else
1631 o(0x1e624000 | x | a << 5); // fcvt s(x),d(a)
1632 }
1633 }
1634
1635 ST_FUNC void ggoto(void)
1636 {
1637 arm64_gen_bl_or_b(1);
1638 --vtop;
1639 }
1640
1641 ST_FUNC void gen_vla_sp_save(int addr) {
1642 tcc_error("variable length arrays unsupported for this target");
1643 }
1644
1645 ST_FUNC void gen_vla_sp_restore(int addr) {
1646 tcc_error("variable length arrays unsupported for this target");
1647 }
1648
1649 ST_FUNC void gen_vla_alloc(CType *type, int align) {
1650 tcc_error("variable length arrays unsupported for this target");
1651 }
1652
1653 /* end of A64 code generator */
1654 /*************************************************************/
1655 #endif
1656 /*************************************************************/
Tiny C Compiler main repository