asmx86.c

   1 /*
   2  *  i386 specific functions for TCC assembler
   3  *
   4  *  Copyright (c) 2001, 2002 Fabrice Bellard
   5  *  Copyright (c) 2009 Frédéric Feret (x86_64 support)
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include "tcc.h"
  23
  24 /* #define NB_ASM_REGS 8 */
  25 #define MAX_OPERANDS 3
  26 #define NB_SAVED_REGS 3
  27
  28 #define TOK_ASM_first TOK_ASM_clc
  29 #define TOK_ASM_last TOK_ASM_emms
  30 #define TOK_ASM_alllast TOK_ASM_pxor
  31
  32 #define OPC_JMP        0x01  /* jmp operand */
  33 #define OPC_B          0x02  /* only used with OPC_WL */
  34 #define OPC_WL         0x04  /* accepts w, l or no suffix */
  35 #define OPC_BWL        (OPC_B | OPC_WL) /* accepts b, w, l or no suffix */
  36 #define OPC_REG        0x08 /* register is added to opcode */
  37 #define OPC_MODRM      0x10 /* modrm encoding */
  38 #define OPC_FWAIT      0x20 /* add fwait opcode */
  39 #define OPC_TEST       0x40 /* test opcodes */
  40 #define OPC_SHIFT      0x80 /* shift opcodes */
  41 #define OPC_D16      0x0100 /* generate data16 prefix */
  42 #define OPC_ARITH    0x0200 /* arithmetic opcodes */
  43 #define OPC_SHORTJMP 0x0400 /* short jmp operand */
  44 #define OPC_FARITH   0x0800 /* FPU arithmetic opcodes */
  45 #ifdef TCC_TARGET_X86_64
  46 # define OPC_WLQ     0x1000  /* accepts w, l, q or no suffix */
  47 # define OPC_BWLQ    (OPC_B | OPC_WLQ) /* accepts b, w, l, q or no suffix */
  48 # define OPC_WLX     OPC_WLQ
  49 #else
  50 # define OPC_WLX     OPC_WL
  51 #endif
  52
  53 #define OPC_GROUP_SHIFT 13
  54
  55 /* in order to compress the operand type, we use specific operands and
  56    we or only with EA  */
  57 enum {
  58     OPT_REG8=0, /* warning: value is hardcoded from TOK_ASM_xxx */
  59     OPT_REG16,  /* warning: value is hardcoded from TOK_ASM_xxx */
  60     OPT_REG32,  /* warning: value is hardcoded from TOK_ASM_xxx */
  61 #ifdef TCC_TARGET_X86_64
  62     OPT_REG64,  /* warning: value is hardcoded from TOK_ASM_xxx */
  63 #endif
  64     OPT_MMX,    /* warning: value is hardcoded from TOK_ASM_xxx */
  65     OPT_SSE,    /* warning: value is hardcoded from TOK_ASM_xxx */
  66     OPT_CR,     /* warning: value is hardcoded from TOK_ASM_xxx */
  67     OPT_TR,     /* warning: value is hardcoded from TOK_ASM_xxx */
  68     OPT_DB,     /* warning: value is hardcoded from TOK_ASM_xxx */
  69     OPT_SEG,
  70     OPT_ST,
  71     OPT_IM8,
  72     OPT_IM8S,
  73     OPT_IM16,
  74     OPT_IM32,
  75 #ifdef TCC_TARGET_X86_64
  76     OPT_IM64,
  77 #endif
  78     OPT_EAX,    /* %al, %ax, %eax or %rax register */
  79     OPT_ST0,    /* %st(0) register */
  80     OPT_CL,     /* %cl register */
  81     OPT_DX,     /* %dx register */
  82     OPT_ADDR,   /* OP_EA with only offset */
  83     OPT_INDIR,  /* *(expr) */
  84     /* composite types */
  85     OPT_COMPOSITE_FIRST,
  86     OPT_IM,     /* IM8 | IM16 | IM32 | IM64 */
  87     OPT_REG,    /* REG8 | REG16 | REG32 | REG64 */
  88     OPT_REGW,   /* REG16 | REG32 | REG64 */
  89     OPT_IMW,    /* IM16 | IM32 | IM64 */
  90 #ifdef TCC_TARGET_X86_64
  91     OPT_IMNO64, /* IM16 | IM32 */
  92 #endif
  93     /* can be ored with any OPT_xxx */
  94     OPT_EA = 0x80
  95 };
  96
  97 #define OP_REG8   (1 << OPT_REG8)
  98 #define OP_REG16  (1 << OPT_REG16)
  99 #define OP_REG32  (1 << OPT_REG32)
 100 #define OP_MMX    (1 << OPT_MMX)
 101 #define OP_SSE    (1 << OPT_SSE)
 102 #define OP_CR     (1 << OPT_CR)
 103 #define OP_TR     (1 << OPT_TR)
 104 #define OP_DB     (1 << OPT_DB)
 105 #define OP_SEG    (1 << OPT_SEG)
 106 #define OP_ST     (1 << OPT_ST)
 107 #define OP_IM8    (1 << OPT_IM8)
 108 #define OP_IM8S   (1 << OPT_IM8S)
 109 #define OP_IM16   (1 << OPT_IM16)
 110 #define OP_IM32   (1 << OPT_IM32)
 111 #define OP_EAX    (1 << OPT_EAX)
 112 #define OP_ST0    (1 << OPT_ST0)
 113 #define OP_CL     (1 << OPT_CL)
 114 #define OP_DX     (1 << OPT_DX)
 115 #define OP_ADDR   (1 << OPT_ADDR)
 116 #define OP_INDIR  (1 << OPT_INDIR)
 117 #ifdef TCC_TARGET_X86_64
 118 # define OP_REG64  (1 << OPT_REG64)
 119 # define OP_IM64   (1 << OPT_IM64)
 120 #else
 121 # define OP_REG64 0
 122 # define OP_IM64  0
 123 #endif
 124
 125 #define OP_EA     0x40000000
 126 #define OP_REG    (OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64)
 127
 128 #ifdef TCC_TARGET_X86_64
 129 # define OP_IM      OP_IM64
 130 # define TREG_XAX   TREG_RAX
 131 # define TREG_XCX   TREG_RCX
 132 # define TREG_XDX   TREG_RDX
 133 #else
 134 # define OP_IM      OP_IM32
 135 # define TREG_XAX   TREG_EAX
 136 # define TREG_XCX   TREG_ECX
 137 # define TREG_XDX   TREG_EDX
 138 #endif
 139
 140 typedef struct ASMInstr {
 141     uint16_t sym;
 142     uint16_t opcode;
 143     uint16_t instr_type;
 144     uint8_t nb_ops;
 145     uint8_t op_type[MAX_OPERANDS]; /* see OP_xxx */
 146 } ASMInstr;
 147
 148 typedef struct Operand {
 149     uint32_t type;
 150     int8_t  reg; /* register, -1 if none */
 151     int8_t  reg2; /* second register, -1 if none */
 152     uint8_t shift;
 153     ExprValue e;
 154 } Operand;
 155
 156 static const uint8_t reg_to_size[9] = {
 157 /*
 158     [OP_REG8] = 0,
 159     [OP_REG16] = 1,
 160     [OP_REG32] = 2,
 161 #ifdef TCC_TARGET_X86_64
 162     [OP_REG64] = 3,
 163 #endif
 164 */
 165     0, 0, 1, 0, 2, 0, 0, 0, 3
 166 };
 167
 168 #define NB_TEST_OPCODES 30
 169
 170 static const uint8_t test_bits[NB_TEST_OPCODES] = {
 171  0x00, /* o */
 172  0x01, /* no */
 173  0x02, /* b */
 174  0x02, /* c */
 175  0x02, /* nae */
 176  0x03, /* nb */
 177  0x03, /* nc */
 178  0x03, /* ae */
 179  0x04, /* e */
 180  0x04, /* z */
 181  0x05, /* ne */
 182  0x05, /* nz */
 183  0x06, /* be */
 184  0x06, /* na */
 185  0x07, /* nbe */
 186  0x07, /* a */
 187  0x08, /* s */
 188  0x09, /* ns */
 189  0x0a, /* p */
 190  0x0a, /* pe */
 191  0x0b, /* np */
 192  0x0b, /* po */
 193  0x0c, /* l */
 194  0x0c, /* nge */
 195  0x0d, /* nl */
 196  0x0d, /* ge */
 197  0x0e, /* le */
 198  0x0e, /* ng */
 199  0x0f, /* nle */
 200  0x0f, /* g */
 201 };
 202
 203 static const uint8_t segment_prefixes[] = {
 204  0x26, /* es */
 205  0x2e, /* cs */
 206  0x36, /* ss */
 207  0x3e, /* ds */
 208  0x64, /* fs */
 209  0x65  /* gs */
 210 };
 211
 212 static const ASMInstr asm_instrs[] = {
 213 #define ALT(x) x
 214 #define DEF_ASM_OP0(name, opcode)
 215 #define DEF_ASM_OP0L(name, opcode, group, instr_type) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 0 },
 216 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 1, { op0 }},
 217 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 2, { op0, op1 }},
 218 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2) { TOK_ASM_ ## name, opcode, (instr_type | group << OPC_GROUP_SHIFT), 3, { op0, op1, op2 }},
 219 #ifdef TCC_TARGET_X86_64
 220 # include "x86_64-asm.h"
 221 #else
 222 # include "i386-asm.h"
 223 #endif
 224     /* last operation */
 225     { 0, },
 226 };
 227
 228 static const uint16_t op0_codes[] = {
 229 #define ALT(x)
 230 #define DEF_ASM_OP0(x, opcode) opcode,
 231 #define DEF_ASM_OP0L(name, opcode, group, instr_type)
 232 #define DEF_ASM_OP1(name, opcode, group, instr_type, op0)
 233 #define DEF_ASM_OP2(name, opcode, group, instr_type, op0, op1)
 234 #define DEF_ASM_OP3(name, opcode, group, instr_type, op0, op1, op2)
 235 #ifdef TCC_TARGET_X86_64
 236 # include "x86_64-asm.h"
 237 #else
 238 # include "i386-asm.h"
 239 #endif
 240 };
 241
 242 #ifdef PRINTF_ASM_CODE
 243 void printf_asm_opcode(){
 244         const ASMInstr *pa;
 245         int freq[4];
 246         int op_vals[500];
 247         int nb_op_vals, i, j;
 248         nb_op_vals = 0;
 249         memset(freq, 0, sizeof(freq));
 250         for(pa = asm_instrs; pa->sym != 0; pa++) {
 251                 freq[pa->nb_ops]++;
 252                 for(i=0;i<pa->nb_ops;i++) {
 253                         for(j=0;j<nb_op_vals;j++) {
 254                                 if (pa->op_type[i] == op_vals[j])
 255                                         goto found;
 256                         }
 257                         op_vals[nb_op_vals++] = pa->op_type[i];
 258                 found: ;
 259                 }
 260         }
 261         for(i=0;i<nb_op_vals;i++) {
 262                 int v = op_vals[i];
 263                 if ((v & (v - 1)) != 0)
 264                         printf("%3d: %08x\n", i, v);
 265         }
 266         printf("size=%d nb=%d f0=%d f1=%d f2=%d f3=%d\n",
 267                 (int)sizeof(asm_instrs), (int)sizeof(asm_instrs) / sizeof(ASMInstr),
 268                 freq[0], freq[1], freq[2], freq[3]);
 269 }
 270 #endif
 271
 272 static inline int get_reg_shift(TCCState *s1)
 273 {
 274     int shift, v;
 275 #ifdef I386_ASM_16
 276     if (s1->seg_size == 16)
 277         tcc_error("invalid effective address");
 278 #endif
 279     v = asm_int_expr(s1);
 280     switch(v) {
 281     case 1:
 282         shift = 0;
 283         break;
 284     case 2:
 285         shift = 1;
 286         break;
 287     case 4:
 288         shift = 2;
 289         break;
 290     case 8:
 291         shift = 3;
 292         break;
 293     default:
 294         expect("1, 2, 4 or 8 constant");
 295         shift = 0;
 296         break;
 297     }
 298     return shift;
 299 }
 300
 301 static int asm_parse_reg(void)
 302 {
 303     int reg = 0;
 304     if (tok != '%')
 305         goto error_32;
 306     next();
 307     if (tok >= TOK_ASM_eax && tok <= TOK_ASM_edi) {
 308         reg = tok - TOK_ASM_eax;
 309 #ifdef TCC_TARGET_X86_64
 310     } else if (tok >= TOK_ASM_rax && tok <= TOK_ASM_rdi) {
 311         reg = tok - TOK_ASM_rax;
 312 #endif
 313 #ifdef I386_ASM_16
 314     } else if (tok >= TOK_ASM_ax && tok <= TOK_ASM_di) {
 315         reg = tok - TOK_ASM_ax;
 316 #endif
 317     } else {
 318     error_32:
 319         expect("register");
 320     }
 321     next();
 322     return reg;
 323 }
 324
 325 static void parse_operand(TCCState *s1, Operand *op)
 326 {
 327     ExprValue e;
 328     int reg, indir;
 329     const char *p;
 330
 331     indir = 0;
 332     if (tok == '*') {
 333         next();
 334         indir = OP_INDIR;
 335     }
 336
 337     if (tok == '%') {
 338         next();
 339         if (tok >= TOK_ASM_al && tok <= TOK_ASM_db7) {
 340             reg = tok - TOK_ASM_al;
 341             op->type = 1 << (reg >> 3); /* WARNING: do not change constant order */
 342             op->reg = reg & 7;
 343             if ((op->type & OP_REG) && op->reg == TREG_XAX)
 344                 op->type |= OP_EAX;
 345             else if (op->type == OP_REG8 && op->reg == TREG_XCX)
 346                 op->type |= OP_CL;
 347             else if (op->type == OP_REG16 && op->reg == TREG_XDX)
 348                 op->type |= OP_DX;
 349         } else if (tok >= TOK_ASM_dr0 && tok <= TOK_ASM_dr7) {
 350             op->type = OP_DB;
 351             op->reg = tok - TOK_ASM_dr0;
 352         } else if (tok >= TOK_ASM_es && tok <= TOK_ASM_gs) {
 353             op->type = OP_SEG;
 354             op->reg = tok - TOK_ASM_es;
 355         } else if (tok == TOK_ASM_st) {
 356             op->type = OP_ST;
 357             op->reg = 0;
 358             next();
 359             if (tok == '(') {
 360                 next();
 361                 if (tok != TOK_PPNUM)
 362                     goto reg_error;
 363                 p = tokc.cstr->data;
 364                 reg = p[0] - '0';
 365                 if ((unsigned)reg >= 8 || p[1] != '\0')
 366                     goto reg_error;
 367                 op->reg = reg;
 368                 next();
 369                 skip(')');
 370             }
 371             if (op->reg == 0)
 372                 op->type |= OP_ST0;
 373             goto no_skip;
 374         } else {
 375         reg_error:
 376             tcc_error("unknown register");
 377         }
 378         next();
 379     no_skip: ;
 380     } else if (tok == '$') {
 381         /* constant value */
 382         next();
 383         asm_expr(s1, &e);
 384         op->type = OP_IM;
 385         op->e.v = e.v;
 386         op->e.sym = e.sym;
 387         if (!op->e.sym) {
 388             if (op->e.v == (uint8_t)op->e.v)
 389                 op->type |= OP_IM8;
 390             if (op->e.v == (int8_t)op->e.v)
 391                 op->type |= OP_IM8S;
 392             if (op->e.v == (uint16_t)op->e.v)
 393                 op->type |= OP_IM16;
 394 #ifdef TCC_TARGET_X86_64
 395             if (op->e.v == (uint32_t)op->e.v)
 396                 op->type |= OP_IM32;
 397 #endif
 398         }
 399     } else {
 400         /* address(reg,reg2,shift) with all variants */
 401         op->type = OP_EA;
 402         op->reg = -1;
 403         op->reg2 = -1;
 404         op->shift = 0;
 405         if (tok != '(') {
 406             asm_expr(s1, &e);
 407             op->e.v = e.v;
 408             op->e.sym = e.sym;
 409         } else {
 410             next();
 411             if (tok == '%') {
 412                 unget_tok('(');
 413                 op->e.v = 0;
 414                 op->e.sym = NULL;
 415             } else {
 416                 /* bracketed offset expression */
 417                 asm_expr(s1, &e);
 418                 if (tok != ')')
 419                     expect(")");
 420                 next();
 421                 op->e.v = e.v;
 422                 op->e.sym = e.sym;
 423             }
 424         }
 425         if (tok == '(') {
 426             next();
 427             if (tok != ',') {
 428                 op->reg = asm_parse_reg();
 429             }
 430             if (tok == ',') {
 431                 next();
 432                 if (tok != ',') {
 433                     op->reg2 = asm_parse_reg();
 434                 }
 435                 if (tok == ',') {
 436                     next();
 437                     op->shift = get_reg_shift(s1);
 438                 }
 439             }
 440             skip(')');
 441         }
 442         if (op->reg == -1 && op->reg2 == -1)
 443             op->type |= OP_ADDR;
 444     }
 445     op->type |= indir;
 446 }
 447
 448 /* XXX: unify with C code output ? */
 449 ST_FUNC void gen_expr32(ExprValue *pe)
 450 {
 451     gen_addr32(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
 452 }
 453
 454 #ifdef TCC_TARGET_X86_64
 455 static void gen_expr64(ExprValue *pe)
 456 {
 457     gen_addr64(pe->sym ? VT_SYM : 0, pe->sym, pe->v);
 458 }
 459 #endif
 460
 461 /* XXX: unify with C code output ? */
 462 static void gen_disp32(ExprValue *pe)
 463 {
 464     Sym *sym = pe->sym;
 465     if (sym && sym->r == cur_text_section->sh_num) {
 466         /* same section: we can output an absolute value. Note
 467            that the TCC compiler behaves differently here because
 468            it always outputs a relocation to ease (future) code
 469            elimination in the linker */
 470         gen_le32(pe->v + sym->jnext - ind - 4);
 471     } else {
 472         if (sym && sym->type.t == VT_VOID) {
 473             sym->type.t = VT_FUNC;
 474             sym->type.ref = NULL;
 475         }
 476         gen_addrpc32(VT_SYM, sym, pe->v);
 477     }
 478 }
 479
 480 #ifdef I386_ASM_16
 481 static void gen_expr16(ExprValue *pe)
 482 {
 483     if (pe->sym)
 484         greloc(cur_text_section, pe->sym, ind, R_386_16);
 485     gen_le16(pe->v);
 486 }
 487 static void gen_disp16(ExprValue *pe)
 488 {
 489     Sym *sym;
 490     sym = pe->sym;
 491     if (sym) {
 492         if (sym->r == cur_text_section->sh_num) {
 493             /* same section: we can output an absolute value. Note
 494                that the TCC compiler behaves differently here because
 495                it always outputs a relocation to ease (future) code
 496                elimination in the linker */
 497             gen_le16(pe->v + sym->jnext - ind - 2);
 498         } else {
 499             greloc(cur_text_section, sym, ind, R_386_PC16);
 500             gen_le16(pe->v - 2);
 501         }
 502     } else {
 503         /* put an empty PC32 relocation */
 504         put_elf_reloc(symtab_section, cur_text_section,
 505                       ind, R_386_PC16, 0);
 506         gen_le16(pe->v - 2);
 507     }
 508 }
 509 #endif
 510
 511 /* generate the modrm operand */
 512 static inline void asm_modrm(int reg, Operand *op)
 513 {
 514     int mod, reg1, reg2, sib_reg1;
 515
 516     if (op->type & (OP_REG | OP_MMX | OP_SSE)) {
 517         g(0xc0 + (reg << 3) + op->reg);
 518     } else if (op->reg == -1 && op->reg2 == -1) {
 519         /* displacement only */
 520 #ifdef I386_ASM_16
 521         if (tcc_state->seg_size == 16) {
 522             g(0x06 + (reg << 3));
 523             gen_expr16(&op->e);
 524         } else if (tcc_state->seg_size == 32)
 525 #endif
 526         {
 527             g(0x05 + (reg << 3));
 528             gen_expr32(&op->e);
 529         }
 530     } else {
 531         sib_reg1 = op->reg;
 532         /* fist compute displacement encoding */
 533         if (sib_reg1 == -1) {
 534             sib_reg1 = 5;
 535             mod = 0x00;
 536         } else if (op->e.v == 0 && !op->e.sym && op->reg != 5) {
 537             mod = 0x00;
 538         } else if (op->e.v == (int8_t)op->e.v && !op->e.sym) {
 539             mod = 0x40;
 540         } else {
 541             mod = 0x80;
 542         }
 543         /* compute if sib byte needed */
 544         reg1 = op->reg;
 545         if (op->reg2 != -1)
 546             reg1 = 4;
 547 #ifdef I386_ASM_16
 548         if (tcc_state->seg_size == 32) {
 549 #endif
 550         g(mod + (reg << 3) + reg1);
 551         if (reg1 == 4) {
 552             /* add sib byte */
 553             reg2 = op->reg2;
 554             if (reg2 == -1)
 555                 reg2 = 4; /* indicate no index */
 556             g((op->shift << 6) + (reg2 << 3) + sib_reg1);
 557         }
 558 #ifdef I386_ASM_16
 559         } else if (tcc_state->seg_size == 16) {
 560             /* edi = 7, esi = 6 --> di = 5, si = 4 */
 561             if ((reg1 == 6) || (reg1 == 7)) {
 562                 reg1 -= 2;
 563             /* ebx = 3 --> bx = 7 */
 564             } else if (reg1 == 3) {
 565                 reg1 = 7;
 566             /* o32 = 5 --> o16 = 6 */
 567             } else if (reg1 == 5) {
 568                 reg1 = 6;
 569             /* sib not valid in 16-bit mode */
 570             } else if (reg1 == 4) {
 571                 reg2 = op->reg2;
 572                 /* bp + si + offset */
 573                 if ((sib_reg1 == 5) && (reg2 == 6)) {
 574                     reg1 = 2;
 575                 /* bp + di + offset */
 576                 } else if ((sib_reg1 == 5) && (reg2 == 7)) {
 577                     reg1 = 3;
 578                 /* bx + si + offset */
 579                 } else if ((sib_reg1 == 3) && (reg2 == 6)) {
 580                     reg1 = 0;
 581                 /* bx + di + offset */
 582                 } else if ((sib_reg1 == 3) && (reg2 == 7)) {
 583                     reg1 = 1;
 584                 } else {
 585                     tcc_error("invalid effective address");
 586                 }
 587                 if (op->e.v == 0)
 588                     mod = 0;
 589             } else {
 590                 tcc_error("invalid register");
 591             }
 592             g(mod + (reg << 3) + reg1);
 593         }
 594 #endif
 595         /* add offset */
 596         if (mod == 0x40) {
 597             g(op->e.v);
 598         } else if (mod == 0x80 || op->reg == -1) {
 599 #ifdef I386_ASM_16
 600             if (tcc_state->seg_size == 16)
 601                 gen_expr16(&op->e);
 602             else if (tcc_state->seg_size == 32)
 603 #endif
 604                 gen_expr32(&op->e);
 605         }
 606     }
 607 }
 608
 609 ST_FUNC void asm_opcode(TCCState *s1, int opcode)
 610 {
 611     const ASMInstr *pa;
 612     int i, modrm_index, reg, v, op1, is_short_jmp, seg_prefix;
 613     int nb_ops, s;
 614     Operand ops[MAX_OPERANDS], *pop;
 615     int op_type[3]; /* decoded op type */
 616 #ifdef I386_ASM_16
 617     static int a32 = 0, o32 = 0, addr32 = 0, data32 = 0;
 618 #endif
 619
 620     /* force synthetic ';' after prefix instruction, so we can handle */
 621     /* one-line things like "rep stosb" instead of only "rep\nstosb" */
 622     if (opcode >= TOK_ASM_wait && opcode <= TOK_ASM_repnz)
 623         unget_tok(';');
 624
 625     /* get operands */
 626     pop = ops;
 627     nb_ops = 0;
 628     seg_prefix = 0;
 629     for(;;) {
 630         if (tok == ';' || tok == TOK_LINEFEED)
 631             break;
 632         if (nb_ops >= MAX_OPERANDS) {
 633             tcc_error("incorrect number of operands");
 634         }
 635         parse_operand(s1, pop);
 636         if (tok == ':') {
 637            if (pop->type != OP_SEG || seg_prefix)
 638                tcc_error("incorrect prefix");
 639            seg_prefix = segment_prefixes[pop->reg];
 640            next();
 641            parse_operand(s1, pop);
 642 #ifndef I386_ASM_16
 643            if (!(pop->type & OP_EA)) {
 644                tcc_error("segment prefix must be followed by memory reference");
 645            }
 646 #endif
 647         }
 648         pop++;
 649         nb_ops++;
 650         if (tok != ',')
 651             break;
 652         next();
 653     }
 654
 655     is_short_jmp = 0;
 656     s = 0; /* avoid warning */
 657
 658     /* optimize matching by using a lookup table (no hashing is needed
 659        !) */
 660     for(pa = asm_instrs; pa->sym != 0; pa++) {
 661         s = 0;
 662         if (pa->instr_type & OPC_FARITH) {
 663             v = opcode - pa->sym;
 664             if (!((unsigned)v < 8 * 6 && (v % 6) == 0))
 665                 continue;
 666         } else if (pa->instr_type & OPC_ARITH) {
 667             if (!(opcode >= pa->sym && opcode < pa->sym + 8*NBWLX))
 668                 continue;
 669             s = (opcode - pa->sym) % NBWLX;
 670         } else if (pa->instr_type & OPC_SHIFT) {
 671             if (!(opcode >= pa->sym && opcode < pa->sym + 7*NBWLX))
 672                 continue;
 673             s = (opcode - pa->sym) % NBWLX;
 674         } else if (pa->instr_type & OPC_TEST) {
 675             if (!(opcode >= pa->sym && opcode < pa->sym + NB_TEST_OPCODES))
 676                 continue;
 677         } else if (pa->instr_type & OPC_B) {
 678             if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX))
 679                 continue;
 680             s = opcode - pa->sym;
 681         } else if (pa->instr_type & OPC_WLX) {
 682             if (!(opcode >= pa->sym && opcode < pa->sym + NBWLX-1))
 683                 continue;
 684             s = opcode - pa->sym + 1;
 685         } else {
 686             if (pa->sym != opcode)
 687                 continue;
 688         }
 689         if (pa->nb_ops != nb_ops)
 690             continue;
 691         /* now decode and check each operand */
 692         for(i = 0; i < nb_ops; i++) {
 693             int op1, op2;
 694             op1 = pa->op_type[i];
 695             op2 = op1 & 0x1f;
 696             switch(op2) {
 697             case OPT_IM:
 698                 v = OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64;
 699                 break;
 700             case OPT_REG:
 701                 v = OP_REG8 | OP_REG16 | OP_REG32 | OP_REG64;
 702                 break;
 703             case OPT_REGW:
 704                 v = OP_REG16 | OP_REG32 | OP_REG64;
 705                 break;
 706             case OPT_IMW:
 707                 v = OP_IM16 | OP_IM32 | OP_IM64;
 708                 break;
 709 #ifdef TCC_TARGET_X86_64
 710             case OPT_IMNO64:
 711                 v = OP_IM16 | OP_IM32;
 712                 break;
 713 #endif
 714             default:
 715                 v = 1 << op2;
 716                 break;
 717             }
 718             if (op1 & OPT_EA)
 719                 v |= OP_EA;
 720             op_type[i] = v;
 721             if ((ops[i].type & v) == 0)
 722                 goto next;
 723         }
 724         /* all is matching ! */
 725         break;
 726     next: ;
 727     }
 728     if (pa->sym == 0) {
 729         if (opcode >= TOK_ASM_first && opcode <= TOK_ASM_last) {
 730             int b;
 731             b = op0_codes[opcode - TOK_ASM_first];
 732 #ifdef I386_ASM_16
 733             if (opcode == TOK_ASM_o32) {
 734                 if (s1->seg_size == 32)
 735                     tcc_error("incorrect prefix");
 736                 else
 737                     o32 = data32 = 1;
 738             } else if (opcode == TOK_ASM_a32) {
 739                 if (s1->seg_size == 32)
 740                     tcc_error("incorrect prefix");
 741                 else
 742                     a32 = addr32 = 1;
 743             }
 744 #endif
 745             if (b & 0xff00)
 746                 g(b >> 8);
 747             g(b);
 748             return;
 749                 } else if (opcode <= TOK_ASM_alllast) {
 750             tcc_error("bad operand with opcode '%s'", get_tok_str(opcode, NULL));
 751         } else {
 752             tcc_error("unknown opcode '%s'",
 753                   get_tok_str(opcode, NULL));
 754         }
 755     }
 756     /* if the size is unknown, then evaluate it (OPC_B or OPC_WL case) */
 757     if (s == NBWLX-1) {
 758         for(i = 0; s == NBWLX-1 && i < nb_ops; i++) {
 759             if ((ops[i].type & OP_REG) && !(op_type[i] & (OP_CL | OP_DX)))
 760                 s = reg_to_size[ops[i].type & OP_REG];
 761         }
 762         if (s == NBWLX-1) {
 763             if ((opcode == TOK_ASM_push || opcode == TOK_ASM_pop) &&
 764                 (ops[0].type & (OP_SEG | OP_IM8S | OP_IM32 | OP_IM64)))
 765                 s = 2;
 766             else
 767                 tcc_error("cannot infer opcode suffix");
 768         }
 769     }
 770
 771 #ifdef I386_ASM_16
 772     for(i = 0; i < nb_ops; i++) {
 773         if (ops[i].type & OP_REG32) {
 774             if (s1->seg_size == 16)
 775                 o32 = 1;
 776         } else if (!(ops[i].type & OP_REG32)) {
 777             if (s1->seg_size == 32)
 778                 o32 = 1;
 779         }
 780     }
 781
 782
 783     if (s == 1 || (pa->instr_type & OPC_D16)) {
 784         if (s1->seg_size == 32)
 785             o32 = 1;
 786     } else if (s == 2) {
 787         if (s1->seg_size == 16) {
 788             if (!(pa->instr_type & OPC_D16))
 789             o32 = 1;
 790         }
 791     }
 792
 793     /* generate a16/a32 prefix if needed */
 794     if ((a32 == 1) && (addr32 == 0))
 795         g(0x67);
 796     /* generate o16/o32 prefix if needed */
 797     if ((o32 == 1) && (data32 == 0))
 798         g(0x66);
 799
 800     addr32 = data32 = 0;
 801 #else
 802     /* generate data16 prefix if needed */
 803     if (s == 1 || (pa->instr_type & OPC_D16))
 804         g(0x66);
 805 #ifdef TCC_TARGET_X86_64
 806     else if (s == 3) {
 807         /* generate REX prefix */
 808         if ((opcode != TOK_ASM_push && opcode != TOK_ASM_pop)
 809             || !(ops[0].type & OP_REG64))
 810             g(0x48);
 811     }
 812 #endif
 813 #endif
 814
 815     /* now generates the operation */
 816     if (pa->instr_type & OPC_FWAIT)
 817         g(0x9b);
 818     if (seg_prefix)
 819         g(seg_prefix);
 820
 821     v = pa->opcode;
 822     if ((v == 0x69 || v == 0x6b) && nb_ops == 2) {
 823         /* kludge for imul $im, %reg */
 824         nb_ops = 3;
 825         ops[2] = ops[1];
 826         op_type[2] = op_type[1];
 827     } else if (v == 0xcd && ops[0].e.v == 3 && !ops[0].e.sym) {
 828         v--; /* int $3 case */
 829         nb_ops = 0;
 830     } else if ((v == 0x06 || v == 0x07)) {
 831         if (ops[0].reg >= 4) {
 832             /* push/pop %fs or %gs */
 833             v = 0x0fa0 + (v - 0x06) + ((ops[0].reg - 4) << 3);
 834         } else {
 835             v += ops[0].reg << 3;
 836         }
 837         nb_ops = 0;
 838     } else if (v <= 0x05) {
 839         /* arith case */
 840         v += ((opcode - TOK_ASM_addb) / NBWLX) << 3;
 841     } else if ((pa->instr_type & (OPC_FARITH | OPC_MODRM)) == OPC_FARITH) {
 842         /* fpu arith case */
 843         v += ((opcode - pa->sym) / 6) << 3;
 844     }
 845     if (pa->instr_type & OPC_REG) {
 846         for(i = 0; i < nb_ops; i++) {
 847             if (op_type[i] & (OP_REG | OP_ST)) {
 848                 v += ops[i].reg;
 849                 break;
 850             }
 851         }
 852         /* mov $im, %reg case */
 853         if (pa->opcode == 0xb0 && s >= 1)
 854             v += 7;
 855     }
 856     if (pa->instr_type & OPC_B)
 857         v += s >= 1;
 858     if (pa->instr_type & OPC_TEST)
 859         v += test_bits[opcode - pa->sym];
 860     if (pa->instr_type & OPC_SHORTJMP) {
 861         Sym *sym;
 862         int jmp_disp;
 863
 864         /* see if we can really generate the jump with a byte offset */
 865         sym = ops[0].e.sym;
 866         if (!sym)
 867             goto no_short_jump;
 868         if (sym->r != cur_text_section->sh_num)
 869             goto no_short_jump;
 870         jmp_disp = ops[0].e.v + sym->jnext - ind - 2;
 871         if (jmp_disp == (int8_t)jmp_disp) {
 872             /* OK to generate jump */
 873             is_short_jmp = 1;
 874             ops[0].e.v = jmp_disp;
 875         } else {
 876         no_short_jump:
 877             if (pa->instr_type & OPC_JMP) {
 878                 /* long jump will be allowed. need to modify the
 879                    opcode slightly */
 880                 if (v == 0xeb)
 881                     v = 0xe9;
 882                 else
 883                     v += 0x0f10;
 884             } else {
 885                 tcc_error("invalid displacement");
 886             }
 887         }
 888     }
 889     op1 = v >> 8;
 890     if (op1)
 891         g(op1);
 892     g(v);
 893
 894     /* search which operand will used for modrm */
 895     modrm_index = 0;
 896     if (pa->instr_type & OPC_SHIFT) {
 897         reg = (opcode - pa->sym) / NBWLX;
 898         if (reg == 6)
 899             reg = 7;
 900     } else if (pa->instr_type & OPC_ARITH) {
 901         reg = (opcode - pa->sym) / NBWLX;
 902     } else if (pa->instr_type & OPC_FARITH) {
 903         reg = (opcode - pa->sym) / 6;
 904     } else {
 905         reg = (pa->instr_type >> OPC_GROUP_SHIFT) & 7;
 906     }
 907     if (pa->instr_type & OPC_MODRM) {
 908         /* first look for an ea operand */
 909         for(i = 0;i < nb_ops; i++) {
 910             if (op_type[i] & OP_EA)
 911                 goto modrm_found;
 912         }
 913         /* then if not found, a register or indirection (shift instructions) */
 914         for(i = 0;i < nb_ops; i++) {
 915             if (op_type[i] & (OP_REG | OP_MMX | OP_SSE | OP_INDIR))
 916                 goto modrm_found;
 917         }
 918 #ifdef ASM_DEBUG
 919         tcc_error("bad op table");
 920 #endif
 921     modrm_found:
 922         modrm_index = i;
 923         /* if a register is used in another operand then it is
 924            used instead of group */
 925         for(i = 0;i < nb_ops; i++) {
 926             v = op_type[i];
 927             if (i != modrm_index &&
 928                 (v & (OP_REG | OP_MMX | OP_SSE | OP_CR | OP_TR | OP_DB | OP_SEG))) {
 929                 reg = ops[i].reg;
 930                 break;
 931             }
 932         }
 933
 934         asm_modrm(reg, &ops[modrm_index]);
 935     }
 936
 937     /* emit constants */
 938 #ifndef TCC_TARGET_X86_64
 939     if (pa->opcode == 0x9a || pa->opcode == 0xea) {
 940         /* ljmp or lcall kludge */
 941 #ifdef I386_ASM_16
 942         if (s1->seg_size == 16 && o32 == 0)
 943             gen_expr16(&ops[1].e);
 944         else
 945 #endif
 946             gen_expr32(&ops[1].e);
 947         if (ops[0].e.sym)
 948             tcc_error("cannot relocate");
 949         gen_le16(ops[0].e.v);
 950         return;
 951     }
 952 #endif
 953     for(i = 0;i < nb_ops; i++) {
 954         v = op_type[i];
 955         if (v & (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64 | OP_IM8S | OP_ADDR)) {
 956             /* if multiple sizes are given it means we must look
 957                at the op size */
 958             if ((v | OP_IM8 | OP_IM64) == (OP_IM8 | OP_IM16 | OP_IM32 | OP_IM64)) {
 959                 if (s == 0)
 960                     v = OP_IM8;
 961                 else if (s == 1)
 962                     v = OP_IM16;
 963                 else if (s == 2 || (v & OP_IM64) == 0)
 964                     v = OP_IM32;
 965                 else
 966                     v = OP_IM64;
 967             }
 968             if (v & (OP_IM8 | OP_IM8S)) {
 969                 if (ops[i].e.sym)
 970                     goto error_relocate;
 971                 g(ops[i].e.v);
 972             } else if (v & OP_IM16) {
 973 #ifdef I386_ASM_16
 974                 if (s1->seg_size == 16)
 975                     gen_expr16(&ops[i].e);
 976                 else
 977 #endif
 978                 if (ops[i].e.sym)
 979                 error_relocate:
 980                     tcc_error("cannot relocate");
 981                 else
 982                     gen_le16(ops[i].e.v);
 983             } else {
 984                 if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
 985                     if (is_short_jmp)
 986                         g(ops[i].e.v);
 987 #ifdef I386_ASM_16
 988                     else if (s1->seg_size == 16)
 989                         gen_disp16(&ops[i].e);
 990 #endif
 991                     else
 992                         gen_disp32(&ops[i].e);
 993                 } else {
 994 #ifdef I386_ASM_16
 995                     if (s1->seg_size == 16 && !((o32 == 1) && (v & OP_IM32)))
 996                         gen_expr16(&ops[i].e);
 997                     else
 998 #endif
 999 #ifdef TCC_TARGET_X86_64
1000                     if (v & OP_IM64)
1001                         gen_expr64(&ops[i].e);
1002                     else
1003 #endif
1004                         gen_expr32(&ops[i].e);
1005                 }
1006             }
1007 #ifdef I386_ASM_16
1008         } else if (v & (OP_REG16 | OP_REG32)) {
1009             if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
1010                 /* jmp $r */
1011                 g(0xE0 + ops[i].reg);
1012             }
1013 #endif
1014 #ifdef TCC_TARGET_X86_64
1015         } else if (v & (OP_REG32 | OP_REG64)) {
1016             if (pa->instr_type & (OPC_JMP | OPC_SHORTJMP)) {
1017                 /* jmp $r */
1018                 g(0xE0 + ops[i].reg);
1019             }
1020 #endif
1021         }
1022     }
1023 #ifdef I386_ASM_16
1024     a32 = o32 = 0;
1025 #endif
1026 }
1027
1028 /* return the constraint priority (we allocate first the lowest
1029    numbered constraints) */
1030 static inline int constraint_priority(const char *str)
1031 {
1032     int priority, c, pr;
1033
1034     /* we take the lowest priority */
1035     priority = 0;
1036     for(;;) {
1037         c = *str;
1038         if (c == '\0')
1039             break;
1040         str++;
1041         switch(c) {
1042         case 'A':
1043             pr = 0;
1044             break;
1045         case 'a':
1046         case 'b':
1047         case 'c':
1048         case 'd':
1049         case 'S':
1050         case 'D':
1051             pr = 1;
1052             break;
1053         case 'q':
1054             pr = 2;
1055             break;
1056         case 'r':
1057             pr = 3;
1058             break;
1059         case 'N':
1060         case 'M':
1061         case 'I':
1062         case 'i':
1063         case 'm':
1064         case 'g':
1065             pr = 4;
1066             break;
1067         default:
1068             tcc_error("unknown constraint '%c'", c);
1069             pr = 0;
1070         }
1071         if (pr > priority)
1072             priority = pr;
1073     }
1074     return priority;
1075 }
1076
1077 static const char *skip_constraint_modifiers(const char *p)
1078 {
1079     while (*p == '=' || *p == '&' || *p == '+' || *p == '%')
1080         p++;
1081     return p;
1082 }
1083
1084 #define REG_OUT_MASK 0x01
1085 #define REG_IN_MASK  0x02
1086
1087 #define is_reg_allocated(reg) (regs_allocated[reg] & reg_mask)
1088
1089 ST_FUNC void asm_compute_constraints(ASMOperand *operands,
1090                                     int nb_operands, int nb_outputs,
1091                                     const uint8_t *clobber_regs,
1092                                     int *pout_reg)
1093 {
1094     ASMOperand *op;
1095     int sorted_op[MAX_ASM_OPERANDS];
1096     int i, j, k, p1, p2, tmp, reg, c, reg_mask;
1097     const char *str;
1098     uint8_t regs_allocated[NB_ASM_REGS];
1099
1100     /* init fields */
1101     for(i=0; i<nb_operands; i++) {
1102         op = &operands[i];
1103         op->input_index = -1;
1104         op->ref_index = -1;
1105         op->reg = -1;
1106         op->is_memory = 0;
1107         op->is_rw = 0;
1108     }
1109     /* compute constraint priority and evaluate references to output
1110        constraints if input constraints */
1111     for(i=0; i<nb_operands; i++) {
1112         op = &operands[i];
1113         str = op->constraint;
1114         str = skip_constraint_modifiers(str);
1115         if (isnum(*str) || *str == '[') {
1116             /* this is a reference to another constraint */
1117             k = find_constraint(operands, nb_operands, str, NULL);
1118             if ((unsigned)k >= i || i < nb_outputs)
1119                 tcc_error("invalid reference in constraint %d ('%s')",
1120                       i, str);
1121             op->ref_index = k;
1122             if (operands[k].input_index >= 0)
1123                 tcc_error("cannot reference twice the same operand");
1124             operands[k].input_index = i;
1125             op->priority = 5;
1126         } else {
1127             op->priority = constraint_priority(str);
1128         }
1129     }
1130
1131     /* sort operands according to their priority */
1132     for(i=0;i<nb_operands;i++)
1133         sorted_op[i] = i;
1134     for(i=0;i<nb_operands - 1;i++) {
1135         for(j=i+1;j<nb_operands;j++) {
1136             p1 = operands[sorted_op[i]].priority;
1137             p2 = operands[sorted_op[j]].priority;
1138             if (p2 < p1) {
1139                 tmp = sorted_op[i];
1140                 sorted_op[i] = sorted_op[j];
1141                 sorted_op[j] = tmp;
1142             }
1143         }
1144     }
1145
1146     for(i = 0;i < NB_ASM_REGS; i++) {
1147         if (clobber_regs[i])
1148             regs_allocated[i] = REG_IN_MASK | REG_OUT_MASK;
1149         else
1150             regs_allocated[i] = 0;
1151     }
1152     /* esp cannot be used */
1153     regs_allocated[4] = REG_IN_MASK | REG_OUT_MASK;
1154     /* ebp cannot be used yet */
1155     regs_allocated[5] = REG_IN_MASK | REG_OUT_MASK;
1156
1157     /* allocate registers and generate corresponding asm moves */
1158     for(i=0;i<nb_operands;i++) {
1159         j = sorted_op[i];
1160         op = &operands[j];
1161         str = op->constraint;
1162         /* no need to allocate references */
1163         if (op->ref_index >= 0)
1164             continue;
1165         /* select if register is used for output, input or both */
1166         if (op->input_index >= 0) {
1167             reg_mask = REG_IN_MASK | REG_OUT_MASK;
1168         } else if (j < nb_outputs) {
1169             reg_mask = REG_OUT_MASK;
1170         } else {
1171             reg_mask = REG_IN_MASK;
1172         }
1173     try_next:
1174         c = *str++;
1175         switch(c) {
1176         case '=':
1177             goto try_next;
1178         case '+':
1179             op->is_rw = 1;
1180             /* FALL THRU */
1181         case '&':
1182             if (j >= nb_outputs)
1183                 tcc_error("'%c' modifier can only be applied to outputs", c);
1184             reg_mask = REG_IN_MASK | REG_OUT_MASK;
1185             goto try_next;
1186         case 'A':
1187             /* allocate both eax and edx */
1188             if (is_reg_allocated(TREG_XAX) ||
1189                 is_reg_allocated(TREG_XDX))
1190                 goto try_next;
1191             op->is_llong = 1;
1192             op->reg = TREG_XAX;
1193             regs_allocated[TREG_XAX] |= reg_mask;
1194             regs_allocated[TREG_XDX] |= reg_mask;
1195             break;
1196         case 'a':
1197             reg = TREG_XAX;
1198             goto alloc_reg;
1199         case 'b':
1200             reg = 3;
1201             goto alloc_reg;
1202         case 'c':
1203             reg = TREG_XCX;
1204             goto alloc_reg;
1205         case 'd':
1206             reg = TREG_XDX;
1207             goto alloc_reg;
1208         case 'S':
1209             reg = 6;
1210             goto alloc_reg;
1211         case 'D':
1212             reg = 7;
1213         alloc_reg:
1214             if (is_reg_allocated(reg))
1215                 goto try_next;
1216             goto reg_found;
1217         case 'q':
1218             /* eax, ebx, ecx or edx */
1219             for(reg = 0; reg < 4; reg++) {
1220                 if (!is_reg_allocated(reg))
1221                     goto reg_found;
1222             }
1223             goto try_next;
1224         case 'r':
1225             /* any general register */
1226             for(reg = 0; reg < 8; reg++) {
1227                 if (!is_reg_allocated(reg))
1228                     goto reg_found;
1229             }
1230             goto try_next;
1231         reg_found:
1232             /* now we can reload in the register */
1233             op->is_llong = 0;
1234             op->reg = reg;
1235             regs_allocated[reg] |= reg_mask;
1236             break;
1237         case 'i':
1238             if (!((op->vt->r & (VT_VALMASK | VT_LVAL)) == VT_CONST))
1239                 goto try_next;
1240             break;
1241         case 'I':
1242         case 'N':
1243         case 'M':
1244             if (!((op->vt->r & (VT_VALMASK | VT_LVAL | VT_SYM)) == VT_CONST))
1245                 goto try_next;
1246             break;
1247         case 'm':
1248         case 'g':
1249             /* nothing special to do because the operand is already in
1250                memory, except if the pointer itself is stored in a
1251                memory variable (VT_LLOCAL case) */
1252             /* XXX: fix constant case */
1253             /* if it is a reference to a memory zone, it must lie
1254                in a register, so we reserve the register in the
1255                input registers and a load will be generated
1256                later */
1257             if (j < nb_outputs || c == 'm') {
1258                 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1259                     /* any general register */
1260                     for(reg = 0; reg < 8; reg++) {
1261                         if (!(regs_allocated[reg] & REG_IN_MASK))
1262                             goto reg_found1;
1263                     }
1264                     goto try_next;
1265                 reg_found1:
1266                     /* now we can reload in the register */
1267                     regs_allocated[reg] |= REG_IN_MASK;
1268                     op->reg = reg;
1269                     op->is_memory = 1;
1270                 }
1271             }
1272             break;
1273         default:
1274             tcc_error("asm constraint %d ('%s') could not be satisfied",
1275                   j, op->constraint);
1276             break;
1277         }
1278         /* if a reference is present for that operand, we assign it too */
1279         if (op->input_index >= 0) {
1280             operands[op->input_index].reg = op->reg;
1281             operands[op->input_index].is_llong = op->is_llong;
1282         }
1283     }
1284
1285     /* compute out_reg. It is used to store outputs registers to memory
1286        locations references by pointers (VT_LLOCAL case) */
1287     *pout_reg = -1;
1288     for(i=0;i<nb_operands;i++) {
1289         op = &operands[i];
1290         if (op->reg >= 0 &&
1291             (op->vt->r & VT_VALMASK) == VT_LLOCAL  &&
1292             !op->is_memory) {
1293             for(reg = 0; reg < 8; reg++) {
1294                 if (!(regs_allocated[reg] & REG_OUT_MASK))
1295                     goto reg_found2;
1296             }
1297             tcc_error("could not find free output register for reloading");
1298         reg_found2:
1299             *pout_reg = reg;
1300             break;
1301         }
1302     }
1303
1304     /* print sorted constraints */
1305 #ifdef ASM_DEBUG
1306     for(i=0;i<nb_operands;i++) {
1307         j = sorted_op[i];
1308         op = &operands[j];
1309         printf("%%%d [%s]: \"%s\" r=0x%04x reg=%d\n",
1310                j,
1311                op->id ? get_tok_str(op->id, NULL) : "",
1312                op->constraint,
1313                op->vt->r,
1314                op->reg);
1315     }
1316     if (*pout_reg >= 0)
1317         printf("out_reg=%d\n", *pout_reg);
1318 #endif
1319 }
1320
1321 ST_FUNC void subst_asm_operand(CString *add_str,
1322                               SValue *sv, int modifier)
1323 {
1324     int r, reg, size, val;
1325     char buf[64];
1326
1327     r = sv->r;
1328     if ((r & VT_VALMASK) == VT_CONST) {
1329         if (!(r & VT_LVAL) && modifier != 'c' && modifier != 'n')
1330             cstr_ccat(add_str, '$');
1331         if (r & VT_SYM) {
1332             cstr_cat(add_str, get_tok_str(sv->sym->v, NULL));
1333             if (sv->c.i != 0) {
1334                 cstr_ccat(add_str, '+');
1335             } else {
1336                 return;
1337             }
1338         }
1339         val = sv->c.i;
1340         if (modifier == 'n')
1341             val = -val;
1342         snprintf(buf, sizeof(buf), "%d", sv->c.i);
1343         cstr_cat(add_str, buf);
1344     } else if ((r & VT_VALMASK) == VT_LOCAL) {
1345         snprintf(buf, sizeof(buf), "%d(%%ebp)", sv->c.i);
1346         cstr_cat(add_str, buf);
1347     } else if (r & VT_LVAL) {
1348         reg = r & VT_VALMASK;
1349         if (reg >= VT_CONST)
1350             tcc_error("internal compiler error");
1351         snprintf(buf, sizeof(buf), "(%%%s)",
1352                  get_tok_str(TOK_ASM_eax + reg, NULL));
1353         cstr_cat(add_str, buf);
1354     } else {
1355         /* register case */
1356         reg = r & VT_VALMASK;
1357         if (reg >= VT_CONST)
1358             tcc_error("internal compiler error");
1359
1360         /* choose register operand size */
1361         if ((sv->type.t & VT_BTYPE) == VT_BYTE)
1362             size = 1;
1363         else if ((sv->type.t & VT_BTYPE) == VT_SHORT)
1364             size = 2;
1365 #ifdef TCC_TARGET_X86_64
1366         else if ((sv->type.t & VT_BTYPE) == VT_LLONG)
1367             size = 8;
1368 #endif
1369         else
1370             size = 4;
1371         if (size == 1 && reg >= 4)
1372             size = 4;
1373
1374         if (modifier == 'b') {
1375             if (reg >= 4)
1376                 tcc_error("cannot use byte register");
1377             size = 1;
1378         } else if (modifier == 'h') {
1379             if (reg >= 4)
1380                 tcc_error("cannot use byte register");
1381             size = -1;
1382         } else if (modifier == 'w') {
1383             size = 2;
1384 #ifdef TCC_TARGET_X86_64
1385         } else if (modifier == 'q') {
1386             size = 8;
1387 #endif
1388         }
1389
1390         switch(size) {
1391         case -1:
1392             reg = TOK_ASM_ah + reg;
1393             break;
1394         case 1:
1395             reg = TOK_ASM_al + reg;
1396             break;
1397         case 2:
1398             reg = TOK_ASM_ax + reg;
1399             break;
1400         default:
1401             reg = TOK_ASM_eax + reg;
1402             break;
1403 #ifdef TCC_TARGET_X86_64
1404         case 8:
1405             reg = TOK_ASM_rax + reg;
1406             break;
1407 #endif
1408         }
1409         snprintf(buf, sizeof(buf), "%%%s", get_tok_str(reg, NULL));
1410         cstr_cat(add_str, buf);
1411     }
1412 }
1413
1414 /* generate prolog and epilog code for asm statement */
1415 ST_FUNC void asm_gen_code(ASMOperand *operands, int nb_operands,
1416                          int nb_outputs, int is_output,
1417                          uint8_t *clobber_regs,
1418                          int out_reg)
1419 {
1420     uint8_t regs_allocated[NB_ASM_REGS];
1421     ASMOperand *op;
1422     int i, reg;
1423     static uint8_t reg_saved[NB_SAVED_REGS] = { 3, 6, 7 };
1424
1425     /* mark all used registers */
1426     memcpy(regs_allocated, clobber_regs, sizeof(regs_allocated));
1427     for(i = 0; i < nb_operands;i++) {
1428         op = &operands[i];
1429         if (op->reg >= 0)
1430             regs_allocated[op->reg] = 1;
1431     }
1432     if (!is_output) {
1433         /* generate reg save code */
1434         for(i = 0; i < NB_SAVED_REGS; i++) {
1435             reg = reg_saved[i];
1436             if (regs_allocated[reg]) {
1437 #ifdef I386_ASM_16
1438                 if (tcc_state->seg_size == 16)
1439                     g(0x66);
1440 #endif
1441                 g(0x50 + reg);
1442             }
1443         }
1444
1445         /* generate load code */
1446         for(i = 0; i < nb_operands; i++) {
1447             op = &operands[i];
1448             if (op->reg >= 0) {
1449                 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL &&
1450                     op->is_memory) {
1451                     /* memory reference case (for both input and
1452                        output cases) */
1453                     SValue sv;
1454                     sv = *op->vt;
1455                     sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1456                     load(op->reg, &sv);
1457                 } else if (i >= nb_outputs || op->is_rw) {
1458                     /* load value in register */
1459                     load(op->reg, op->vt);
1460                     if (op->is_llong) {
1461                         SValue sv;
1462                         sv = *op->vt;
1463                         sv.c.ul += 4;
1464                         load(TREG_XDX, &sv);
1465                     }
1466                 }
1467             }
1468         }
1469     } else {
1470         /* generate save code */
1471         for(i = 0 ; i < nb_outputs; i++) {
1472             op = &operands[i];
1473             if (op->reg >= 0) {
1474                 if ((op->vt->r & VT_VALMASK) == VT_LLOCAL) {
1475                     if (!op->is_memory) {
1476                         SValue sv;
1477                         sv = *op->vt;
1478                         sv.r = (sv.r & ~VT_VALMASK) | VT_LOCAL;
1479                         load(out_reg, &sv);
1480
1481                         sv.r = (sv.r & ~VT_VALMASK) | out_reg;
1482                         store(op->reg, &sv);
1483                     }
1484                 } else {
1485                     store(op->reg, op->vt);
1486                     if (op->is_llong) {
1487                         SValue sv;
1488                         sv = *op->vt;
1489                         sv.c.ul += 4;
1490                         store(TREG_XDX, &sv);
1491                     }
1492                 }
1493             }
1494         }
1495         /* generate reg restore code */
1496         for(i = NB_SAVED_REGS - 1; i >= 0; i--) {
1497             reg = reg_saved[i];
1498             if (regs_allocated[reg]) {
1499 #ifdef I386_ASM_16
1500                 if (tcc_state->seg_size == 16)
1501                     g(0x66);
1502 #endif
1503                 g(0x58 + reg);
1504             }
1505         }
1506     }
1507 }
1508
1509 ST_FUNC void asm_clobber(uint8_t *clobber_regs, const char *str)
1510 {
1511     int reg;
1512     TokenSym *ts;
1513
1514     if (!strcmp(str, "memory") ||
1515         !strcmp(str, "cc"))
1516         return;
1517     ts = tok_alloc(str, strlen(str));
1518     reg = ts->tok;
1519     if (reg >= TOK_ASM_eax && reg <= TOK_ASM_edi) {
1520         reg -= TOK_ASM_eax;
1521     } else if (reg >= TOK_ASM_ax && reg <= TOK_ASM_di) {
1522         reg -= TOK_ASM_ax;
1523 #ifdef TCC_TARGET_X86_64
1524     } else if (reg >= TOK_ASM_rax && reg <= TOK_ASM_rdi) {
1525         reg -= TOK_ASM_rax;
1526 #endif
1527     } else {
1528         tcc_error("invalid clobber register '%s'", str);
1529     }
1530     clobber_regs[reg] = 1;
1531 }